Remove default_nettype statements at the end of the RTL

Signed-off-by: Kareem Farid <[email protected]>
efabless · Jun 26, 2024 · 1336eeb · 1336eeb
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diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
@@ -153,4 +153,3 @@ module counter #(
     end
 
 endmodule
-`default_nettype wire
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
@@ -119,5 +119,3 @@ user_proj_example mprj (
 );
 
 endmodule	// user_project_wrapper
-
-`default_nettype wire