6800 FigForth Builds

Table of Contents 6800 FigForth Running Under SmithBUG Features 6800 FigForth in ROM Features Front Panel Controls Memory Map Links

6800 FigForth Running Under SmithBUG

Original MultiComp design is copyright by Grant Searle 2014
- Grant Searle's web site
- Grant Searle's "multicomp" page
Grant did not have a 6800 ROM
This build loads under SmithBUG
Hackaday page - see logs
Changes to this code by Doug Gilliland 2022

MC6800 CPU
- Runs at 25 MHz for internal SRAM and Peripherals
- Runs at 16.7 MHz for external SRAM
ROM - Running SmithBUG from back in the day
- FigForth Under SmithBUG repo
J3 jumper selects either built-in VDU or Serial port
VDU - ANSI terminal (default = jumper removed)
- XGA 80x25 character display
- PS/2 keyboard
MC6850 ACIA UART
1MB External SRAM
MMU1, MMU2 Memory management register control window

Original MultiComp design is copyright by Grant Searle 2014
- Grant Searle's web site
- Grant Searle's "multicomp" page
Grant did not have a 6800 ROM
- This build uses a figForth ROM
Hackaday page - see logs
Changes to this code by Doug Gilliland 2022

MC6800 CPU
- Runs at 25 MHz for internal SRAM and Peripherals
- Runs at 16.7 MHz for external SRAM
ROM - running figForth from back in the day
- FigForth In ROM repo
J3 jumper selects either built-in VDU or Serial port
VDU - ANSI terminal (default = jumper removed)
- XGA 80x25 character display
- PS/2 keyboard
MC6850 ACIA UART
1MB External SRAM
MMU1, MMU2 Memory management register control window

Wiki page
Monitors Address/Data when in Run mode
PB31 - RUN - (Upper left pushbutton) - Run/Halt (Upper left LED on for Run)
PB30 - RESET CPU
PB29 - STEP - Not yet implemented
PB28 - Not used
PB27 - CLEAR - Clears address if in Set Address Mode control mode
PB26 - INCADR - Increment address - Function depend on Enable Write Data and Set Address Mode controls
- Ignored if Set Address is selected
- If Enable Write Data is selected, Write data then Increment address
- If Enable Write Data is not selected, otherwise increment read address and read next location
PB25 - SETDAT - Enable Write Data control - Bottom row of pushbuttons controls write of data to memory
PB24 - SETADR - Set Address Mode control - Middle two rows of pushbuttons control LEDs

0x0000-0x0FFF - 4KB Internal SRAM
0x1000-0x2FFF - 6KB Internal ROM
0x3000-0x3FFF - 4KB Internal SRAM
0x4000-0x7FFF - 16KB Internal SRAM
0xA000-0xBFFF - 512KB External SRAM
- 8KB Windows, 64 frames
- MMU1 provides additional address bits
- MMU1 initialized to 0
- Set to first frame allowing memory to appear as part of Tiny BASIC contiguous space
0xC000-0xDFFF - 512KB External SRAM
- 8KB Window, 64 frames
- MMU2 provides additional address bits
- MMU2 initialized to 0
- Set to first frame allowing memory to appear as part of Tiny BASIC contiguous space
0xE000-0xEBFF - Deliberately left open to not conflict
0xFC18-0xFC19 - VDU (serSelect J3 JUMPER REMOVED)
0xFC28-0xFC19 - ACIA (serSelect J3 JUMPER INSTALLED)
0xFC30 - MMU1 Latch 7-bits
0xFC31 - MMU2 Latch 7-bits
0xFFFE-0xFFFF - ROM Reset Vector