Releases: dd86k/ddcpuid
0.21.1
Maintenance release. Contains some minor fixes in the program and manual.
Unfortunately, I have no interest in keeping this project up with newer advancements in processor features and technologies. I don't feel like supporting hybrid configs the way it is, it's incredibly silly.
May deprecate this in some time in 2024.
Changelog:
- Fixed AVX-512 detection on AMD processors.
- Fixed 5-level paging (LA57) for AMD processors.
- Fixed SSE4.1 detection.
- CPUID leaves are now bound-checked for inconsistencies under virtual guests.
0.21
Maintenance release. I also swear I will no longer touch the list switch.
Changelog
- Added: Platform field and
--platform
switch.- The baseline is what the processor is capable of, but the platform is what it is currently running.
- For example, running in a 32-bit virtual guest, my 5950X's baseline will be x86-64, but the platform will be i686.
- Added:
i386
baseline/platform labels (but good luck getting that). - Fixed: AMD core count when SMT is disabled.
- Improved: Detection of cpuid leaves for
--raw
. - Improved: Detecting and showing paravirtualization features.
- Updated:
MAX_LEAF
from 0x30 to 0x40. - Updated: "Technologies" to "Features".
- Updated: fma3 has been renamed to fma to avoid possible confusion.
- Removed: "None" outputs, ddcpuid will now print nothing at all if no features for the set was detected.
- Removed:
-a|--all
and-d|--details
options, it is now-l|--list
. - Removed: Other deprecated switches (
--table
,-S
,-s
,-l
,--level
,-d
,--details
). - Removed: (dev) Intermediate structures and simplified some internal functions.
0.20
I have refactored this project to be more workable with.
Changelog
- Added: Replaced "classification" with "baseline", with added 32-bit support.
- Adds
-b
and--baseline
command-line options. - Possible values are now
i486
(80486),i585
(Pentium),i686
(Pentium Pro),x86-64
,x86-64-v2
,x86-64-v3
, andx86-64-v4
. - This won't do much of a difference on 32-bit platforms, since the baseline for DMD is the Pentium Pro (i686).
- Also fixed times when a 64-bit processor was "classified" as 32-bit.
- Adds
- Added:
-a
and--all
as the new "detailed" view mode. - Added:
-r
and--raw
as the new "table" view mode.- Arguments to this mode can be directly invoked with
--raw 3,2
, selecting EAX=3,ECX=2.
- Arguments to this mode can be directly invoked with
- Added: Support for legacy string tables (brand index and by family/model identifiers).
- Added: Support for legacy cache topology tables (via CPUID.02h).
- Improved: ISO binary notations are now used throughout the entirety of the program.
- Improved: All string values have been transformed into lowercase, there's no need to scream.
- Improved: Cache line output formatting for clarity and sentence structure.
- Improved: When no memory size bits are available, it is simply not displayed.
- Fixed: Intel effective Family_ID.
- The extended family ID is only taken when the family ID is indifferent to 15, not 0.
- This bug existed since the first version of ddcpuid. Sorry for that.
- Fixed: x86_64 and VMX not being present in Extensions list in summary "simple" view, since they are significant extensions.
- Deprecated:
-d
,--details
,-l
,--level
,--table
,-s
, and-S
options.- These will be removed in v0.21.
v0.20.0 release candidate 3
v0.20.0-rc.3 Fix cache topology when no L1I cache
0.19.1
Maintenance release to fix SGX detection. This also adds supports for SGX1 and SGX2 bits.
When the system BIOS has the SGX feature set to "Enabled", this only enables CPUID.7h.EBX[2]. This only supports fixed-size enclaves.
When the system BIOS has the SGX feature set to "User Controlled", this enables the prior bit plus CPUID.12h.EAX[0] for SGX1, CPUID.12.EAX[1] for SGX2, CPUID.12h.EDX[7:0] for maximum size (2^n) in non-64-bit modes, and CPUID.12h.EDX[15:8] for maximum size (2^n) in 64-bit mode.
For example, my Pentium N5000 Silver supports SGX with maximum memory sizes of 2GB (32-bit) and 64GB (64-bit). The BIOS supports sizes of 32MB, 64MB, and 128MB in Enabled mode (SGX1). In User Controlled mode, all SGX1/SGX2/size information were available.
The manual also saw many corrections (thanks Jan) such as:
- Adds information about SGX1, and SGX2 including figures;
- Adds information about paravirtualization including figures;
- Fixed "Year Introduced" inconsistencies in syntax;
- Rewritten Notation section;
- And fixed SSE4.2 XML acceleration dead link. Thanks Intel.
Don't forget to check the Detailed View with -d
or --details
!
Changelog
- Added: SGX1/SGX2 (EDMM) support. When neither are available, only "SGX" is printed (fixed enclave sizes).
- Added: Legacy extensions to Summary view.
- Improved: Changed "ACPI" to "System" to better reflect the category. Also because APIC isn't an ACPI standard.
- Fixed: SGX detection.
0.19.0
This release features a revamped Summary view which is the new default. The older view has been revamped as Detailed view.
Changelog
- Added: Summary view.
- Added: Detailed view with
-d
/--details
. - Added: Physical core count.
- Added: Leaf specification with
-S
. - Added:
--table
as a synonym for-r
. - Added: SGX information (maximum enclave size in 64-bit and non-64-bit environments).
- Added: Secret.
- Fixed: Cache topology on more recent processors. Like 11th Gen Core processors.
- Fixed: Improper cache size formatting.
0.18.1
ddcpuid 0.18.0
Changelog
- ADDED Logical core count for Intel and AMD processors
- ADDED DUB library support
- ADDED (AMD) APICv support
- ADDED Vendor string validation to avoid assuming vendors
- FIXED GDC compiltation (entirely!)
- And some minor fixes and internal changes
ddcpuid 0.17.1
ddcpuid v0.17.0
Improved reading and adds support for TSXLDTRK.