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[rtl] fix source with for load unit source queue. #859

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Nov 21, 2024
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[rtl] fix source with for load unit source queue. #859

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2 changes: 1 addition & 1 deletion t1/src/lsu/LSU.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -329,7 +329,7 @@ class LSU(param: LSUParameter) extends Module {
p := VecInit(queueCount.map(_ =/= 0.U)).asUInt | dataInMSHR
}

val sourceQueue = Queue.io(UInt(param.mshrParam.sourceWidth.W), param.sourceQueueSize)
val sourceQueue = Queue.io(UInt(param.mshrParam.cacheLineIndexBits.W), param.sourceQueueSize)
// load unit connect
axi4Port.ar.valid := loadUnit.memRequest.valid && sourceQueue.enq.ready
axi4Port.ar.bits <> DontCare
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