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[rtl] add probe for write queue enq. #670

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[rtl] add probe for write queue enq. #670

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7e77659
[rtl] add probe for write queue enq.
qinjun-li Jul 8, 2024
9ba06c9
[rtl] add instructionValid for probe.
qinjun-li Jul 8, 2024
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19 changes: 13 additions & 6 deletions t1/src/Lane.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@ class LaneOM extends Class {
vfus := vfusIn
}

class LaneSlotProbe extends Bundle {
class LaneSlotProbe(instructionIndexBit: Int) extends Bundle {
val stage0EnqueueReady: Bool = Bool()
val stage0EnqueueValid: Bool = Bool()
val changingMaskSet: Bool = Bool()
Expand All @@ -41,11 +41,14 @@ class LaneSlotProbe extends Bundle {
val executionUnitVfuRequestValid: Bool = Bool()
val stage3VrfWriteReady: Bool = Bool()
val stage3VrfWriteValid: Bool = Bool()
// val probeStage1: Bool = Bool()

// write queue enq for lane
val writeQueueEnq: Bool = Bool()
val writeTag: UInt = UInt(instructionIndexBit.W)
}

class LaneProbe(slotsSize: Int) extends Bundle {
val slots = Vec(slotsSize, new LaneSlotProbe)
class LaneProbe(slotsSize: Int, instructionIndexBit: Int) extends Bundle {
val slots = Vec(slotsSize, new LaneSlotProbe(instructionIndexBit))
// @todo @Clo91eaf remove valid here, add stall := valid & !ready
val laneRequestValid: Bool = Bool()
// @todo remove it.
Expand All @@ -55,6 +58,7 @@ class LaneProbe(slotsSize: Int) extends Bundle {
// @todo replace it with VRFProbe
val vrfInstructionWriteReportReady: Bool = Bool()
val instructionFinished: UInt = UInt(slotsSize.W)
val instructionValid: UInt = UInt(slotsSize.W)
}

object LaneParameter {
Expand Down Expand Up @@ -302,8 +306,8 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
val vrfReadyToStore: Bool = IO(Output(Bool()))

@public
val probe: LaneProbe = IO(Output(Probe(new LaneProbe(parameter.chainingSize))))
val probeWire: LaneProbe = Wire(new LaneProbe(parameter.chainingSize))
val probe: LaneProbe = IO(Output(Probe(new LaneProbe(parameter.chainingSize, parameter.instructionIndexBits))))
val probeWire: LaneProbe = Wire(new LaneProbe(parameter.chainingSize, parameter.instructionIndexBits))
define(probe, ProbeValue(probeWire))
@public
val vrfProbe = IO(Output(Probe(new VRFProbe(
Expand Down Expand Up @@ -809,6 +813,8 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
probeWire.slots(index).executionUnitVfuRequestValid := executionUnit.vfuRequest.valid
probeWire.slots(index).stage3VrfWriteReady := stage3.vrfWriteRequest.ready
probeWire.slots(index).stage3VrfWriteValid := stage3.vrfWriteRequest.valid
probeWire.slots(index).writeQueueEnq := stage3.vrfWriteRequest.fire
probeWire.slots(index).writeTag := stage3.vrfWriteRequest.bits.instructionIndex
// probeWire.slots(index).probeStage1 := ???
}

Expand Down Expand Up @@ -1208,4 +1214,5 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
probeWire.lastSlotOccupied := slotOccupied.last
probeWire.vrfInstructionWriteReportReady := vrf.instructionWriteReport.ready
probeWire.instructionFinished := instructionFinished
probeWire.instructionValid := instructionValid
}
12 changes: 11 additions & 1 deletion t1/src/T1.scala
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Expand Up @@ -281,6 +281,10 @@ case class T1Parameter(

class T1Probe(param: T1Parameter) extends Bundle {
val instructionCounter: UInt = UInt(param.instructionIndexBits.W)
// write queue enq for mask unit
val writeQueueEnq: ValidIO[UInt] = Valid(UInt(param.instructionIndexBits.W))
// mask unit instruction valid
val instructionValid: UInt = UInt(param.chainingSize.W)
}

/** Top of Vector processor:
Expand Down Expand Up @@ -319,7 +323,7 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa

// TODO: this is an example of adding a new Probe
val lsuProbe = IO(Probe(new LSUProbe(parameter.lsuParameters)))
val laneProbes = Seq.tabulate(parameter.laneNumber)(laneIdx => IO(Probe(new LaneProbe(parameter.chainingSize))).suggestName(s"lane${laneIdx}Probe"))
val laneProbes = Seq.tabulate(parameter.laneNumber)(laneIdx => IO(Probe(new LaneProbe(parameter.chainingSize, parameter.instructionIndexBits))).suggestName(s"lane${laneIdx}Probe"))
val laneVrfProbes = Seq.tabulate(parameter.laneNumber)(laneIdx => IO(Probe(new VRFProbe(
parameter.laneParam.vrfParam.regNumBits,
parameter.laneParam.vrfOffsetBits,
Expand Down Expand Up @@ -1692,6 +1696,12 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
val probeWire = Wire(new T1Probe(parameter))
define(t1Probe, ProbeValue(probeWire))
probeWire.instructionCounter := instructionCounter
// maskUnitWrite maskUnitWriteReady
probeWire.writeQueueEnq.valid := maskUnitWrite.valid && maskUnitWriteReady
probeWire.writeQueueEnq.bits := maskUnitWrite.bits.instructionIndex
instructionValid := maskAnd(
!slots.last.state.sMaskUnitExecution && !slots.last.state.idle,
indexToOH(slots.last.record.instructionIndex, parameter.chainingSize)).asUInt

// new V Request from core
// val requestValidProbe: Bool = IO(Output(Probe(Bool())))
Expand Down
8 changes: 7 additions & 1 deletion t1/src/lsu/LSU.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ import chisel3.experimental.hierarchy.{Instance, Instantiate, instantiable, publ
import chisel3.probe.{Probe, ProbeValue, define}
import chisel3.util._
import chisel3.util.experimental.BitSet
import org.chipsalliance.t1.rtl.{CSRInterface, LSUBankParameter, LSURequest, LSUWriteQueueBundle, VRFReadRequest, VRFWriteRequest, firstlastHelper, indexToOH, instIndexL}
import org.chipsalliance.t1.rtl.{CSRInterface, LSUBankParameter, LSURequest, LSUWriteQueueBundle, VRFReadRequest, VRFWriteRequest, firstlastHelper, indexToOH, instIndexL, maskAnd}
import tilelink.{TLBundle, TLBundleParameter, TLChannelA, TLChannelD}

// TODO: need some idea from BankBinder
Expand Down Expand Up @@ -128,10 +128,12 @@ class MemoryWriteProbe(param: MSHRParam) extends Bundle {
}

class LSUProbe(param: LSUParameter) extends Bundle {
// lsu write queue enq probe
val slots = Vec(param.laneNumber, new LSUSlotProbe(param))
val storeUnitProbe = new MemoryWriteProbe(param.mshrParam)
val otherUnitProbe = new MemoryWriteProbe(param.mshrParam)
val reqEnq: UInt = UInt(param.lsuMSHRSize.W)
val lsuInstructionValid: UInt = UInt(param.chainingSize.W)
}

/** Load Store Unit
Expand Down Expand Up @@ -323,6 +325,10 @@ class LSU(param: LSUParameter) extends Module {

probeWire.storeUnitProbe := probe.read(storeUnit.probe)
probeWire.otherUnitProbe := probe.read(otherUnit.probe)
probeWire.lsuInstructionValid :=
maskAnd(!loadUnit.status.idle, indexToOH(loadUnit.status.instructionIndex, param.chainingSize)).asUInt |
maskAnd(!storeUnit.status.idle, indexToOH(storeUnit.status.instructionIndex, param.chainingSize)).asUInt |
maskAnd(!otherUnit.status.idle, indexToOH(otherUnit.status.instructionIndex, param.chainingSize)).asUInt

vrfWritePort.zip(writeQueueVec).foreach { case (p, q) =>
p.valid := q.io.deq.valid
Expand Down
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