[rtl] Narrow writes require a real address.

chipsalliance · Nov 26, 2024 · 03ba384 · 03ba384
1 parent 336d0ad
commit 03ba384
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/t1/src/lsu/SimpleAccessUnit.scala b/t1/src/lsu/SimpleAccessUnit.scala
@@ -843,7 +843,7 @@ class SimpleAccessUnit(param: MSHRParam) extends Module with LSUPublic {
   memReadRequest.valid        := s1Valid && sourceFree && !lsuRequestReg.instructionInformation.isStore
 
   memWriteRequest.valid        := s1Valid && sourceFree && lsuRequestReg.instructionInformation.isStore
-  memWriteRequest.bits.address := (s1Reg.address >> addressOffSetForDataPath) << addressOffSetForDataPath
+  memWriteRequest.bits.address := s1Reg.address
   memWriteRequest.bits.size    := dataEEW
   memWriteRequest.bits.data    := storeData
   memWriteRequest.bits.mask    := storeMask