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AHB/DMA fix in the testbench #278

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AHB/DMA fix in the testbench #278

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977fc49
use axi_lsu_dma_bridge in configuration with ahb
wsipak Nov 21, 2024
0b12254
don't use RV_DMA_BUS_TAG
wsipak Nov 21, 2024
2dbe0da
fix axi4<->ahb connections
wsipak Nov 22, 2024
59a55c8
cleanup
wsipak Nov 22, 2024
9550b62
ecc test passes
wsipak Nov 22, 2024
e0d170f
add todo
wsipak Nov 22, 2024
b5c52f9
reconnect lmem and dma in tb
wsipak Nov 22, 2024
f24c95a
connect lsu master to the bridge
wsipak Nov 25, 2024
21ac582
use axi lmem even with ahb configuration
wsipak Nov 25, 2024
e7f055a
fix ahb signals in the testbench
wsipak Nov 25, 2024
a692593
do not care about iccm/dccm addressing in ahb_to_axi4
wsipak Nov 25, 2024
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3 changes: 1 addition & 2 deletions design/lib/ahb_to_axi4.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -209,8 +209,7 @@ import el2_pkg::*;
assign ahb_hrdata[63:0] = buf_rdata[63:0];
assign ahb_hresp = ((ahb_htrans_q[1:0] != 2'b0) & (buf_state != IDLE) &

((~(ahb_addr_in_dccm | ahb_addr_in_iccm)) | // request not for ICCM or DCCM
((ahb_addr_in_iccm | (ahb_addr_in_dccm & ahb_hwrite_q)) & ~((ahb_hsize_q[1:0] == 2'b10) | (ahb_hsize_q[1:0] == 2'b11))) | // ICCM Rd/Wr OR DCCM Wr not the right size
(
((ahb_hsize_q[2:0] == 3'h1) & ahb_haddr_q[0]) | // HW size but unaligned
((ahb_hsize_q[2:0] == 3'h2) & (|ahb_haddr_q[1:0])) | // W size but unaligned
((ahb_hsize_q[2:0] == 3'h3) & (|ahb_haddr_q[2:0])))) | // DW size but unaligned
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4 changes: 2 additions & 2 deletions testbench/ahb_sif.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -140,7 +140,7 @@ module ahb_sif (
endmodule
`endif

`ifdef RV_BUILD_AXI4
// `ifdef RV_BUILD_AXI4
module axi_slv #(
TAGW = 1
) (
Expand Down Expand Up @@ -238,5 +238,5 @@ module axi_slv #(
end
end
endmodule
`endif
// `endif

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