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Cleanup block verfication codebase
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- Remove reduntant imports from RTL
- Assign some hanging outputs to `unused_*` wires
- Add explicit lint waivers for VeeR codebase
- Add test-specific lint waivers for test wrappers
- Build complex test design using multiple threads

Signed-off-by: Robert Szczepanski <[email protected]>
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robertszczepanski committed Nov 19, 2024
1 parent 2388ae0 commit 157ac3e
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Showing 30 changed files with 212 additions and 61 deletions.
3 changes: 2 additions & 1 deletion design/el2_veer_wrapper.sv
Original file line number Diff line number Diff line change
Expand Up @@ -886,6 +886,7 @@ import el2_pkg::*;
);


logic unused_dmi_hard_reset;
// JTAG/DMI instance
dmi_wrapper dmi_wrapper (
// JTAG signals
Expand All @@ -904,7 +905,7 @@ import el2_pkg::*;
.reg_wr_addr (dmi_addr), // Write address to Processor
.reg_en (dmi_en), // Write interface bit to Processor
.reg_wr_en (dmi_wr_en), // Write enable to Processor
.dmi_hard_reset ()
.dmi_hard_reset (unused_dmi_hard_reset)
);

// DMI core/uncore mux
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1 change: 0 additions & 1 deletion design/lib/el2_mem_if.sv
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,6 @@
//********************************************************************************


import el2_pkg::*;
interface el2_mem_if #(
`include "el2_param.vh"
) ();
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8 changes: 7 additions & 1 deletion verification/block/common.mk
Original file line number Diff line number Diff line change
Expand Up @@ -40,12 +40,18 @@ endif
# Enable processing of #delay statements
ifeq ($(SIM), verilator)
COMPILE_ARGS += --timing
COMPILE_ARGS += -Wall -Wno-fatal
COMPILE_ARGS += -Wall
COMPILE_ARGS += $(CURDIR)/config.vlt

EXTRA_ARGS += --trace --trace-structs
EXTRA_ARGS += $(VERILATOR_COVERAGE)
endif

# Include test specific Verilator config if it exists
ifneq ("$(wildcard $(TEST_DIR)/config.vlt)","")
COMPILE_ARGS += $(TEST_DIR)/config.vlt
endif

COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 10ps

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97 changes: 97 additions & 0 deletions verification/block/config.vlt
Original file line number Diff line number Diff line change
@@ -0,0 +1,97 @@
`verilator_config

// Unnamed blocks do not influence logic
lint_off -rule GENUNNAMED

// Unconnected IC memory output pins
lint_off -rule PINCONNECTEMPTY -file "*/el2_ifu_ic_mem.sv"

// These require revisit to remove multiple definitions of variables with same names
lint_off -rule VARHIDDEN -file "*/axi4_to_ahb.sv"
lint_off -rule VARHIDDEN -file "*/el2_ifu_bp_ctl.sv"
lint_off -rule VARHIDDEN -file "*/el2_ifu_mem_ctl.sv"
lint_off -rule VARHIDDEN -file "*/el2_exu_alu_ctl.sv"
lint_off -rule VARHIDDEN -file "*/el2_pic_ctrl.sv"

// Width related warning require explicit type casting
lint_off -rule WIDTHTRUNC -file "*/ahb_to_axi4.sv"
lint_off -rule WIDTHTRUNC -file "*/axi4_to_ahb.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_dma_ctrl.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_ifu_ifc_ctl.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_ifu_bp_ctl.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_ifu_aln_ctl.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_dec_decode_ctl.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_dec_ib_ctl.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_dec_tlu_ctl.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_dec_trigger.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_lib.sv"
lint_off -rule WIDTHTRUNC -file "*/beh_lib.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_lsu_bus_buffer.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_dec_pmp_ctl.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_lsu_addrcheck.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_lsu_dccm_ctl.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_lsu_dccm_mem.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_lsu_trigger.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_ifu_iccm_mem.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_ifu_mem_ctl.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_exu.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_exu_alu_ctl.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_exu_div_ctl.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_exu_mul_ctl.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_dbg.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_pic_ctrl.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_pmp.sv"
lint_off -rule WIDTHTRUNC -file "*/el2_mem_if.sv"

lint_off -rule WIDTHEXPAND -file "*/el2_exu.sv"
lint_off -rule WIDTHEXPAND -file "*/el2_pic_ctrl.sv"
lint_off -rule WIDTHEXPAND -file "*/el2_ifu_bp_ctl.sv"
lint_off -rule WIDTHEXPAND -file "*/el2_ifu_mem_ctl.sv"
lint_off -rule WIDTHEXPAND -file "*/el2_ifu_iccm_mem.sv"
lint_off -rule WIDTHEXPAND -file "*/el2_lsu_addrcheck.sv"
lint_off -rule WIDTHEXPAND -file "*/el2_lsu_bus_buffer.sv"
lint_off -rule WIDTHEXPAND -file "*/el2_lsu_stbuf.sv"
lint_off -rule WIDTHEXPAND -file "*/el2_lsu_dccm_ctl.sv"
lint_off -rule WIDTHEXPAND -file "*/el2_lsu_dccm_mem.sv"
lint_off -rule WIDTHEXPAND -file "*/el2_exu_mul_ctl.sv"
lint_off -rule WIDTHEXPAND -file "*/el2_dec_tlu_ctl.sv"
lint_off -rule WIDTHEXPAND -file "*/el2_dma_ctrl.sv"
lint_off -rule WIDTHEXPAND -file "*/el2_dbg.sv"

// Unused parameters are probably safe to remove from RTL
lint_off -rule UNUSEDPARAM -file "*/axi4_to_ahb.sv"
lint_off -rule UNUSEDPARAM -file "*/el2_ifu.sv"
lint_off -rule UNUSEDPARAM -file "*/el2_pic_ctrl.sv"
lint_off -rule UNUSEDPARAM -file "*/el2_dma_ctrl.sv"
lint_off -rule UNUSEDPARAM -file "*/el2_ifu_bp_ctl.sv"
lint_off -rule UNUSEDPARAM -file "*/el2_ifu_mem_ctl.sv"
lint_off -rule UNUSEDPARAM -file "*/el2_dec_tlu_ctl.sv"
lint_off -rule UNUSEDPARAM -file "*/el2_lsu_dccm_ctl.sv"
lint_off -rule UNUSEDPARAM -file "*/el2_lsu_dccm_mem.sv"

// Gated clock, expected latch
lint_off -rule LATCH -file "*/beh_lib.sv" -lines 781

// The Verilator reports that `core_rst_l` is being used in sync and async nets,
// pointing to `rvdff` module as a source of the problem. Since the `rvdff` looks
// unrelated to `core_rst_l`, it requires a closer investigation.
lint_off -rule SYNCASYNCNET -file "*/el2_veer.sv" -lines 35

// Logic that might be not optimal for event based model used by Verilator
lint_off -rule UNOPTFLAT -file "*/axi4_to_ahb.sv"
lint_off -rule UNOPTFLAT -file "*/el2_ifu_ifc_ctl.sv"
lint_off -rule UNOPTFLAT -file "*/el2_dec_decode_ctl.sv"
lint_off -rule UNOPTFLAT -file "*/el2_exu_mul_ctl.sv"
lint_off -rule UNOPTFLAT -file "*/el2_exu_div_ctl.sv"
lint_off -rule UNOPTFLAT -file "*/el2_lsu.sv"
lint_off -rule UNOPTFLAT -file "*/el2_lsu_lsc_ctl.sv"
lint_off -rule UNOPTFLAT -file "*/el2_pic_ctrl.sv"

// Warnings related to the generated `el2_param.vh`
lint_off -rule UNUSEDPARAM -file "*/el2_ifu_compress_ctl.sv"
lint_off -rule UNUSEDPARAM -file "*/el2_dec_gpr_ctl.sv"
lint_off -rule UNUSEDPARAM -file "*/el2_dec_trigger.sv"
lint_off -rule UNUSEDPARAM -file "*/el2_lsu_trigger.sv"
lint_off -rule UNUSEDPARAM -file "*/el2_lsu_clkdomain.sv"

lint_off -rule WIDTHTRUNC -file "*/el2_ifu_compress_ctl.sv"
8 changes: 4 additions & 4 deletions verification/block/dccm/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,8 @@ null :=
space := $(null) #
comma := ,

CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
SRCDIR := $(abspath $(CURDIR)../../../../design)
TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
SRCDIR := $(abspath $(TEST_DIR)../../../../design)

TEST_FILES = $(sort $(wildcard test_*.py))

Expand All @@ -13,12 +13,12 @@ TOPLEVEL = el2_lsu_dccm_mem_wrapper

VERILOG_SOURCES = \
$(SRCDIR)/lib/el2_mem_if.sv \
$(CURDIR)/dccm/el2_lsu_dccm_mem_wrapper.sv \
$(TEST_DIR)/el2_lsu_dccm_mem_wrapper.sv \
$(SRCDIR)/lsu/el2_lsu_dccm_mem.sv \
$(SRCDIR)/lib/mem_lib.sv

# Undefine the VERILATOR macro to make the code use actual RAM cells instead
# of simulation models
EXTRA_ARGS += -UVERILATOR

include $(CURDIR)/../common.mk
include $(TEST_DIR)/../common.mk
5 changes: 5 additions & 0 deletions verification/block/dccm/config.vlt
Original file line number Diff line number Diff line change
@@ -0,0 +1,5 @@
`verilator_config

lint_off -rule PINCONNECTEMPTY -file "*/el2_lsu_dccm_mem_wrapper.sv"

lint_off -rule WIDTHTRUNC -file "*/el2_lsu_dccm_mem_wrapper.sv"
8 changes: 4 additions & 4 deletions verification/block/dec_ib/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -2,16 +2,16 @@ null :=
space := $(null) #
comma := ,

CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
SRCDIR := $(abspath $(CURDIR)../../../../design)
TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
SRCDIR := $(abspath $(TEST_DIR)../../../../design)

TEST_FILES = $(sort $(wildcard test_*.py))

MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))
TOPLEVEL = el2_dec_ib_ctl_wrapper

VERILOG_SOURCES = \
$(CURDIR)/dec_ib/el2_dec_ib_ctl_wrapper.sv \
$(TEST_DIR)/el2_dec_ib_ctl_wrapper.sv \
$(SRCDIR)/dec/el2_dec_ib_ctl.sv

include $(CURDIR)/../common.mk
include $(TEST_DIR)/../common.mk
3 changes: 3 additions & 0 deletions verification/block/dec_ib/config.vlt
Original file line number Diff line number Diff line change
@@ -0,0 +1,3 @@
`verilator_config

lint_off -rule WIDTHTRUNC -file "*/el2_dec_ib_ctl_wrapper.sv"
8 changes: 4 additions & 4 deletions verification/block/dec_tl/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -2,16 +2,16 @@ null :=
space := $(null) #
comma := ,

CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
SRCDIR := $(abspath $(CURDIR)../../../../design)
TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
SRCDIR := $(abspath $(TEST_DIR)../../../../design)

TEST_FILES = $(sort $(wildcard test_*.py))

MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))
TOPLEVEL = el2_dec_trigger_wrapper

VERILOG_SOURCES = \
$(CURDIR)/dec_tl/el2_dec_trigger_wrapper.sv \
$(TEST_DIR)/el2_dec_trigger_wrapper.sv \
$(SRCDIR)/dec/el2_dec_trigger.sv

include $(CURDIR)/../common.mk
include $(TEST_DIR)/../common.mk
5 changes: 5 additions & 0 deletions verification/block/dec_tl/config.vlt
Original file line number Diff line number Diff line change
@@ -0,0 +1,5 @@
`verilator_config

lint_off -rule WIDTHTRUNC -file "*/el2_dec_trigger_wrapper.sv"

lint_off -rule UNUSEDPARAM -file "*/el2_dec_trigger_wrapper.sv"
6 changes: 3 additions & 3 deletions verification/block/dma/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,8 @@ null :=
space := $(null) #
comma := ,

CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
SRCDIR := $(abspath $(CURDIR)../../../../design)
TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
SRCDIR := $(abspath $(TEST_DIR)../../../../design)

TEST_FILES = $(sort $(wildcard test_*.py))

Expand All @@ -14,4 +14,4 @@ TOPLEVEL = el2_dma_ctrl
VERILOG_SOURCES = \
$(SRCDIR)/el2_dma_ctrl.sv

include $(CURDIR)/../common.mk
include $(TEST_DIR)/../common.mk
8 changes: 4 additions & 4 deletions verification/block/dmi/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -2,20 +2,20 @@ null :=
space := $(null)
comma := ,

CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
SRCDIR := $(abspath $(CURDIR)../../../../design)
TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
SRCDIR := $(abspath $(TEST_DIR)../../../../design)

TEST_FILES = $(sort $(wildcard test_*.py))

MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))
TOPLEVEL = dmi_test_wrapper

VERILOG_SOURCES = \
$(CURDIR)/dmi/dmi_test_wrapper.sv \
$(TEST_DIR)/dmi_test_wrapper.sv \
$(SRCDIR)/dmi/rvjtag_tap.v \
$(SRCDIR)/dmi/dmi_mux.v \
$(SRCDIR)/dmi/dmi_jtag_to_core_sync.v \
$(SRCDIR)/dmi/dmi_wrapper.v

include $(CURDIR)/../common.mk
include $(TEST_DIR)/../common.mk

5 changes: 5 additions & 0 deletions verification/block/dmi/config.vlt
Original file line number Diff line number Diff line change
@@ -0,0 +1,5 @@
`verilator_config

lint_off -rule WIDTHTRUNC -file "*/dmi_test_wrapper.sv"

lint_off -rule UNUSEDPARAM -file "*/dmi_test_wrapper.sv"
8 changes: 4 additions & 4 deletions verification/block/exu_alu/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -3,16 +3,16 @@ null :=
space := $(null) #
comma := ,

CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
SRCDIR := $(abspath $(CURDIR)../../../../design)
TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
SRCDIR := $(abspath $(TEST_DIR)../../../../design)

TEST_FILES = $(sort $(wildcard test_*.py))

MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))
TOPLEVEL = el2_exu_alu_ctl_wrapper

VERILOG_SOURCES = \
$(CURDIR)/exu_alu/el2_exu_alu_ctl_wrapper.sv \
$(TEST_DIR)/el2_exu_alu_ctl_wrapper.sv \
$(SRCDIR)/exu/el2_exu_alu_ctl.sv

include $(CURDIR)/../common.mk
include $(TEST_DIR)/../common.mk
5 changes: 5 additions & 0 deletions verification/block/exu_alu/config.vlt
Original file line number Diff line number Diff line change
@@ -0,0 +1,5 @@
`verilator_config

lint_off -rule WIDTHTRUNC -file "*/el2_exu_alu_ctl_wrapper.sv"

lint_off -rule UNUSEDPARAM -file "*/el2_exu_alu_ctl_wrapper.sv"
8 changes: 4 additions & 4 deletions verification/block/exu_div/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -3,16 +3,16 @@ null :=
space := $(null) #
comma := ,

CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
SRCDIR := $(abspath $(CURDIR)../../../../design)
TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
SRCDIR := $(abspath $(TEST_DIR)../../../../design)

TEST_FILES = $(sort $(wildcard test_*.py))

MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))
TOPLEVEL = el2_exu_div_ctl_wrapper

VERILOG_SOURCES = \
$(CURDIR)/exu_div/el2_exu_div_ctl_wrapper.sv \
$(TEST_DIR)/el2_exu_div_ctl_wrapper.sv \
$(SRCDIR)/exu/el2_exu_div_ctl.sv

include $(CURDIR)/../common.mk
include $(TEST_DIR)/../common.mk
5 changes: 5 additions & 0 deletions verification/block/exu_div/config.vlt
Original file line number Diff line number Diff line change
@@ -0,0 +1,5 @@
`verilator_config

lint_off -rule WIDTHTRUNC -file "*/el2_exu_div_ctl_wrapper.sv"

lint_off -rule UNUSEDPARAM -file "*/el2_exu_div_ctl_wrapper.sv"
8 changes: 4 additions & 4 deletions verification/block/exu_mul/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -3,16 +3,16 @@ null :=
space := $(null) #
comma := ,

CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
SRCDIR := $(abspath $(CURDIR)../../../../design)
TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
SRCDIR := $(abspath $(TEST_DIR)../../../../design)

TEST_FILES = $(sort $(wildcard test_*.py))

MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))
TOPLEVEL = el2_exu_mul_ctl_wrapper

VERILOG_SOURCES = \
$(CURDIR)/exu_mul/el2_exu_mul_ctl_wrapper.sv \
$(TEST_DIR)/el2_exu_mul_ctl_wrapper.sv \
$(SRCDIR)/exu/el2_exu_mul_ctl.sv

include $(CURDIR)/../common.mk
include $(TEST_DIR)/../common.mk
5 changes: 5 additions & 0 deletions verification/block/exu_mul/config.vlt
Original file line number Diff line number Diff line change
@@ -0,0 +1,5 @@
`verilator_config

lint_off -rule WIDTHTRUNC -file "*/el2_exu_mul_ctl_wrapper.sv"

lint_off -rule UNUSEDPARAM -file "*/el2_exu_mul_ctl_wrapper.sv"
8 changes: 4 additions & 4 deletions verification/block/iccm/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,8 @@ null :=
space := $(null) #
comma := ,

CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
SRCDIR := $(abspath $(CURDIR)../../../../design)
TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
SRCDIR := $(abspath $(TEST_DIR)../../../../design)

TEST_FILES = $(sort $(wildcard test_*.py))

Expand All @@ -13,12 +13,12 @@ TOPLEVEL = el2_ifu_iccm_mem_wrapper

VERILOG_SOURCES = \
$(SRCDIR)/lib/el2_mem_if.sv \
$(CURDIR)/iccm/el2_ifu_iccm_mem_wrapper.sv \
$(TEST_DIR)/el2_ifu_iccm_mem_wrapper.sv \
$(SRCDIR)/ifu/el2_ifu_iccm_mem.sv \
$(SRCDIR)/lib/mem_lib.sv

# Undefine the VERILATOR macro to make the code use actual RAM cells instead
# of simulation models
EXTRA_ARGS += -UVERILATOR

include $(CURDIR)/../common.mk
include $(TEST_DIR)/../common.mk
5 changes: 5 additions & 0 deletions verification/block/iccm/config.vlt
Original file line number Diff line number Diff line change
@@ -0,0 +1,5 @@
`verilator_config

lint_off -rule PINCONNECTEMPTY -file "*/el2_ifu_iccm_mem_wrapper.sv"

lint_off -rule WIDTHTRUNC -file "*/el2_ifu_iccm_mem_wrapper.sv"
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