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gateware: switch from clk_fs to strobe on all boards. verify ecpix also
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vk2seb committed Jun 12, 2024
1 parent 2159362 commit d9e77c5
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Showing 6 changed files with 2 additions and 38 deletions.
9 changes: 0 additions & 9 deletions gateware/boards/colorlight_i5/sysmgr.v
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,6 @@ module sysmgr (
input wire clk_in,
input wire rst_in,
output wire clk_256fs,
output wire clk_fs,
output wire rst_out
);

Expand All @@ -15,12 +14,10 @@ wire pll_reset;
wire rst_i;

reg [7:0] rst_cnt;
reg [7:0] clkdiv;

assign pll_reset = rst_in;
assign rst_i = ~rst_cnt[7];
assign rst_out = rst_i;
assign clk_fs = clkdiv[7];

`ifndef VERILATOR_LINT_ONLY

Expand Down Expand Up @@ -75,10 +72,4 @@ always @(posedge clk_in)
else if (~rst_cnt[7])
rst_cnt <= rst_cnt + 1;

always @(posedge clk_256fs)
if (rst_i)
clkdiv <= 8'h00;
else
clkdiv <= clkdiv + 1;

endmodule // sysmgr
9 changes: 0 additions & 9 deletions gateware/boards/ecpix5/sysmgr.v
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,6 @@ module sysmgr (
input wire clk_in,
input wire rst_in,
output wire clk_256fs,
output wire clk_fs,
output wire rst_out
);

Expand All @@ -15,12 +14,10 @@ wire pll_reset;
wire rst_i;

reg [7:0] rst_cnt;
reg [7:0] clkdiv;

assign rst_i = ~rst_cnt[7];
assign rst_out = rst_i;
assign pll_reset = rst_in;
assign clk_fs = clkdiv[7];

`ifndef VERILATOR_LINT_ONLY

Expand Down Expand Up @@ -71,10 +68,4 @@ always @(posedge clk_in)
else if (~rst_cnt[7])
rst_cnt <= rst_cnt + 1;

always @(posedge clk_256fs)
if (rst_i)
clkdiv <= 8'h00;
else
clkdiv <= clkdiv + 1;

endmodule // sysmgr
9 changes: 0 additions & 9 deletions gateware/boards/gatemate_evb/sysmgr.v
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,6 @@ module sysmgr (
input wire clk_in,
input wire rst_in,
output wire clk_256fs,
output wire clk_fs,
output wire rst_out
);

Expand All @@ -14,12 +13,10 @@ wire pll_reset;
wire rst_i;

reg [7:0] rst_cnt;
reg [7:0] clkdiv;

assign pll_reset = rst_in;
assign rst_i = ~rst_cnt[7];
assign rst_out = rst_i;
assign clk_fs = clkdiv[7];

`ifndef VERILATOR_LINT_ONLY

Expand All @@ -46,10 +43,4 @@ always @(posedge clk_in)
else if (~rst_cnt[7])
rst_cnt <= rst_cnt + 1;

always @(posedge clk_256fs)
if (rst_i)
clkdiv <= 8'h00;
else
clkdiv <= clkdiv + 1;

endmodule // sysmgr
9 changes: 0 additions & 9 deletions gateware/boards/pico_ice/sysmgr.v
Original file line number Diff line number Diff line change
Expand Up @@ -3,18 +3,15 @@
module sysmgr (
input wire rst_in,
output wire clk_256fs,
output wire clk_fs,
output wire rst_out
);

wire clk_12m;
wire rst_i;

reg [7:0] rst_cnt = 8'h80;
reg [7:0] clkdiv;

assign clk_256fs = clk_12m;
assign clk_fs = clkdiv[7];
assign rst_i = rst_cnt[7];

`ifndef VERILATOR_LINT_ONLY
Expand All @@ -35,12 +32,6 @@ module sysmgr (
else if (rst_cnt[7])
rst_cnt <= rst_cnt + 1;

always @(posedge clk_256fs)
if (rst_i)
clkdiv <= 8'h00;
else
clkdiv <= clkdiv + 1;

`ifndef VERILATOR_LINT_ONLY
SB_GB rst_gbuf_I (
.USER_SIGNAL_TO_GLOBAL_BUFFER(rst_i),
Expand Down
2 changes: 1 addition & 1 deletion gateware/cores/digital_echo.sv
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@
module digital_echo #(
parameter W = 16,
// Length of the echo buffers in samples.
parameter ECHO_LEN = 4096,
parameter ECHO_LEN = 4096
)(
input rst,
input clk,
Expand Down
2 changes: 1 addition & 1 deletion gateware/scripts/verilator_lint.sh
Original file line number Diff line number Diff line change
Expand Up @@ -56,6 +56,6 @@ verilator --lint-only cores/util/filter/karlsen_lpf.sv
verilator --lint-only cores/util/filter/karlsen_lpf_pipelined.sv
verilator --lint-only -Icores -Icores/util/filter filter.sv
verilator --lint-only -Icores -Icores/util pitch_shift.sv
verilator --lint-only -Icores -Icores/util stereo_echo.sv
verilator --lint-only -Icores -Icores/util digital_echo.sv
verilator --lint-only -Icores -Icores/util dc_block.sv
verilator --lint-only -Icores -Icores/util wavetable_osc.sv

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