192 selectable

gateware/drivers/ak4619-cfg-192.hex

@@ -0,0 +1,23 @@
+20 // I2C slave address (0x10<<1) and RW bit (W=0).
+00 // Register address to start at.
+37 // 0x00 Power Management
+AE // 0x01 Audio I/F Format
+1C // 0x02 Audio I/F Format
+04 // 0x03 System Clock Setting
+22 // 0x04 MIC AMP Gain
+22 // 0x05 MIC AMP Gain
+30 // 0x06 ADC1 Lch Digital Volume
+30 // 0x07 ADC1 Rch Digital Volume
+30 // 0x08 ADC2 Lch Digital Volume
+30 // 0x09 ADC2 Rch Digital Volume
+22 // 0x0A ADC Digital Filter Setting
+55 // 0x0B ADC Analog Input Setting
+00 // 0x0C Reserved
+06 // 0x0D ADC Mute & HPF Control
+18 // 0x0E DAC1 Lch Digital Volume
+18 // 0x0F DAC1 Rch Digital Volume
+18 // 0x10 DAC2 Lch Digital Volume
+18 // 0x11 DAC2 Rch Digital Volume
+04 // 0x12 DAC Input Select Setting
+05 // 0x13 DAC De-Emphasis Setting
+0A // 0x14 DAC Mute & Filter Setting

gateware/drivers/ak4619-cfg.hex

@@ -3,7 +3,7 @@
 37 // 0x00 Power Management
 AE // 0x01 Audio I/F Format
 1C // 0x02 Audio I/F Format
-04 // 0x03 System Clock Setting
+00 // 0x03 System Clock Setting
 22 // 0x04 MIC AMP Gain
 22 // 0x05 MIC AMP Gain
 30 // 0x06 ADC1 Lch Digital Volume

gateware/drivers/ak4619.sv

@@ -61,9 +61,16 @@ logic [4:0] bit_counter;
 
 assign pdn         = ~rst;
 assign bick        = clkdiv[0];
-assign mclk        = clkdiv[0];
 assign lrck        = clkdiv[7];
 
+`ifdef AK4619_192KHZ
+// MCLK for 192KHz sample rate.
+assign mclk        = clkdiv[0];
+`else
+// MCLK for 8-48KHz sample rates.
+assign mclk        = clk_256fs;
+`endif
+
 // 0, 1, 2, 3 == L, R, L, R
 assign channel     = clkdiv[7:6];
 // 0..31 for each channel, regardless of W.