arch/xtensa: use arch atomic when enable iram heap

S32C1I instructions may target cached, cache-bypass, and data RAM memory locations. S32C1I instructions are not permitted to access memory addresses in data ROM, instruction memory or the address region allocated to the XLMI port. Attempts to direct the S32C1I at these addresses will cause an exception. Signed-off-by: zhangyuan29 <[email protected]>
apache · Nov 15, 2024 · 7fe6ce4 · 7fe6ce4
1 parent 7ba0f11
commit 7fe6ce4
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diff --git a/arch/xtensa/src/cmake/Toolchain.cmake b/arch/xtensa/src/cmake/Toolchain.cmake
@@ -188,3 +188,7 @@ endif()
 if(CONFIG_DEBUG_SYMBOLS)
   add_compile_options(${CONFIG_DEBUG_SYMBOLS_LEVEL})
 endif()
+
+if(CONFIG_LIBC_ARCH_ATOMIC)
+  add_compile_options(-D__STDC_NO_ATOMICS__)
+endif()
diff --git a/arch/xtensa/src/esp32/Kconfig b/arch/xtensa/src/esp32/Kconfig
@@ -859,6 +859,7 @@ config ESP32_RTC_HEAP
 config ESP32_IRAM_HEAP
 	bool "Use the rest of IRAM as a separate heap"
 	select ARCH_HAVE_EXTRA_HEAPS
+	select LIBC_ARCH_ATOMIC
 	default n
 
 endmenu # Memory Configuration

diff --git a/arch/xtensa/src/lx6/Toolchain.defs b/arch/xtensa/src/lx6/Toolchain.defs
@@ -155,6 +155,10 @@ ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
   ARCHOPTIMIZATION += $(CONFIG_DEBUG_SYMBOLS_LEVEL)
 endif
 
+ifeq ($(CONFIG_LIBC_ARCH_ATOMIC),y)
+  ARCHCFLAGS += -D__STDC_NO_ATOMICS__
+endif
+
 # Default toolchain
 ifeq ($(CONFIG_XTENSA_TOOLCHAIN_XCC), y)
   ARCHCFLAGS += -Wno-atomic-alignment

diff --git a/arch/xtensa/src/lx7/Toolchain.defs b/arch/xtensa/src/lx7/Toolchain.defs
@@ -159,6 +159,10 @@ ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
   ARCHOPTIMIZATION += $(CONFIG_DEBUG_SYMBOLS_LEVEL)
 endif
 
+ifeq ($(CONFIG_LIBC_ARCH_ATOMIC),y)
+  ARCHCFLAGS += -D__STDC_NO_ATOMICS__
+endif
+
 # Default toolchain
 ifeq ($(CONFIG_XTENSA_TOOLCHAIN_XCC), y)
   ARCHCFLAGS += -Wno-atomic-alignment