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Data Offload Integration: adrv9009 AMD/Xilinx Projects #1516

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Data Offload Integration: adrv9009 AMD/Xilinx Projects #1516

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@podgori podgori commented Nov 11, 2024

PR Description

These changes integrate the Data Offload in the adrv9009 AMD/Xilinx based projects, replacing the old dacfifo IP.

In addition, a common script is used to import the MIG configuration for the zc706 PL DDR3 use case.

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

AndrDragomir
AndrDragomir previously approved these changes Nov 14, 2024
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AndrDragomir
AndrDragomir previously approved these changes Nov 14, 2024
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3 participants
@podgori @AndrDragomir @IuliaCMoldovan