2.2.1: minor updates

README.md

@@ -6,7 +6,7 @@
 [![codebeat badge](https://codebeat.co/badges/66773495-9967-4514-8c2c-916293f584b5)](https://codebeat.co/projects/github-com-acaldero-wepsim-master)
 [![Codacy Badge](https://api.codacy.com/project/badge/Grade/579e744cedde4dc78f8084d9db7abd32)](https://app.codacy.com/gh/acaldero/wepsim/dashboard)
 [![License: LGPL v3](https://img.shields.io/badge/License-LGPL%20v3-blue.svg)](https://www.gnu.org/licenses/lgpl-3.0)
-[![Release](https://img.shields.io/badge/Stable-2.2.0-green.svg)](https://github.com/acaldero/wepsim/releases/tag/v2.2.0)
+[![Release](https://img.shields.io/badge/Stable-2.2.1-green.svg)](https://github.com/acaldero/wepsim/releases/tag/v2.2.1)
 
 
 ## Table of contents
@@ -109,19 +109,19 @@ Step   | iOS                       |  Android                  | Action to perfo
 
 ### A) Run (and print the final state)
 
-+ From the command line it is possible to 'run' the 'asm-mips_s1e1.txt' assembly for the 'ep' architecture with the 'mc-ep_mips_base.txt' microcode, and print the final state:
++ From the command line it is possible to 'run' the 's1e1.asm' assembly for the 'ep' architecture with the 'mc-ep_base.txt' microcode, and print the final state:
 
 ```bash
-./wepsim.sh -a run -m ep -f ./examples/microcode/mc-ep_mips_base.txt -s ./examples/assembly/asm-mips_s1e1.txt
+./wepsim.sh -a run -m ep -f ./examples/microcode/mips/mc-ep_base.txt -s ./examples/assembly/mips/s1e1.asm
 register R2 = 0x2; register R3 = 0x1; register R5 = 0x1; register R29 = 0xfffff; register PC = 0x8018; memory 0x8000 = 0x8400002; memory 0x8004 = 0x8600001; memory 0x8008 = 0xa21809; memory 0x800c = 0x8400002; memory 0x8010 = 0x8600001; memory 0x8014 = 0xa2180a;
 ```
 
 ### B) Run step by step
 
-+ It is also possible to 'run' 'step by step' the 'asm-ep-s1_e1.txt' assembly for the 'ep' architecture with the 'mc-ep_mips_base.txt' microcode, and print for each assembly instruction the state elements that modify its value:
++ It is also possible to 'run' 'step by step' the 's1_e1.asm' assembly for the 'ep' architecture with the 'mc-ep_base.txt' microcode, and print for each assembly instruction the state elements that modify its value:
 
 ```bash
-./wepsim.sh -a stepbystep -m ep -f ./examples/microcode/mc-ep_mips_base.txt -s ./examples/assembly/asm-mips_s1e1.txt
+./wepsim.sh -a stepbystep -m ep -f ./examples/microcode/mips/ep_base.mc -s ./examples/assembly/mips/s1e1.asm
 pc,		instruction,			changes_from_zero_or_current_value
 pc = 0x8000,	li $2 2,			register R2 = 0x2; register R29 = 0xfffff; register PC = 0x8004
 pc = 0x8004,	li $3 1,			register R3 = 0x1; register PC = 0x8008
@@ -133,10 +133,10 @@ pc = 0x8014,	sub $5 $2 $3,			register R5 = 0x1; register PC = 0x8018
 
 ### C) Run microstep by microstep
 
-+ And to 'run' 'microstep by microstep' the 'asm-mips_s1e1.txt' assembly for the 'ep' architecture with the 'mc-ep_mips_base.txt' microcode, and print for each microinstruction the state elements that modify its value:
++ And to 'run' 'microstep by microstep' the 's1e1.asm' assembly for the 'ep' architecture with the 'ep_base.mc' microcode, and print for each microinstruction the state elements that modify its value:
 
 ```bash
-./wepsim.sh -a microstepbymicrostep -m ep -f ./examples/microcode/mc-ep_mips_base.txt -s ./examples/assembly/asm-mips_s1e1.txt
+./wepsim.sh -a microstepbymicrostep -m ep -f ./examples/microcode/mips/ep_base.mc -s ./examples/assembly/mips/s1e1.asm
 micropc,		microcode,				changes_from_zero_or_current_value
 micropc = 0x0,		T2 C0,					
 micropc = 0x1,		TA R BW=11 M1 C1,				
@@ -157,19 +157,19 @@ micropc = 0x35,		MC MR=0 SELA=1011 SELB=10000 MA=0 MB=0 SELCOP=1010 T6 SELC=1010
 
 ### D) Run & check end state (example when o.k.)
 
-+ You can check if the state at the end of the execution is the same as the one stored on file 'cl-mips_s1e1.txt'. You can 'run' the 'asm-mips_s1e1.txt' assembly for the 'ep' architecture with the 'mc-ep_mips_base.txt' microcode (**and if it matches the expected state, then the output is going to be**):
++ You can check if the state at the end of the execution is the same as the one stored on file 'cl-s1e1.txt'. You can 'run' the 's1e1.asm' assembly for the 'ep' architecture with the 'ep_base.mc' microcode (**and if it matches the expected state, then the output is going to be**):
 
 ```bash
-./wepsim.sh -a check -m ep -f ./examples/microcode/mc-ep_mips_base.txt -s ./examples/assembly/asm-mips_s1e1.txt -r ./examples/checklist/cl-mips_s1e1.txt
+./wepsim.sh -a check -m ep -f ./examples/microcode/mips/ep_base.mc -s ./examples/assembly/mips/s1e1.asm -r ./examples/checklist/mips/cl-s1e1.txt
 OK: Execution: no error reported
 ```
 
 ### E) Run & check end state (example when k.o.)
 
-+ You can check if the state at the end of the execution is the same as the one stored on file 'cl-mips_s1e1.txt'. You can 'run' the 'asm-mips_s1e1.txt' assembly for the 'ep' architecture with the 'mc-ep_mips_base.txt' microcode (**and if it fails to match the expected state then the output is going to be**):
++ You can check if the state at the end of the execution is the same as the one stored on file 'cl-s1e1.txt'. You can 'run' the 's1e1.asm' assembly for the 'ep' architecture with the 'ep_base.mc' microcode (**and if it fails to match the expected state then the output is going to be**):
 
 ```bash
-./wepsim.sh -a check -m ep -f ./examples/microcode/mc-ep_mips_base.txt -s ./examples/assembly/asm-mips_s1e1.txt -r ./examples/checklist/cl-mips_s1e2.txt
+./wepsim.sh -a check -m ep -f ./examples/microcode/mips/ep_base.mc -s ./examples/assembly/mips/s1e1.asm -r ./examples/checklist/mips/cl-s1e2.txt
 ERROR: Execution: different results: cpu[R1]='0' (expected '0xf'), cpu[R2]='0x2' (expected '0xf'), cpu[R3]='0' (expected '0x1'), cpu[R29]='0x100000' (expected '0xfffff'), cpu[PC]='0x8078' (expected '0x8018'), memory[0x1000]='0' (expected '0xa07ff0f'), memory[0x1004]='0' (expected '0x10061'), memory[0x1008]='0' (expected '0x7ffff'), memory[0x100c]='0' (expected '0x61000a'), memory[0x1010]='0' (expected '0xf'), memory[0x1014]='0' (expected '0xffffffff'), memory[0x1018]='0' (expected '0x7'), memory[0x101c]='0' (expected '0x12345678'), memory[0x1020]='0' (expected '0x61'), memory[0x1024]='0' (expected '0x6c6c6568'), memory[0x1028]='0' (expected '0x726f776f'), memory[0x102c]='0' (expected '0x646c'), memory[0x8000]='0x8400002' (expected '0x20201000'), memory[0x8004]='0x8600001' (expected '0x10601010'), memory[0x8008]='0xa21809' (expected '0x820000f'), memory[0x800c]='0x8400002' (expected '0x24201000'), memory[0x8010]='0x8600001' (expected '0x840000f'), memory[0x8014]='0xa2180a' (expected '0x14401010'),
 ```
 
@@ -178,7 +178,7 @@ ERROR: Execution: different results: cpu[R1]='0' (expected '0xf'), cpu[R2]='0x2'
 + And finally, it is possible to execute microstep by microstep but with a more verbose description:
 
 ```bash
-./wepsim.sh -a microstepverbalized -m ep -f ./examples/microcode/mc-ep_mips_base.txt -s ./examples/assembly/asm-mips_s1e1.txt
+./wepsim.sh -a microstepverbalized -m ep -f ./examples/microcode/mips/ep_base.mc -s ./examples/assembly/mips/s1e1.asm
 Micropc at 0x0.	Activated signals are: T2 C0. Associated actions are: Copy from Program Counter Register to Internal Bus value 0x8000. Load from Internal Bus to Memory Address Register value 0x8000.
 Micropc at 0x1.	Activated signals are: TA R BW M1 C1. Associated actions are: Copy from Memory Address Register to Address Bus value 0x8000. Memory output = 0x8400002 (Read a word from 0x8000). Select the full Word. Copy from from Memory to Input of Memory Data Register value 0x8400002. Load from Input of Memory Data Register to Memory Data Register value 0x8400002.
 Micropc at 0x2.	Activated signals are: M2 C2 T1 C3. Associated actions are: Copy to Input of Program Counter Program Counter Register plus four with result 0x8004. Load from Input of Program Counter to Program Counter Register value 0x8004. Copy from Memory Data Register to Internal Bus value 0x8400002. Load from Internal Bus to Instruction Register value 0x8400002. Decode instruction.
@@ -312,7 +312,7 @@ Micropc at 0x1.	Activated signals are: TA R BW M1 C1. Associated actions are: Co
 !unzip -o wepsim-2.2.0.zip  >& /dev/null
 !rm -fr   wepsim-2.2.0.zip
 !echo "(3/4) Executing WepSIM..."
-!./wepsim-2.2.0/wepsim.sh -a stepbystep -m ep -f ./wepsim-2.2.0/examples/microcode/mc-ep_mips_base.txt -s ./wepsim-2.2.0/examples/assembly/asm-mips_s1e1.txt > ./result.csv
+!./wepsim-2.2.0/wepsim.sh -a stepbystep -m ep -f ./wepsim-2.2.0/examples/microcode/mips/ep_base.mc -s ./wepsim-2.2.0/examples/assembly/mips/s1e1.asm > ./result.csv
 !rm -fr   wepsim-2.2.0
 !echo "(4/4) Showing execution trace as table..."
 

devel/mk_dist.sh

@@ -299,30 +299,33 @@ cp    -a external/speechkitt            ws_dist/external/
 cp    -a external/cordova.js            ws_dist/external/cordova.js
 
 ## pre-examples (default_packed)
-DEFAULT_EXAMPLE_SET="examples/examples_set/apps_ep_mips.json examples/examples_set/apps_poc_mips.json"
-jq 'reduce inputs as $i (.; . += $i)' $DEFAULT_EXAMPLE_SET > examples/examples_set/default_mips.json
-DEFAULT_EXAMPLE_SET="examples/examples_set/apps_ep_mips_instructive.json examples/examples_set/apps_poc_mips_instructive.json"
-jq 'reduce inputs as $i (.; . += $i)' $DEFAULT_EXAMPLE_SET > examples/examples_set/default_mips_instructive.json
- DEFAULT_EXAMPLE_SET="examples/examples_set/apps_ep_rv32.json examples/examples_set/apps_poc_rv32.json"
- jq 'reduce inputs as $i (.; . += $i)' $DEFAULT_EXAMPLE_SET > examples/examples_set/default_rv32.json
- DEFAULT_EXAMPLE_SET="examples/examples_set/apps_ep_rv32_instructive.json examples/examples_set/apps_poc_rv32_instructive.json"
- jq 'reduce inputs as $i (.; . += $i)' $DEFAULT_EXAMPLE_SET > examples/examples_set/default_rv32_instructive.json
-DEFAULT_EXAMPLE_SET="examples/examples_set/apps_ep_native.json examples/examples_set/apps_poc_native.json"
-jq 'reduce inputs as $i (.; . += $i)' $DEFAULT_EXAMPLE_SET > examples/examples_set/default_native.json
-DEFAULT_EXAMPLE_SET="examples/examples_set/ag_ep_rv32_packed.json examples/examples_set/ag_poc_rv32_packed.json"
-jq 'reduce inputs as $i (.; . += $i)' $DEFAULT_EXAMPLE_SET > examples/examples_set/ag_rv32_packed.json
+DEFAULT_EXAMPLE_SET="examples/examples_set/mips/es_ep.json             examples/examples_set/mips/es_poc.json"
+jq 'reduce inputs as $i (.; . += $i)' $DEFAULT_EXAMPLE_SET > examples/examples_set/mips/default.json
+DEFAULT_EXAMPLE_SET="examples/examples_set/mips/es_ep_instructive.json examples/examples_set/mips/es_poc_instructive.json"
+jq 'reduce inputs as $i (.; . += $i)' $DEFAULT_EXAMPLE_SET > examples/examples_set/mips/default_instructive.json
+ DEFAULT_EXAMPLE_SET="examples/examples_set/rv32/es_ep.json             examples/examples_set/rv32/es_poc.json"
+ jq 'reduce inputs as $i (.; . += $i)' $DEFAULT_EXAMPLE_SET > examples/examples_set/rv32/default.json
+ DEFAULT_EXAMPLE_SET="examples/examples_set/rv32/es_ep_instructive.json examples/examples_set/rv32/es_poc_instructive.json"
+ jq 'reduce inputs as $i (.; . += $i)' $DEFAULT_EXAMPLE_SET > examples/examples_set/rv32/default_instructive.json
+DEFAULT_EXAMPLE_SET="examples/examples_set/arm/es_ep.json"
+jq 'reduce inputs as $i (.; . += $i)' $DEFAULT_EXAMPLE_SET > examples/examples_set/arm/default.json
+DEFAULT_EXAMPLE_SET="examples/examples_set/z80/es_ep.json"
+jq 'reduce inputs as $i (.; . += $i)' $DEFAULT_EXAMPLE_SET > examples/examples_set/z80/default.json
+  DEFAULT_EXAMPLE_SET="examples/examples_set/rv32_ag/es_ep.json examples/examples_set/rv32_ag/es_poc.json"
+  jq 'reduce inputs as $i (.; . += $i)' $DEFAULT_EXAMPLE_SET > examples/examples_set/rv32_ag/default.json
+  DEFAULT_EXAMPLE_SET="examples/examples_set/mips_ocw/es_ep.json"
+  jq 'reduce inputs as $i (.; . += $i)' $DEFAULT_EXAMPLE_SET > examples/examples_set/mips_ocw/default.json
 
 ## pre-examples (default.json + apps.json)
  echo '[]' | \
- jq ' . + [ { "name": "Default-MIPS",      "url": "examples/examples_set/default_mips.json",                "description": "MIPS instruction set",           "size":  "18+",   "url_base_asm": "examples/assembly_mips/",     "url_base_mc": "examples/microcode/" } ]' | \
- jq ' . + [ { "name": "Default-RISCV",     "url": "examples/examples_set/default_rv32.json",                "description": "RISC-V instruction set",         "size":  "18+",   "url_base_asm": "examples/assembly_rv32/",     "url_base_mc": "examples/microcode/" } ]' | \
- jq ' . + [ { "name": "Instructive-MIPS",  "url": "examples/examples_set/default_mips_instructive.json",    "description": "MIPS instruction set",           "size":  "12+",   "url_base_asm": "examples/assembly_mips/",     "url_base_mc": "examples/microcode/" } ]' | \
- jq ' . + [ { "name": "Instructive-RISCV", "url": "examples/examples_set/default_rv32_instructive.json",    "description": "RISC-V instruction set",         "size":  "12+",   "url_base_asm": "examples/assembly_rv32/",     "url_base_mc": "examples/microcode/" } ]' | \
- jq ' . + [ { "name": "Native",            "url": "examples/examples_set/default_native.json",              "description": "MIPS, RISC-V, ARM, Z80",         "size":  "3+",    "url_base_asm": "examples/assembly_native/",   "url_base_mc": "examples/microcode/" } ]' | \
- jq ' . + [ { "name": "AulaGlobal course", "url": "examples/examples_set/ag_rv32_packed.json",              "description": "RISC-V instruction set for <a href='https://github.com/acaldero/uc3m_ec'>aula global</a>",        "size":  "10+",   "url_base_asm": "examples/assembly_ag/",       "url_base_mc": "examples/microcode/" } ]' | \
- jq ' . + [ { "name": "OCW course",        "url": "examples/examples_set/ocw_ep_mips_packed.json",          "description": "MIPS examples for <a href='https://ocw.uc3m.es/course/view.php?id=136'>opencourseware</a>",       "size":  "10+",   "url_base_asm": "examples/assembly_ocw/",   "url_base_mc": "examples/microcode/" } ]' > examples/examples_set/default.json
+ jq ' . + [ { "name": "Default-MIPS",      "url": "examples/examples_set/mips/default.json",                "description": "MIPS instruction set",           "size":  "18+",   "url_base_asm": "examples/assembly/mips/",     "url_base_mc": "examples/microcode/mips/" } ]' | \
+ jq ' . + [ { "name": "Default-RISCV",     "url": "examples/examples_set/rv32/default.json",                "description": "RISC-V instruction set",         "size":  "18+",   "url_base_asm": "examples/assembly/rv32/",     "url_base_mc": "examples/microcode/rv32/" } ]' | \
+ jq ' . + [ { "name": "Instructive-MIPS",  "url": "examples/examples_set/mips/default_instructive.json",    "description": "MIPS instruction set",           "size":  "12+",   "url_base_asm": "examples/assembly/mips/",     "url_base_mc": "examples/microcode/mips/" } ]' | \
+ jq ' . + [ { "name": "Instructive-RISCV", "url": "examples/examples_set/rv32/default_instructive.json",    "description": "RISC-V instruction set",         "size":  "12+",   "url_base_asm": "examples/assembly/rv32/",     "url_base_mc": "examples/microcode/rv32/" } ]' | \
+ jq ' . + [ { "name": "AulaGlobal course", "url": "examples/examples_set/rv32_ag/default.json",             "description": "RISC-V instruction set for <a href='https://github.com/acaldero/uc3m_ec'>aula global</a>",                                                      "size":  "10+",   "url_base_asm": "examples/assembly/rv32_ag/",     "url_base_mc": "examples/microcode/rv32/" } ]' | \
+ jq ' . + [ { "name": "OCW course",        "url": "examples/examples_set/mips_ocw/default.json",           "description": "MIPS examples for <a href='https://ocw.uc3m.es/course/view.php?id=136'>opencourseware</a>",                                                      "size":  "10+",   "url_base_asm": "examples/assembly/mips_ocw/",   "url_base_mc": "examples/microcode/mips/" } ]' > examples/examples_set/default.json
 
-cp examples/examples_set/default.json examples/apps.json
+## cp examples/examples_set/default.json examples/apps.json
 
 #  examples
 echo "  * ws_dist/examples/..."

devel/test_jshint.sh

@@ -23,7 +23,7 @@ set -x
 
 
 echo "checking sim_core..."
- jshint ./sim_core/sim_core_ui.js
+#jshint ./sim_core/sim_core_ui.js
  jshint ./sim_core/sim_core_voice.js
  jshint ./sim_core/sim_api_stateshots.js
  jshint ./sim_core/sim_api_native.js
@@ -134,7 +134,7 @@ echo "checking wepsim_web..."
  jshint ./wepsim_web/wepsim_uiscreen_classic.js
  jshint ./wepsim_web/wepsim_uiscreen_compact.js
  jshint ./wepsim_web/wepsim_uiscreen_main.js
- jshint ./wepsim_web/wepsim_web_api.js
+#jshint ./wepsim_web/wepsim_web_api.js
  jshint ./wepsim_web/wepsim_web_editor.js
 #jshint ./wepsim_web/wepsim_web_pwa.js
  jshint ./wepsim_web/wepsim_web_simulator.js

devel/test_wepsim_pack1.json

@@ -2,43 +2,43 @@
    {
       "pack":        "microcode + assembly",
       "description": "run",
-      "test":        "./ws_dist/wepsim.sh -a  run                   -m ep -f ./examples/microcode/mc-ep_mips_base.txt -s ./examples/assembly_mips/asm-mips_s1e1.txt",
+      "test":        "./ws_dist/wepsim.sh -a  run                   -m ep -f ./examples/microcode/mips/ep_base.mc -s ./examples/assembly/mips/s1e1.asm",
       "more":        "See WepSIM"
    },
    {
       "pack":        "microcode + assembly",
       "description": "stepbystep",
-      "test":        "./ws_dist/wepsim.sh -a  stepbystep            -m ep -f ./examples/microcode/mc-ep_mips_base.txt -s ./examples/assembly_mips/asm-mips_s1e1.txt",
+      "test":        "./ws_dist/wepsim.sh -a  stepbystep            -m ep -f ./examples/microcode/mips/ep_base.mc -s ./examples/assembly/mips/s1e1.asm",
       "more":        "See WepSIM"
    },
    {
       "pack":        "microcode + assembly",
       "description": "microstepbymicrostep",
-      "test":        "./ws_dist/wepsim.sh -a  microstepbymicrostep  -m ep -f ./examples/microcode/mc-ep_mips_base.txt -s ./examples/assembly_mips/asm-mips_s1e1.txt",
+      "test":        "./ws_dist/wepsim.sh -a  microstepbymicrostep  -m ep -f ./examples/microcode/mips/ep_base.mc -s ./examples/assembly/mips/s1e1.asm",
       "more":        "See WepSIM"
    },
    {
       "pack":        "microcode + assembly",
       "description": "check ok",
-      "test":        "./ws_dist/wepsim.sh -a  check                 -m ep -f ./examples/microcode/mc-ep_mips_base.txt -s ./examples/assembly_mips/asm-mips_s1e1.txt -r ./examples/checklist/cl-mips_s1e1.txt",
+      "test":        "./ws_dist/wepsim.sh -a  check                 -m ep -f ./examples/microcode/mips/ep_base.mc -s ./examples/assembly/mips/s1e1.asm -r ./examples/checklist/mips/cl-s1e1.txt",
       "more":        "See WepSIM"
    },
    {
       "pack":        "microcode + assembly",
       "description": "check ko",
-      "test":        "./ws_dist/wepsim.sh -a  check                 -m ep -f ./examples/microcode/mc-ep_mips_base.txt -s ./examples/assembly_mips/asm-mips_s1e1.txt -r ./examples/checklist/cl-mips_s1e2.txt",
+      "test":        "./ws_dist/wepsim.sh -a  check                 -m ep -f ./examples/microcode/mips/ep_base.mc -s ./examples/assembly/mips/s1e1.asm -r ./examples/checklist/mips/cl-s1e2.txt",
       "more":        "See WepSIM"
    },
    {
       "pack":        "microcode + assembly",
       "description": "microstepverbalized",
-      "test":        "./ws_dist/wepsim.sh -a  microstepverbalized   -m ep -f ./examples/microcode/mc-ep_mips_base.txt -s ./examples/assembly_mips/asm-mips_s1e1.txt",
+      "test":        "./ws_dist/wepsim.sh -a  microstepverbalized   -m ep -f ./examples/microcode/mips/ep_base.mc -s ./examples/assembly/mips/s1e1.asm",
       "more":        "See WepSIM"
    },
    {
       "pack":        "microcode + assembly",
       "description": "show-console",
-      "test":        "./ws_dist/wepsim.sh -a  show-console          -m ep -f ./examples/microcode/mc-ep_mips_os.txt   -s ./examples/assembly_mips/asm-mips_s4e1.txt",
+      "test":        "./ws_dist/wepsim.sh -a  show-console          -m ep -f ./examples/microcode/mips/ep_os.mc   -s ./examples/assembly/mips/s4e1.asm",
       "more":        "See WepSIM"
    }
 ]

devel/test_wepsim_pack2.json

@@ -20,7 +20,7 @@
    {
       "pack":        "checkpoint",
       "description": "check ok",
-      "test":        "./ws_dist/wepsim.sh -a  check                 --checkpoint ./examples/checkpoint/tutorial_1.txt -r ./examples/checklist/cl-mips_s1e1.txt",
+      "test":        "./ws_dist/wepsim.sh -a  check                 --checkpoint ./examples/checkpoint/tutorial_1.txt -r ./examples/checklist/mips/cl-s1e1.txt",
       "more":        "See WepSIM"
    },
    {