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This directory contains the sources of GHDL, the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL). GHDL is not an interpreter: it allows you to analyse and elaborate sources for generating machine code from your design. Native program execution is the only way for high speed simulation.

Main features

Full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the latest 2008 revision.

Partial support of PSL.

By using a code generator (LLVM, GCC or, x86_64/i386 only, a built-in one), it is much faster than any interpreted simulator. It can handle very large designs, such as leon3/grlib.

GHDL runs on GNU/Linux, Windows and macOS; on x86, x86_64, armv6/armv7/aarch32, aarch64 and ppc64. You can freely download nightly assets, use OCI images (aka Docker/Podman containers), or try building it on your own machine (see 'Getting GHDL' below).

Can write waveforms to GHW, VCD or FST files. Combined with a GUI-based waveform viewer and a good text editor, GHDL is a very powerful tool for writing, testing and simulating your code.

Co-simulation with foreign applications is supported through Verilog Procedural Interface (VPI) and/or VHPIDIRECT. See ghdl.github.io/ghdl-cosim.

Can synthesize arbitrarily complex VHDL designs into a VHDL 1993 netlist, which can be implicitly or explicitly used in open source or vendor synthesis frameworks.

Supported third party projects: Yosys (through ghdl-yosys-plugin), cocotb (through the VPI interface), OSVVM, UVVM, VUnit, ... (see ghdl/extended-tests).

GHDL is free software:

  • GNU General Public License 2
  • Creative Commons Attribution-ShareAlike available at ghdl.github.io/ghdl.
  • Some of the runtime libraries, are under different terms; see the individual source files for details.

Getting GHDL

  • Pre-built packages:
    • GHDL is available through the default package manager on most distributions: Debian/Ubuntu, Fedora, Arch Linux, MSYS2, etc.
    • After each succesful CI run, nightly tarballs/zipfiles for Ubuntu and Windows (MSYS2) are updated.
    • For using GHDL in CI, setup-ghdl-ci is provided. It is a GitHub Action (see github.com/features/actions) to setup GHDL in just 3 lines.
  • You may use containers from ghdl/docker or hdl/containers, in case your didn't find a suitable release.
  • Build GHDL yourself! See ghdl.github.io/ghdl: Building GHDL.

Project structure

Regular users

  • The CLI tool allows analysis, compilation, simulation and (experimental) synthesis for generating VHDL 1993 netlists. It is written in Ada and C, and three different backends are supported, which are sometimes named ghdl_mcode, ghdl_gcc and ghdl_llvm. This is the entrypoint for most users.

  • [experimental] ghdl-yosys-plugin is the integration of GHDL as a frontend plugin module for Yosys Open SYnthesis Suite, which uses the libghdl library (built with --enable-synth).

  • ghdl-ls (part of pyGHDL, see below) implements Language Server Protocol (LSP) in Python. VHDL analysis features provided by GHDL are accessed through libghdl. This can be integrated in text editors or IDES, such as, Vim, Emacs, Atom or Visual Studio Code. See ghdl/ghdl-language-server.

Advanced users

  • libghdl is a shared library that includes a subset of the regular features plus some features to be used by extension tools (i.e. pyGHDL). This is built along with the regular GHDL and it supports both non-synthesisable and synthesisable code. Nonetheless, this is not for users, but for tools built on top of the core. When configured along with --enable-synth, this shared library includes synthesis features too.

  • pyGHDL is a Python interface to libghdl. Currently, it is only used by ghdl-ls; however, it can be useful for advanced users which are willing to build Python utilities based on GHDL. There is work in progress for binding libghdl to pyVHDLModel (see pyGHDL.dom).

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  • [deprecated] ghdl_simul, which supports interpreted simulation, is available for historical reasons and for development/debugging only. It is very slow compared to the 'regular' compiled simulation and not all the features are supported.

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VHDL 2008/93/87 simulator

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  • VHDL 59.7%
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