Merge pull request #1087 from hannahxy13/bugfix/verification_step_name

Changed QONNX_TO_FINN_PYTHON verification step name to match build co…
Xilinx · Jul 15, 2024 · 438a482 · 438a482
2 parents b50175c + 0133f23
commit 438a482
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Showing 5 changed files with 11 additions and 1 deletion.
diff --git a/src/finn/builder/build_dataflow_config.py b/src/finn/builder/build_dataflow_config.py
@@ -96,6 +96,8 @@ class VerificationStepType(str, Enum):
     STREAMLINED_PYTHON = "streamlined_python"
     #: verify after step_apply_folding_config, using C++ for each HLS node
     FOLDED_HLS_CPPSIM = "folded_hls_cppsim"
+    #: verify after step_hw_ipgen
+    NODE_BY_NODE_RTLSIM = "node_by_node_rtlsim"
     #: verify after step_create_stitched_ip, using stitched-ip Verilog
     STITCHED_IP_RTLSIM = "stitched_ip_rtlsim"
 

diff --git a/src/finn/builder/build_dataflow_steps.py b/src/finn/builder/build_dataflow_steps.py
@@ -279,7 +279,7 @@ def step_qonnx_to_finn(model: ModelWrapper, cfg: DataflowBuildConfig):
     )
 
     if VerificationStepType.QONNX_TO_FINN_PYTHON in cfg._resolve_verification_steps():
-        verify_step(model, cfg, "qonnx_to_finn_python", need_parent=False)
+        verify_step(model, cfg, "finn_onnx_python", need_parent=False)
 
     return model
 
@@ -527,6 +527,11 @@ def step_hw_ipgen(model: ModelWrapper, cfg: DataflowBuildConfig):
     estimate_layer_resources_hls = model.analysis(hls_synth_res_estimation)
     with open(report_dir + "/estimate_layer_resources_hls.json", "w") as f:
         json.dump(estimate_layer_resources_hls, f, indent=2)
+
+    if VerificationStepType.NODE_BY_NODE_RTLSIM in cfg._resolve_verification_steps():
+        model = model.transform(PrepareRTLSim())
+        model = model.transform(SetExecMode("rtlsim"))
+        verify_step(model, cfg, "node_by_node_rtlsim", need_parent=True)
     return model
 
 

diff --git a/src/finn/qnn-data/build_dataflow/build.py b/src/finn/qnn-data/build_dataflow/build.py
@@ -61,6 +61,7 @@
         build_cfg.VerificationStepType.TIDY_UP_PYTHON,
         build_cfg.VerificationStepType.STREAMLINED_PYTHON,
         build_cfg.VerificationStepType.FOLDED_HLS_CPPSIM,
+        build_cfg.VerificationStepType.NODE_BY_NODE_RTLSIM,
         build_cfg.VerificationStepType.STITCHED_IP_RTLSIM,
     ],
     save_intermediate_models=True,

diff --git a/src/finn/qnn-data/build_dataflow/dataflow_build_config.json b/src/finn/qnn-data/build_dataflow/dataflow_build_config.json
@@ -13,6 +13,7 @@
     "initial_python",
     "streamlined_python",
     "folded_hls_cppsim",
+    "node_by_node_rtlsim",
     "stitched_ip_rtlsim"
   ],
   "generate_outputs": [

diff --git a/tests/util/test_build_dataflow.py b/tests/util/test_build_dataflow.py
@@ -72,5 +72,6 @@ def test_end2end_build_dataflow_directory():
         assert os.path.isfile(verify_out_dir + f"/verify_initial_python_{i}_SUCCESS.npy")
         assert os.path.isfile(verify_out_dir + f"/verify_streamlined_python_{i}_SUCCESS.npy")
         assert os.path.isfile(verify_out_dir + f"/verify_folded_hls_cppsim_{i}_SUCCESS.npy")
+        assert os.path.isfile(verify_out_dir + f"/verify_node_by_node_rtlsim_{i}_SUCCESS.npy")
         assert os.path.isfile(verify_out_dir + f"/verify_stitched_ip_rtlsim_{i}_SUCCESS.npy")
         assert os.path.isfile(output_dir + f"/report/verify_rtlsim_{i}.vcd")