Merge pull request #2 from cmuellner/mulah-fix

Small corrections and simplifications for xtheadmac and xtheadmemidx
XUANTIE-RV · Sep 5, 2022 · c5cf5d7 · c5cf5d7
2 parents 26280ad + 6b3ebe1
commit c5cf5d7
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Showing 7 changed files with 11 additions and 11 deletions.
diff --git a/xtheadmac/mula.adoc b/xtheadmac/mula.adoc
@@ -28,7 +28,7 @@ Operation::
 [source,sail]
 --
 M := reg[rs1] * reg[rs2]
-reg[rd] := zext.d(reg[rd] + M)
+reg[rd] := reg[rd] + M
 --
 
 Permission::

diff --git a/xtheadmac/mulah.adoc b/xtheadmac/mulah.adoc
@@ -27,8 +27,8 @@ This instruction computes the multiply-add result of the provided half-word oper
 Operation::
 [source,sail]
 --
-M := zext.h(reg[rs1]) * zext.h(reg[rs2])
-reg[rd] := sext.w(zext.w(reg[rd] + M))
+M := sext.w(reg[rs1][15:0]) * sext.w(reg[rs2][15:0])
+reg[rd] := sext.w(reg[rd] + M)
 --
 
 Permission::

diff --git a/xtheadmac/mulaw.adoc b/xtheadmac/mulaw.adoc
@@ -27,8 +27,8 @@ This instruction computes the multiply-add result of the provided word operands.
 Operation::
 [source,sail]
 --
-M := zext.w(reg[rs1]) * zext.w(reg[rs2])
-reg[rd] := sext.w(zext.w(reg[rd] + M))
+M := sext.w(reg[rs1]) * sext.w(reg[rs2])
+reg[rd] := sext.w(reg[rd] + M)
 --
 
 Permission::

diff --git a/xtheadmac/muls.adoc b/xtheadmac/muls.adoc
@@ -28,7 +28,7 @@ Operation::
 [source,sail]
 --
 M := reg[rs1] * reg[rs2]
-reg[rd] := zext.d(reg[rd] - M)
+reg[rd] := reg[rd] - M
 --
 
 Permission::

diff --git a/xtheadmac/mulsh.adoc b/xtheadmac/mulsh.adoc
@@ -27,8 +27,8 @@ This instruction computes the multiply-subtract result of the provided half-word
 Operation::
 [source,sail]
 --
-M := zext.h(reg[rs1]) * zext.h(reg[rs2])
-reg[rd] := sext.w(zext.w(reg[rd] - M))
+M := sext.h(reg[rs1][15:0]) * sext.h(reg[rs2][15:0])
+reg[rd] := sext.w(reg[rd] - M)
 --
 
 Permission::

diff --git a/xtheadmac/mulsw.adoc b/xtheadmac/mulsw.adoc
@@ -27,8 +27,8 @@ This instruction computes the multiply-subtract result of the provided word oper
 Operation::
 [source,sail]
 --
-M := zext.w(reg[rs1]) * zext.w(reg[rs2])
-reg[rd] := sext.w(zext.w(reg[rd] - M))
+M := sext.w(reg[rs1]) * sext.w(reg[rs2])
+reg[rd] := sext.w(reg[rd] - M)
 --
 
 Permission::

diff --git a/xtheadmemidx/lurwu.adoc b/xtheadmemidx/lurwu.adoc
@@ -22,7 +22,7 @@ Encoding::
 ....
 
 Description::
-This instruction loads a zero extended 16-bit value into GP register _rd_ from the address _rs1_ + (zero_extend(_rs2_) << _imm2_).
+This instruction loads a zero extended 32-bit value into GP register _rd_ from the address _rs1_ + (zero_extend(_rs2_) << _imm2_).
 
 Note, that this instruction is equivalent to a `zext.w _rs2_, _rs2_` followed by a `th.lrwu` with the same arguments.