We develop a domain specific language for graph processing accelerator generation targeting on complex hardware architectures such that users can focus on the basic logic of graph processing algorithms rather than mixing low-level hardware details and the graph processing algorithms. Currently, we mainly target a typical server-grade FPGA device from Xilinx.
At the initial version i.e. v0, we mainly utilize DSL to hide the script based graph processing accelerator generator. Basically, we still rely on existing graph processing accelerator generator framework (ThunderGP) to perform the code generation while it is transparent to users. In this case, users do not need to dig into the generator for specific template configuration.
In v1.0, we utilize the HLS based graph processing accelerator components to serve as backend of Graphitron. In general, Graphitron becomes a real DSL for graph processing accelerator generation while it utilize HLS as the backend. Essentially, it is a source-to-source DSL that converts Graphitron-based graph processing accelerator to HLS-based graph processing accelerator. Compared to prior templated based graph processing accelerator, it is much easier for the users to understand and can smoothly support different graph processing accelerator architecture such as edge-centric graph processing accelerator and vertex-centric graph processing accelerator.