fix: hardening fails due to missing power pins in macro netlists

.github/workflows/gds.yaml

@@ -127,7 +127,7 @@ jobs:
           EXPECTED_REPO: ${{ github.repository }}
         run: |
           # temporary workaround for missing bits in pad_raw:
-          sed -i 's/inout \[61:0\] pad_raw/inout [63:0] pad_raw/' efabless/verilog/gl/tt_ihp_wrapper.v
+          sed -i 's/inout \[61:0\] pad_raw/inout [63:0] pad_raw/' efabless/verilog/gl/tt_ihp_wrapper.nl.v
 
           make clean test_mux_gl
           # make will return success even if the test fails, so check for failure in the results.xml

.gitignore

@@ -12,6 +12,7 @@ shuttle_index.md
 efabless/gds/*.gds
 efabless/gds/*.lef
 efabless/verilog/gl/tt_ihp_wrapper.v
+efabless/verilog/gl/tt_ihp_wrapper.nl.v
 efabless/verilog/rtl/user_defines.v
 efabless/README.md
 

verilog/includes/includes.gl.mux_top

@@ -1,5 +1,5 @@
--v $(EFABLESS_SUBMISSION)/verilog/gl/tt_ihp_wrapper.v
--v $(TT_GL_VERILOG)/tt_ctrl.v
--v $(TT_GL_VERILOG)/tt_mux.v
--v $(TT_GL_VERILOG)/tt_um_chip_rom.v
+-v $(EFABLESS_SUBMISSION)/verilog/gl/tt_ihp_wrapper.nl.v
+-v $(TT_GL_VERILOG)/tt_ctrl.nl.v
+-v $(TT_GL_VERILOG)/tt_mux.nl.v
+-v $(TT_GL_VERILOG)/tt_um_chip_rom.nl.v
 -v $(USER_PROJECT_VERILOG)/../projects/tt_um_factory_test/tt_um_factory_test.v