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fix: disable power gating for all user projects #37

fix: disable power gating for all user projects

fix: disable power gating for all user projects #37

Workflow file for this run

name: gds
on:
workflow_dispatch:
push:
# Don't run on project submissions:
branches-ignore:
- projects/tt_um_*
pull_request:
# Don't run on project submissions:
paths-ignore:
- projects/tt_um_*/**
jobs:
gds:
env:
PYTHONIOENCODING: utf-8
PDK: ihp-sg13g2
PDK_ROOT: ${{ github.workspace }}/IHP-Open-PDK
TT_CONFIG: ihp-sg13g2.yaml
# Uncomment the following line to build only the specified projects:
#TT_ONLY_PROJECTS: tt_um_chip_rom,tt_um_factory_test
runs-on: ubuntu-24.04
steps:
- name: checkout repo
uses: actions/checkout@v4
with:
submodules: recursive
- name: Load OpenLane environment variables
run: cat .github/config/openlane.txt | tee -a $GITHUB_ENV
- name: setup python
uses: actions/setup-python@v5
with:
python-version: '3.11'
cache: 'pip'
- run: pip install -r tt-multiplexer/py/requirements.txt -r tt/requirements.txt
- name: Update caravel configuration
run: python ./tt/configure.py --update-shuttle
- uses: cachix/install-nix-action@v26
- uses: cachix/cachix-action@v14
with:
name: ${{ vars.CACHIX_CACHE || 'tinytapeout' }}
extraPullNames: ${{ vars.CACHIX_CACHE_EXTRA || 'openlane' }}
authToken: ${{ secrets.CACHIX_TOKEN }}
# run OpenLane to build the GDS
- name: Harden Chip ROM
working-directory: tt/rom
run: nix-shell $GITHUB_WORKSPACE/openlane2/shell.nix --run "python build.ihp-sg13g2.py"
- name: Harden tt_ctrl
working-directory: tt-multiplexer/ol2/tt_ctrl
run: nix-shell $GITHUB_WORKSPACE/openlane2/shell.nix --run "python build.py"
- name: Harden tt_mux
working-directory: tt-multiplexer/ol2/tt_mux
run: nix-shell $GITHUB_WORKSPACE/openlane2/shell.nix --run "python build.py"
- name: Copy macros
run: python ./tt/configure.py --copy-macros
- name: Harden tt_top
working-directory: tt-multiplexer/ol2/tt_top
run: nix-shell $GITHUB_WORKSPACE/openlane2/shell.nix --run "python build.py"
- name: Copy final results
run: python ./tt/configure.py --copy-final-results
- name: Create IHP submission
run: python ./tt/configure.py --create-ihp-submission
- name: upload GDS artifact
if: success() || failure()
uses: actions/upload-artifact@v4
with:
name: GDS
path: tt-multiplexer/ol2/tt_top/runs/RUN_*/*
- name: upload macros artifact
if: success() || failure()
uses: actions/upload-artifact@v4
with:
name: macros
path: |
tt/rom/runs/
tt-multiplexer/cfg/*.yaml
tt-multiplexer/ol2/tt_ctrl/runs/
tt-multiplexer/ol2/tt_mux/runs/
tt-multiplexer/ol2/tt_top/gds/*
tt-multiplexer/ol2/tt_top/lef/*
tt-multiplexer/ol2/tt_top/spef/*
tt-multiplexer/ol2/tt_top/verilog/*
- name: upload shuttle_index.json
if: success() || failure()
uses: actions/upload-artifact@v4
with:
name: shuttle_index
path: shuttle_index.json
- name: upload IHP submission directory
uses: actions/upload-artifact@v4
with:
name: ihp_submission
path: ihp
# Install iverilog, cocotb (required for GL test)
- name: install oss-cad-suite
uses: YosysHQ/setup-oss-cad-suite@v3
with:
version: '2024-10-21'
github-token: ${{ secrets.GITHUB_TOKEN }}
- name: GL simulation
working-directory: verilog/dv/mux
env:
EXPECTED_REPO: ${{ github.repository }}
run: |
# temporary workaround for missing bits in pad_raw:
sed -i 's/inout \[61:0\] pad_raw/inout [63:0] pad_raw/' ../../../ihp/verilog/gl/tt_ihp_wrapper.nl.v
make clean test_mux_gl
# make will return success even if the test fails, so check for failure in the results.xml
! grep failure results.xml
- name: upload GL test results
if: success() || failure()
uses: actions/upload-artifact@v4
with:
name: gl_test_vcd
path: |
verilog/dv/mux/results.xml
verilog/dv/mux/test_mux.vcd
verilog/dv/mux/test_mux.gtkw