Update project tt_um_couchand_cora16 (couchand/tt06-cora16)

projects/tt_um_couchand_cora16/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt06 7f56a586",
   "repo": "https://github.com/couchand/tt06-cora16",
-  "commit": "f3b79c50fff115c8dd11945afc08489f3463dab1",
-  "workflow_url": "https://github.com/couchand/tt06-cora16/actions/runs/8756517453",
+  "commit": "6c2688c68d55da29e970b6b656358e535ee0afb3",
+  "workflow_url": "https://github.com/couchand/tt06-cora16/actions/runs/8758486396",
   "sort_id": 1713544112105,
   "openlane_version": "OpenLane f691c8c0712ca6c6645e3fd548985b3cbcf08c78",
   "pdk_version": "open_pdks e0f692f46654d6c7c99fc70a0c94a080dab53571"

projects/tt_um_couchand_cora16/docs/info.md

@@ -41,7 +41,7 @@ The module expects an SPI RAM attached to the relevant SPI pins.  The onboard Ra
 
 Status byte | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
 ------------+---+---+---+---+---+---+---+--
-            | x | x | **E**lse | x | x | x | **N**eg | **Z**ero
+            | x | x | **E**lse | x | x | **C**arry | **N**eg | **Z**ero
 
 Impact on the status flags is documented as:
 
@@ -61,13 +61,14 @@ Drop | `0000 0011` | Drop a word from the stack | `---- ----`
 Push | `0000 0100` | Push a word to the stack | `---- ----`
 Pop  | `0000 0101` | Pop a word from the stack to the accumulator | `---- ----`
 Return | `0000 0110` | Return to the address on top of the stack | `---- ----`
-Not  | `0000 0111` | One's complement of the accumulator | `---- --##`
+Not  | `0000 0111` | One's complement of the accumulator | `---- -1##`
 Out Lo | `0000 1000` | Output the low byte of the accumulator | `---- ----`
 Out Hi | `0000 1001` | Output the high byte of the accumulator | `---- ----`
 Set DP | `0000 1010` | Set the data pointer value to the accumulator value | `---- ----`
 Test | `0000 1011` | Set the status flags based on the accumulator value | `---- --##`
 Branch Indirect | `0000 1100` | Add the accumulator to the program counter | `---- ----`
 Call Indirect | `0000 1101` | Call the subroutine address in the accumulator | `---- ----`
+Status        | `0001 0000` | Load the status flags into the accumulator | `---- ----`
 Load Indirect | `0100 01mm` | Load a word from the address in the accumulator, using addressing mode `m` (bug: modes not supported) | `---- ----`
 
 
@@ -77,12 +78,12 @@ Name | Bit Pattern | Description | Status
 -----+-------------+-------------+-------
 Load | `1000 0sss vvvv vvvv` | Load a value into the accumulator | `---- ----`
 Store | `1001 0sss vvvv vvvv` | Store a value to memory | `---- ----`
-Add | `1000 1sss vvvv vvvv` | Add a value to the accumulator | `---- --##`
-Sub | `1001 1sss vvvv vvvv` | Subtract a value from the accumulator | `---- --##`
+Add | `1000 1sss vvvv vvvv` | Add a value to the accumulator | `---- -###`
+Sub | `1001 1sss vvvv vvvv` | Subtract a value from the accumulator | `---- -###`
 And | `1010 0sss vvvv vvvv` | Bitwise and a value with the accumulator | `---- --##`
 Or  | `1010 1sss vvvv vvvv` | Bitwise or a value with the accumulator | `---- --##`
 Xor | `1011 0sss vvvv vvvv` | Bitwise exclusive or a value with the accumulator | `---- --##`
-Shift | `1011 1sss vvvv vvvv` | Shift the accumulator (see note below on direction) | `---- --##`
+Shift | `1011 1sss vvvv vvvv` | Shift the accumulator (see note below on direction) | `---- -###`
 Branch | `1100 0pp pppp pppp` | Add the offset `p` to the program counter | `---- ----`
 Call   | `1101 0pp pppp pppp` | Call the subroutine at address `p` | `---- ----`
 If     | `1111 000 0000 cccc` | Skip the following instruction if the condition doesn't hold | `---- ----`
@@ -118,10 +119,12 @@ Else      | `0010`      | Skip the next instruction if the `E` bit is cleared
 Not Else  | `0011`      | Skip the next instruction if the `E` bit is set
 Neg       | `0100`      | Skip the next instruction if the `N` bit is cleared
 Not Neg   | `0101`      | Skip the next instruction if the `N` bit is set
+Carry     | `0110`      | Skip the next instruction if the `C` bit is cleared
+Not Carry | `0111`      | Skip the next instruction if the `C` bit is set
 
 ### Three-byte instructions
 
 Name | Bit Pattern | Description | Status
 -----+-------------+-------------+-------
-Call Word | `0000 1110 wwww wwww wwww wwww` | Call the subroutine at address `w` | `---- ----`
-Load Immediate Word | `0000 1111 wwww wwww wwww wwww` | Set the accumulator to `w` | `---- ----`
+Call Word | `0011 1110 wwww wwww wwww wwww` | Call the subroutine at address `w` | `---- ----`
+Load Immediate Word | `0011 1111 wwww wwww wwww wwww` | Set the accumulator to `w` | `---- ----`

projects/tt_um_couchand_cora16/stats/metrics.csv

@@ -1,2 +1,2 @@
 design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
-/work/src,tt_um_couchand_cora16,wokwi,flow completed,0h9m51s0ms,0h9m0s0ms,129197.82894823722,0.03634736,64598.91447411861,62.45,77.9787,666.11,2253,0,0,0,0,0,0,0,11,11,0,-1,-1,105005,22105,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,70124080.0,0.0,73.27,89.59,48.15,70.17,-1,2824,3134,69,379,0,0,0,2900,29,1,94,137,456,150,23,1205,146,141,27,1384,456,22,905,2348,5115,34255.3536,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,55.080,38.870,0.3,1,10,0.63,0,sky130_fd_sc_hd,AREA 0
+/work/src,tt_um_couchand_cora16,wokwi,flow completed,0h16m31s0ms,0h15m39s0ms,137946.74496304546,0.03634736,68973.37248152273,66.17,77.5988,869.12,2420,0,0,0,0,0,0,0,6,6,0,-1,-1,108846,23757,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,74465865.0,0.0,78.28,92.76,54.78,75.08,-1,3039,3349,72,382,0,0,0,3114,29,1,101,157,462,157,26,1268,147,142,29,1317,456,15,892,2507,5187,34255.3536,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,55.080,38.870,0.3,1,10,0.67,0,sky130_fd_sc_hd,AREA 0

projects/tt_um_couchand_cora16/stats/synthesis-stats.txt

@@ -3,83 +3,78 @@
 
 === tt_um_couchand_cora16 ===
 
-   Number of wires:               2237
-   Number of wire bits:           2272
-   Number of public wires:         141
-   Number of public wire bits:     176
+   Number of wires:               2404
+   Number of wire bits:           2439
+   Number of public wires:         142
+   Number of public wire bits:     177
    Number of memories:               0
    Number of memory bits:            0
    Number of processes:              0
-   Number of cells:               2253
-     sky130_fd_sc_hd__a2111o_2      13
-     sky130_fd_sc_hd__a2111oi_2      2
-     sky130_fd_sc_hd__a211o_2       69
-     sky130_fd_sc_hd__a211oi_2       5
-     sky130_fd_sc_hd__a21bo_2        6
-     sky130_fd_sc_hd__a21boi_2       8
-     sky130_fd_sc_hd__a21o_2        99
-     sky130_fd_sc_hd__a21oi_2       80
-     sky130_fd_sc_hd__a221o_2       77
-     sky130_fd_sc_hd__a221oi_2       3
-     sky130_fd_sc_hd__a22o_2        51
-     sky130_fd_sc_hd__a22oi_2       14
-     sky130_fd_sc_hd__a2bb2o_2      15
-     sky130_fd_sc_hd__a311o_2       13
-     sky130_fd_sc_hd__a311oi_2       2
-     sky130_fd_sc_hd__a31o_2        62
-     sky130_fd_sc_hd__a31oi_2        6
-     sky130_fd_sc_hd__a32o_2         9
-     sky130_fd_sc_hd__a41o_2         4
-     sky130_fd_sc_hd__and2_2        92
-     sky130_fd_sc_hd__and2b_2       13
-     sky130_fd_sc_hd__and3_2        49
-     sky130_fd_sc_hd__and3b_2        1
-     sky130_fd_sc_hd__and4_2        15
-     sky130_fd_sc_hd__and4b_2        1
-     sky130_fd_sc_hd__and4bb_2       3
-     sky130_fd_sc_hd__buf_1        188
+   Number of cells:               2420
+     sky130_fd_sc_hd__a2111o_2       3
+     sky130_fd_sc_hd__a211o_2       72
+     sky130_fd_sc_hd__a211oi_2       4
+     sky130_fd_sc_hd__a21bo_2       11
+     sky130_fd_sc_hd__a21boi_2       5
+     sky130_fd_sc_hd__a21o_2        94
+     sky130_fd_sc_hd__a21oi_2       81
+     sky130_fd_sc_hd__a221o_2       85
+     sky130_fd_sc_hd__a221oi_2       1
+     sky130_fd_sc_hd__a22o_2        46
+     sky130_fd_sc_hd__a22oi_2        1
+     sky130_fd_sc_hd__a2bb2o_2       9
+     sky130_fd_sc_hd__a311o_2       10
+     sky130_fd_sc_hd__a311oi_2       1
+     sky130_fd_sc_hd__a31o_2        69
+     sky130_fd_sc_hd__a31oi_2        4
+     sky130_fd_sc_hd__a32o_2         7
+     sky130_fd_sc_hd__a41o_2         8
+     sky130_fd_sc_hd__and2_2        80
+     sky130_fd_sc_hd__and2b_2        9
+     sky130_fd_sc_hd__and3_2        57
+     sky130_fd_sc_hd__and3b_2        7
+     sky130_fd_sc_hd__and4_2        10
+     sky130_fd_sc_hd__and4b_2        6
+     sky130_fd_sc_hd__and4bb_2       2
+     sky130_fd_sc_hd__buf_1        207
      sky130_fd_sc_hd__buf_2          9
      sky130_fd_sc_hd__conb_1         7
-     sky130_fd_sc_hd__dfxtp_2      135
-     sky130_fd_sc_hd__inv_2         55
-     sky130_fd_sc_hd__mux2_2        91
-     sky130_fd_sc_hd__nand2_2      168
-     sky130_fd_sc_hd__nand2b_2       2
+     sky130_fd_sc_hd__dfxtp_2      136
+     sky130_fd_sc_hd__inv_2         61
+     sky130_fd_sc_hd__mux2_2       158
+     sky130_fd_sc_hd__nand2_2      201
+     sky130_fd_sc_hd__nand2b_2       1
      sky130_fd_sc_hd__nand3_2        5
-     sky130_fd_sc_hd__nand4_2        1
-     sky130_fd_sc_hd__nor2_2       167
+     sky130_fd_sc_hd__nand4_2        3
+     sky130_fd_sc_hd__nor2_2       172
      sky130_fd_sc_hd__nor2b_2        2
-     sky130_fd_sc_hd__nor3_2         6
-     sky130_fd_sc_hd__nor3b_2        1
+     sky130_fd_sc_hd__nor3_2         5
      sky130_fd_sc_hd__nor4_2         2
-     sky130_fd_sc_hd__o2111a_2       3
-     sky130_fd_sc_hd__o2111ai_2      3
-     sky130_fd_sc_hd__o211a_2      114
+     sky130_fd_sc_hd__o2111a_2       7
+     sky130_fd_sc_hd__o2111ai_2      6
+     sky130_fd_sc_hd__o211a_2      154
      sky130_fd_sc_hd__o211ai_2       8
-     sky130_fd_sc_hd__o21a_2        67
-     sky130_fd_sc_hd__o21ai_2       56
-     sky130_fd_sc_hd__o21ba_2        7
-     sky130_fd_sc_hd__o21bai_2       2
-     sky130_fd_sc_hd__o221a_2       67
-     sky130_fd_sc_hd__o221ai_2       3
-     sky130_fd_sc_hd__o22a_2        27
-     sky130_fd_sc_hd__o22ai_2        1
-     sky130_fd_sc_hd__o2bb2a_2      13
-     sky130_fd_sc_hd__o2bb2ai_2      1
-     sky130_fd_sc_hd__o311a_2        7
-     sky130_fd_sc_hd__o31a_2        13
-     sky130_fd_sc_hd__o31ai_2        8
-     sky130_fd_sc_hd__o32a_2         6
-     sky130_fd_sc_hd__o41a_2         2
-     sky130_fd_sc_hd__or2_2        150
-     sky130_fd_sc_hd__or2b_2        17
-     sky130_fd_sc_hd__or3_2         26
-     sky130_fd_sc_hd__or3b_2        14
-     sky130_fd_sc_hd__or4_2         20
+     sky130_fd_sc_hd__o21a_2        79
+     sky130_fd_sc_hd__o21ai_2       77
+     sky130_fd_sc_hd__o21ba_2        3
+     sky130_fd_sc_hd__o21bai_2       5
+     sky130_fd_sc_hd__o221a_2       51
+     sky130_fd_sc_hd__o221ai_2       1
+     sky130_fd_sc_hd__o22a_2        40
+     sky130_fd_sc_hd__o22ai_2        3
+     sky130_fd_sc_hd__o2bb2a_2       8
+     sky130_fd_sc_hd__o311a_2       10
+     sky130_fd_sc_hd__o31a_2        17
+     sky130_fd_sc_hd__o31ai_2        7
+     sky130_fd_sc_hd__o32a_2         4
+     sky130_fd_sc_hd__or2_2        152
+     sky130_fd_sc_hd__or2b_2         9
+     sky130_fd_sc_hd__or3_2         35
+     sky130_fd_sc_hd__or3b_2        22
+     sky130_fd_sc_hd__or4_2         19
      sky130_fd_sc_hd__or4b_2        10
-     sky130_fd_sc_hd__or4bb_2        4
-     sky130_fd_sc_hd__xnor2_2       38
-     sky130_fd_sc_hd__xor2_2        15
+     sky130_fd_sc_hd__xnor2_2       26
+     sky130_fd_sc_hd__xor2_2        16
 
-   Chip area for module '\tt_um_couchand_cora16': 20654.809600
+   Chip area for module '\tt_um_couchand_cora16': 21885.990400
 

projects/tt_um_couchand_cora16/tt_um_couchand_cora16.lef

@@ -67,7 +67,7 @@ MACRO tt_um_couchand_cora16
   PIN rst_n
     DIRECTION INPUT ;
     USE SIGNAL ;
-    ANTENNAGATEAREA 0.213000 ;
+    ANTENNAGATEAREA 0.159000 ;
     PORT
       LAYER met4 ;
         RECT 151.190 224.760 151.490 225.760 ;
@@ -281,7 +281,7 @@ MACRO tt_um_couchand_cora16
   PIN uio_out[0]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
-    ANTENNADIFFAREA 0.795200 ;
+    ANTENNADIFFAREA 1.336500 ;
     PORT
       LAYER met4 ;
         RECT 59.190 224.760 59.490 225.760 ;
@@ -333,7 +333,7 @@ MACRO tt_um_couchand_cora16
   PIN uio_out[6]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
-    ANTENNADIFFAREA 1.782000 ;
+    ANTENNADIFFAREA 0.795200 ;
     PORT
       LAYER met4 ;
         RECT 37.110 224.760 37.410 225.760 ;
@@ -342,7 +342,7 @@ MACRO tt_um_couchand_cora16
   PIN uio_out[7]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
-    ANTENNADIFFAREA 1.782000 ;
+    ANTENNADIFFAREA 1.336500 ;
     PORT
       LAYER met4 ;
         RECT 33.430 224.760 33.730 225.760 ;
@@ -362,7 +362,7 @@ MACRO tt_um_couchand_cora16
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
     ANTENNAGATEAREA 0.247500 ;
-    ANTENNADIFFAREA 0.891000 ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 84.950 224.760 85.250 225.760 ;
@@ -372,7 +372,7 @@ MACRO tt_um_couchand_cora16
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
     ANTENNAGATEAREA 0.247500 ;
-    ANTENNADIFFAREA 0.891000 ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 81.270 224.760 81.570 225.760 ;
@@ -381,8 +381,8 @@ MACRO tt_um_couchand_cora16
   PIN uo_out[3]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
-    ANTENNAGATEAREA 0.126000 ;
-    ANTENNADIFFAREA 0.891000 ;
+    ANTENNAGATEAREA 0.247500 ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 77.590 224.760 77.890 225.760 ;
@@ -392,7 +392,7 @@ MACRO tt_um_couchand_cora16
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
     ANTENNAGATEAREA 0.247500 ;
-    ANTENNADIFFAREA 0.891000 ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 73.910 224.760 74.210 225.760 ;
@@ -402,7 +402,7 @@ MACRO tt_um_couchand_cora16
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
     ANTENNAGATEAREA 0.247500 ;
-    ANTENNADIFFAREA 0.891000 ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 70.230 224.760 70.530 225.760 ;
@@ -411,8 +411,8 @@ MACRO tt_um_couchand_cora16
   PIN uo_out[6]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
-    ANTENNAGATEAREA 0.126000 ;
-    ANTENNADIFFAREA 0.891000 ;
+    ANTENNAGATEAREA 0.247500 ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 66.550 224.760 66.850 225.760 ;
@@ -422,7 +422,7 @@ MACRO tt_um_couchand_cora16
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
     ANTENNAGATEAREA 0.247500 ;
-    ANTENNADIFFAREA 0.891000 ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 62.870 224.760 63.170 225.760 ;
@@ -432,11 +432,11 @@ MACRO tt_um_couchand_cora16
       LAYER li1 ;
         RECT 2.760 2.635 158.240 223.125 ;
       LAYER met1 ;
-        RECT 1.450 2.080 160.930 223.680 ;
+        RECT 0.530 2.080 160.930 223.680 ;
       LAYER met2 ;
-        RECT 0.550 2.050 160.900 224.245 ;
+        RECT 0.090 2.050 160.900 224.245 ;
       LAYER met3 ;
-        RECT 0.525 2.555 160.730 224.225 ;
+        RECT 0.065 2.555 160.730 224.225 ;
       LAYER met4 ;
         RECT 2.135 224.360 3.590 224.760 ;
         RECT 4.690 224.360 7.270 224.760 ;
@@ -483,15 +483,15 @@ MACRO tt_um_couchand_cora16
         RECT 155.570 224.360 158.150 224.760 ;
         RECT 159.250 224.360 160.705 224.760 ;
         RECT 2.135 223.680 160.705 224.360 ;
-        RECT 2.135 4.255 20.995 223.680 ;
-        RECT 23.395 4.255 40.430 223.680 ;
-        RECT 42.830 4.255 59.865 223.680 ;
-        RECT 62.265 4.255 79.300 223.680 ;
-        RECT 81.700 4.255 98.735 223.680 ;
-        RECT 101.135 4.255 118.170 223.680 ;
-        RECT 120.570 4.255 137.605 223.680 ;
-        RECT 140.005 4.255 157.040 223.680 ;
-        RECT 159.440 4.255 160.705 223.680 ;
+        RECT 2.135 6.295 20.995 223.680 ;
+        RECT 23.395 6.295 40.430 223.680 ;
+        RECT 42.830 6.295 59.865 223.680 ;
+        RECT 62.265 6.295 79.300 223.680 ;
+        RECT 81.700 6.295 98.735 223.680 ;
+        RECT 101.135 6.295 118.170 223.680 ;
+        RECT 120.570 6.295 137.605 223.680 ;
+        RECT 140.005 6.295 157.040 223.680 ;
+        RECT 159.440 6.295 160.705 223.680 ;
   END
 END tt_um_couchand_cora16
 END LIBRARY