feat: update project tt_um_dlmiles_muldiv8_sky130faha from dlmiles/tt…

…06-muldiv8-sky130faha

Commit: 742257d48f84c40fb003960652fd49767e3d0857
Workflow: https://github.com/dlmiles/tt06-muldiv8-sky130faha/actions/runs/8743928507

projects/tt_um_dlmiles_muldiv8_sky130faha/LICENSE

@@ -0,0 +1,201 @@
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
+
+      "Licensor" shall mean the copyright owner or entity authorized by
+      the copyright owner that is granting the License.
+
+      "Legal Entity" shall mean the union of the acting entity and all
+      other entities that control, are controlled by, or are under common
+      control with that entity. For the purposes of this definition,
+      "control" means (i) the power, direct or indirect, to cause the
+      direction or management of such entity, whether by contract or
+      otherwise, or (ii) ownership of fifty percent (50%) or more of the
+      outstanding shares, or (iii) beneficial ownership of such entity.
+
+      "You" (or "Your") shall mean an individual or Legal Entity
+      exercising permissions granted by this License.
+
+      "Source" form shall mean the preferred form for making modifications,
+      including but not limited to software source code, documentation
+      source, and configuration files.
+
+      "Object" form shall mean any form resulting from mechanical
+      transformation or translation of a Source form, including but
+      not limited to compiled object code, generated documentation,
+      and conversions to other media types.
+
+      "Work" shall mean the work of authorship, whether in Source or
+      Object form, made available under the License, as indicated by a
+      copyright notice that is included in or attached to the work
+      (an example is provided in the Appendix below).
+
+      "Derivative Works" shall mean any work, whether in Source or Object
+      form, that is based on (or derived from) the Work and for which the
+      editorial revisions, annotations, elaborations, or other modifications
+      represent, as a whole, an original work of authorship. For the purposes
+      of this License, Derivative Works shall not include works that remain
+      separable from, or merely link (or bind by name) to the interfaces of,
+      the Work and Derivative Works thereof.
+
+      "Contribution" shall mean any work of authorship, including
+      the original version of the Work and any modifications or additions
+      to that Work or Derivative Works thereof, that is intentionally
+      submitted to Licensor for inclusion in the Work by the copyright owner
+      or by an individual or Legal Entity authorized to submit on behalf of
+      the copyright owner. For the purposes of this definition, "submitted"
+      means any form of electronic, verbal, or written communication sent
+      to the Licensor or its representatives, including but not limited to
+      communication on electronic mailing lists, source code control systems,
+      and issue tracking systems that are managed by, or on behalf of, the
+      Licensor for the purpose of discussing and improving the Work, but
+      excluding communication that is conspicuously marked or otherwise
+      designated in writing by the copyright owner as "Not a Contribution."
+
+      "Contributor" shall mean Licensor and any individual or Legal Entity
+      on behalf of whom a Contribution has been received by Licensor and
+      subsequently incorporated within the Work.
+
+   2. Grant of Copyright License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      copyright license to reproduce, prepare Derivative Works of,
+      publicly display, publicly perform, sublicense, and distribute the
+      Work and such Derivative Works in Source or Object form.
+
+   3. Grant of Patent License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      (except as stated in this section) patent license to make, have made,
+      use, offer to sell, sell, import, and otherwise transfer the Work,
+      where such license applies only to those patent claims licensable
+      by such Contributor that are necessarily infringed by their
+      Contribution(s) alone or by combination of their Contribution(s)
+      with the Work to which such Contribution(s) was submitted. If You
+      institute patent litigation against any entity (including a
+      cross-claim or counterclaim in a lawsuit) alleging that the Work
+      or a Contribution incorporated within the Work constitutes direct
+      or contributory patent infringement, then any patent licenses
+      granted to You under this License for that Work shall terminate
+      as of the date such litigation is filed.
+
+   4. Redistribution. You may reproduce and distribute copies of the
+      Work or Derivative Works thereof in any medium, with or without
+      modifications, and in Source or Object form, provided that You
+      meet the following conditions:
+
+      (a) You must give any other recipients of the Work or
+          Derivative Works a copy of this License; and
+
+      (b) You must cause any modified files to carry prominent notices
+          stating that You changed the files; and
+
+      (c) You must retain, in the Source form of any Derivative Works
+          that You distribute, all copyright, patent, trademark, and
+          attribution notices from the Source form of the Work,
+          excluding those notices that do not pertain to any part of
+          the Derivative Works; and
+
+      (d) If the Work includes a "NOTICE" text file as part of its
+          distribution, then any Derivative Works that You distribute must
+          include a readable copy of the attribution notices contained
+          within such NOTICE file, excluding those notices that do not
+          pertain to any part of the Derivative Works, in at least one
+          of the following places: within a NOTICE text file distributed
+          as part of the Derivative Works; within the Source form or
+          documentation, if provided along with the Derivative Works; or,
+          within a display generated by the Derivative Works, if and
+          wherever such third-party notices normally appear. The contents
+          of the NOTICE file are for informational purposes only and
+          do not modify the License. You may add Your own attribution
+          notices within Derivative Works that You distribute, alongside
+          or as an addendum to the NOTICE text from the Work, provided
+          that such additional attribution notices cannot be construed
+          as modifying the License.
+
+      You may add Your own copyright statement to Your modifications and
+      may provide additional or different license terms and conditions
+      for use, reproduction, or distribution of Your modifications, or
+      for any such Derivative Works as a whole, provided Your use,
+      reproduction, and distribution of the Work otherwise complies with
+      the conditions stated in this License.
+
+   5. Submission of Contributions. Unless You explicitly state otherwise,
+      any Contribution intentionally submitted for inclusion in the Work
+      by You to the Licensor shall be under the terms and conditions of
+      this License, without any additional terms or conditions.
+      Notwithstanding the above, nothing herein shall supersede or modify
+      the terms of any separate license agreement you may have executed
+      with Licensor regarding such Contributions.
+
+   6. Trademarks. This License does not grant permission to use the trade
+      names, trademarks, service marks, or product names of the Licensor,
+      except as required for reasonable and customary use in describing the
+      origin of the Work and reproducing the content of the NOTICE file.
+
+   7. Disclaimer of Warranty. Unless required by applicable law or
+      agreed to in writing, Licensor provides the Work (and each
+      Contributor provides its Contributions) on an "AS IS" BASIS,
+      WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+      implied, including, without limitation, any warranties or conditions
+      of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
+      PARTICULAR PURPOSE. You are solely responsible for determining the
+      appropriateness of using or redistributing the Work and assume any
+      risks associated with Your exercise of permissions under this License.
+
+   8. Limitation of Liability. In no event and under no legal theory,
+      whether in tort (including negligence), contract, or otherwise,
+      unless required by applicable law (such as deliberate and grossly
+      negligent acts) or agreed to in writing, shall any Contributor be
+      liable to You for damages, including any direct, indirect, special,
+      incidental, or consequential damages of any character arising as a
+      result of this License or out of the use or inability to use the
+      Work (including but not limited to damages for loss of goodwill,
+      work stoppage, computer failure or malfunction, or any and all
+      other commercial damages or losses), even if such Contributor
+      has been advised of the possibility of such damages.
+
+   9. Accepting Warranty or Additional Liability. While redistributing
+      the Work or Derivative Works thereof, You may choose to offer,
+      and charge a fee for, acceptance of support, warranty, indemnity,
+      or other liability obligations and/or rights consistent with this
+      License. However, in accepting such obligations, You may act only
+      on Your own behalf and on Your sole responsibility, not on behalf
+      of any other Contributor, and only if You agree to indemnify,
+      defend, and hold each Contributor harmless for any liability
+      incurred by, or claims asserted against, such Contributor by reason
+      of your accepting any such warranty or additional liability.
+
+   END OF TERMS AND CONDITIONS
+
+   APPENDIX: How to apply the Apache License to your work.
+
+      To apply the Apache License to your work, attach the following
+      boilerplate notice, with the fields enclosed by brackets "[]"
+      replaced with your own identifying information. (Don't include
+      the brackets!)  The text should be enclosed in the appropriate
+      comment syntax for the file format. We also recommend that a
+      file or class name and description of purpose be included on the
+      same "printed page" as the copyright notice for easier
+      identification within third-party archives.
+
+   Copyright [yyyy] [name of copyright owner]
+
+   Licensed under the Apache License, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   You may obtain a copy of the License at
+
+       http://www.apache.org/licenses/LICENSE-2.0
+
+   Unless required by applicable law or agreed to in writing, software
+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   See the License for the specific language governing permissions and
+   limitations under the License.

projects/tt_um_dlmiles_muldiv8_sky130faha/commit_id.json

@@ -0,0 +1,9 @@
+{
+  "app": "Tiny Tapeout tt06 c74b14ac",
+  "repo": "https://github.com/dlmiles/tt06-muldiv8-sky130faha",
+  "commit": "742257d48f84c40fb003960652fd49767e3d0857",
+  "workflow_url": "https://github.com/dlmiles/tt06-muldiv8-sky130faha/actions/runs/8743928507",
+  "sort_id": 1713470781833,
+  "openlane_version": "OpenLane eaba5192c45aa333ab45216ce1773d75d539e9b3",
+  "pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"
+}

projects/tt_um_dlmiles_muldiv8_sky130faha/docs/info.md

@@ -0,0 +1,183 @@
+<!---
+
+This file is used to generate your project datasheet. Please fill in the information below and delete any unused
+sections.
+
+You can also include images in this folder and reference them in the markdown. Each image must be less than
+512 kb in size, and the combined size of all images must be less than 1 MB.
+-->
+
+## Background
+
+Combinational multiply / divider unit (8bit+8bit input)
+
+This is an updated version of the original project that was submitted and
+manufactured in TT04 https://github.com/dlmiles/tt04-muldiv4.  The previous
+project was hand crafted in Logisim-Evolution then exported as verilog and
+integrated into a TT04 project.
+
+This version is the same design, extended to 8-bit wide inputs, but instead
+of hand crafting the logic gates in a GUI we convert functional blocks into
+SpinalHDL language constructs.  Part of the purpose of this design is to
+understand the area and timing changes introduced by adding more bits, then
+to explore alternative topologies.
+
+The goal of the next iteration of this design maybe to introduce a FMA
+(Fused Multiply Add/Accumulate) function and ALU function to explore if
+there is some useful composition of these functions (that might be useful
+in an 8bit CPU/MCU design, or scale to something bigger).  The next
+iteration on from this could explore how to draw the transistors directly
+(instead of using standard cell library) for such an arrangement, this may
+result in non-rectangular cells that interlock to improve both area density
+and timing performance.  Or it might go up in smoke... who knows.
+
+# How It Works
+
+Due to the limited total IOs available at the external TT interface it is
+necessary to clock the project and setup UI_IN[0] to load each of the 2
+8-bit input registers.
+
+The data is latched at the CLK NEGEDGE and the value provided to the
+combinational logic MUL/DIV operations (which are seperate logic modules)
+with the answer becoming immediately available (after propagation and
+ripple settling time) at the outputs.
+
+The result output is also multiplexed and has an immediate and register
+mode.  The immediate mode provides a direct visibility of the MUL/DIV
+combintational timing between input and outputs (you need to account for
+address multiplex of high-low 8bit sides of result).  The registered mode
+capture the result in full so that it is possible to pipeline interleave
+request and result information to achieve higher throughput.
+
+So one half of the answer is immediately available to read and the other
+half of the answer can be read by toggling UI_IN[0] (address bit0).
+Clocking is needed for registered output mode, but not necessarily for
+immediate mode.
+
+// FIXME please check out the original githun for any enahcnaed
+// documentation for this project, potentially improved information
+// nearer PCB+IC delivery (to customer) schedule but also post-production
+// post-physically testing results and information.
+// I hope to produce some kind graphs showing the timing capture and
+// reliability to show and demonstrate the cascade effect.  This assume
+// I have the design correct to allow this to happen, but there are some
+// tricked (like extending CLK on-duty cycle when latches are open) enough
+// to see result capture output.
+
+// FIXME provide wavedrom diagram (MULU, MULS, DIVU, DIVS)
+
+// FIXME explain IMMediate mode and REGistered mode (to pipeline)
+
+// FIXME provide blockdiagram of functional units
+//    D
+//   MUX
+//   X Y registers (loaded from multiplexed D)
+//    OP -> res flags
+//   P P registers
+//  DEMUX
+//    R
+
+// FIXME explain architective difference to previous example and
+// considerations why to change.
+
+// FIXME explain addressing mode to allow much wider units and
+//  potentially uneven input sizes.
+
+
+Multiplier (signed/unsigned)
+Method uses Ripple Carry Array as 'high speed multiplier'
+Setup operation mode bits MULDIV=0 and OPSIGNED(unsigned=0/signed=1)
+Setup A (multiplier 8-bit) * B (multiplicand 8-bit)
+Expect result P (product 16-bit)
+
+
+Divider (signed/unsigned)
+Method uses Full Adder with Mux as 'combinational restoring array divider algorithm'.
+Setup operation mode bits MULDIV=1 and OPSIGNED(unsigned=0/signed=1)
+Setup Dend (dividend 8-bit) / Dsor (divisor 8-bit)
+Expect result Q (quotient 8-bit) with R (remainder 8-bit)
+
+Divider has error bit indicators that take precedence over any result.
+If any error bit is set then the output Q and R should be disregarded.
+When in multiplier mode error bits are muted to 0.
+No input values can cause an overflow error so the bit is always reset.
+
+## How to test
+
+Please check back with the project github main page and the published
+docs/ directory.  There is expected to be some instructions provided
+around the time the TT05 chips a received (Q4 2024).
+
+At the time of writing receiving a physical chip (from a previous TT
+edition) back has not occured, so there is no experience on the best
+way to test this project, so I defer the task of writing this section
+to a later time.
+
+There should be sufficient instructions here start you own journey.
+
+## External hardware
+
+It is expect the RP2040 and a Python REPL should be sufficient test this
+project.
+
+## Thoughts to the future (next iteration)
+
+uio_in[3] might moved to bit4 and DIV0/OVER combined into bit5
+This would allow the address the contigious area below.
+However during a test build of a MULDIV16 version it easily exceeds 1x1, as
+this stage looking towards making builds with permutations of
+design/topology and method to generate GDS.  So 1x1 is good to achieve this.
+
+The uio_in[3] feature wants to use registered mode to lock result when last address
+is clocked in this way we can pipeline result and demonstration of what pipelining
+can do to increase thoughput.
+
+The TB is limited to the 4bit version.  Ran out of time to validate
+registered output and pipeline.
+
+
+Encapsulate the SpinalHDL Scala netlist generation, and write a yosys JVM
+module harness (a yosys C++ module that is a JVM thread/process runner, with
+communication interface, data/ffi API/lifecycle).  Then write a yosys plugin
+that allows it to directly include, use and call for generated data based on
+parametric details.
+
+Consider emitting a custom cell/macro/GDS_object that yosys can call for,
+then emit verilog like a regular standard cell module.
+
+Consider modifying OpenROAD/OpenLane to incorporate generated macros
+directly into other detailed routing environment then have the existing
+detailed routing work around it as-is.
+
+
+## TODO
+
+Fixup the original logicsim schematic labels.
+
+The input re-ordering (which made the SpinalHDL algo easier)
+
+Relabel the P6_EXTND_EN to P7_EXTND_EN the original prodict index label was
+a bad choice in retrospect.
+
+
+Provide the SpinalHDL directory to the project with the sbt project and
+netlist generation code.
+
+
+Fill out SpinalHDL unit testing testing.
+
+Test support for SUPPORT_SIGNED=false (try to completely remove nets from
+output instead of assigning constant False and letting synthesis optimize
+away)
+
+Implement support for seperate SUPPORT_SIGNED for each input with 3 modes
+of operation ALWAYS/NEVER/BOTH(like now using control input bit)
+
+Implement and test support for odd-sized inputs, so the width of X and Y or
+DEND and DSOR can be different sizes.
+
+When input width can be unequal, test out the EOVERFLOW in the divider is
+wired to the correct port and works in this scenarios.
+
+Provide unit testing for commong multipler sizes, obvious byte boudnaries
+but also the sizes common in FPGA DSP primitives.