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Add support for QuickLogic devices #89

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This PR adds support for the following QuickLogic devices:

glatosinski and others added 30 commits October 12, 2020 13:25
Fixed syntax error and set the WIDTH of signed_mult to 32 for default. (Maciej Kurc<[email protected]>)
QL: cells_sim: fix port definitions for buffers (Karol Gugala<[email protected]>)
QL: cells_map: map Valid_mult for mult16x16 (Karol Gugala<[email protected]>)
QL: cells_sim: update simulation models (Karol Gugala<[email protected]>)
QL: cells_sim: fix dff in logic_cell_macro (Karol Gugala<[email protected]>)
QL: cells_sim: remove commented out code (Karol Gugala<[email protected]>)
QL: use (* iopad_external_pin *) (Karol Gugala<[email protected]>)
QL: synth: do not check for empty top_opt (Karol Gugala<[email protected]>)
QL: replace YS_OVERRIDE -> override (Karol Gugala<[email protected]>)
Fixed incorrect techmap for mux4x0 (Maciej Kurc<[email protected]>)
QuickLogic: flatten designs by default (Karol Gugala<[email protected]>)
QuickLogic: add autoname (Karol Gugala<[email protected]>)
QuickLogic: add CODEOWNERS entry (Karol Gugala<[email protected]>)
QuickLogic: refactor synth_quicklogic (Karol Gugala<[email protected]>)
QuickLogic: Add MUX4 and MUX8 mappings (Karol Gugala<[email protected]>)
QL: Updated the flow of synth_quicklogic (Maciej Kurc<[email protected]>)
QL: Added more test cases (Maciej Kurc<[email protected]>)
Fixed a typo (Maciej Kurc<[email protected]>)
Added labels to the synth_quicklogic flow (Maciej Kurc<[email protected]>)
Fixed an undeclared signal bug and FF models in quicklogic/cells_sim.v (Maciej Kurc<[email protected]>)
quicklogic: add gpio_cell_macro sim model (Karol Gugala<[email protected]>)
Updated flip-flop implementations (Grzegorz Latosinski<[email protected]>)
Changed the Quicklogic synth flow to use clkbufmap. Updated cells_sim.v and tests. (Maciej Kurc<[email protected]>)
Removed techmaps for gate-level builtin cells. (Maciej Kurc<[email protected]>)
Added tests for synth_quicklogic. (Maciej Kurc<[email protected]>)
QL: add gpio_macro_cell definition (Karol Gugala<[email protected]>)
Fixed logic_cell_macro model in cells_sim.v (Maciej Kurc<[email protected]>)
quicklogic: Added command for assigning undriven ports (Grzegorz Latosinski<[email protected]>)
quicklogic: Removed synthesis comments (Grzegorz Latosinski<[email protected]>)
quicklogic: Added implementation of the logic cell (Grzegorz Latosinski<[email protected]>)
quicklogic: Used help_mode to alter the run calls (Grzegorz Latosinski<[email protected]>)
quicklogic: Moved peepopt before techmap (Grzegorz Latosinski<[email protected]>)
quicklogic: Removed excessive proc calls (Grzegorz Latosinski<[email protected]>)
quicklogic: Removed -exe flag (Grzegorz Latosinski<[email protected]>)
quicklogic: Added qlal4s3_mult_cell_macro (Grzegorz Latosinski<[email protected]>)
quicklogic: Fixed indents for qlal4s3b_cell_macro (Grzegorz Latosinski<[email protected]>)
quicklogic: Added logic_cell_macro (Grzegorz Latosinski<[email protected]>)
quicklogic: fix segfault in help synth_quicklogic (Karol Gugala<[email protected]>)
quicklogic: remove redundant bipad module (Karol Gugala<[email protected]>)
quicklogic: Added support for bipad (Grzegorz Latosinski<[email protected]>)
quicklogic: Added support for latches (Grzegorz Latosinski<[email protected]>)
quicklogic: Added dffsc module (Grzegorz Latosinski<[email protected]>)
quicklogic: Add IO pads only to the top module IO ports (Grzegorz Latosinski<[email protected]>)
quicklogic: Improved cleaning routines (Grzegorz Latosinski<[email protected]>)
quicklogic: Added mapping from 32x32 multiplier to 16x16 multiplier (Grzegorz Latosinski<[email protected]>)
quicklogic: Fixed '-top' flag handling for synth_quicklogic (Grzegorz Latosinski<[email protected]>)
quicklogic: Fixed call to hierarchy check (Grzegorz Latosinski<[email protected]>)
quicklogic: Added keep directive for Quicklogic CPU blackbox (Grzegorz Latosinski<[email protected]>)
quicklogic: Renamed multiply blocks to convention accepted by SpDE (Grzegorz Latosinski<[email protected]>)
quicklogic: Updated cells_sim.v and cells_map.v (Maciej Kurc<[email protected]>)
quicklogic: Corrected simulation models of LUTs for Quicklogic. (Maciej Kurc<[email protected]>)
quicklogic: Added mapping of VCC and GND in design to logic_1 and logic_0 (Grzegorz Latosinski<[email protected]>)
quicklogic: Introduced VCC (logic_1) and GND (logic_0) blocks (Grzegorz Latosinski<[email protected]>)
quicklogic: added minor blocks (Grzegorz Latosinski<[email protected]>)
quicklogic: added multiplier blocks (Grzegorz Latosinski<[email protected]>)
quicklogic: added RAM block (Grzegorz Latosinski<[email protected]>)
quicklogic: Added black boxes for hard CPU and gclkbuff (Grzegorz Latosinski<[email protected]>)
quicklogic: Fixed mapping for QuickLogic LUTs (Grzegorz Latosinski<[email protected]>)
quicklogic: Specialized all inpads assigned to asynchronous inputs to ckpads. (Grzegorz Latosinski<[email protected]>)
quicklogic: Fixed the output name for ckpad. (Grzegorz Latosinski<[email protected]>)
quicklogic: Fixed missing registered FF outputs. (Maciej Kurc<[email protected]>)
quicklogic: Added splitting the ports (SpDE support) (Grzegorz Latosinski<[email protected]>)
quicklogic: Added support for IO pads and CLK pads (Grzegorz Latosinski<[email protected]>)
quicklogic: Added address inversion for QuickLogic LUTs (Grzegorz Latosinski<[email protected]>)
quicklogic: Removed VCC/GND entries (Grzegorz Latosinski<[email protected]>)
quicklogic: Added IO pads to the QuickLogic script (Grzegorz Latosinski<[email protected]>)
quicklogic: Fixed cells mapping for inverted signals (Grzegorz Latosinski<[email protected]>)
quicklogic: Updated the library of available cells for QuickLogic (Grzegorz Latosinski<[email protected]>)
quicklogic: synth_quicklogic: Added loading cells library for QuickLogic (Grzegorz Latosinski<[email protected]>)
quicklogic: Created an initial script for MUX-based FPGAs (Grzegorz Latosinski<[email protected]>)

Signed-off-by: Grzegorz Latosinski <[email protected]>
Signed-off-by: Maciej Kurc <[email protected]>
Signed-off-by: Karol Gugala <[email protected]>

Co-authored-by: Grzegorz Latosinski <[email protected]>
Co-authored-by: Maciej Kurc <[email protected]>
Co-authored-by: Karol Gugala <[email protected]>
Makefile.inc - added Mult, RAM and FIFO Macro details
cells_sim.v - removed inpadff, outpadff, bipadiff, bipadoff and bipadioff definitions

Signed-off-by: Rakesh Moolacheri <[email protected]>
Signed-off-by: Lalit Sharma <[email protected]>
QL: AP: tweak LUT costs to prefer bigger LUTs (Karol Gugala<[email protected]>)
QL: techmaps: split LUT techmaps for PP3 and AP3 (Karol Gugala<[email protected]>)
QL: AP3: set lut costs so LU4 is preferred one (Karol Gugala<[email protected]>)
QL: AP3: fix sim and map Verilogs (Karol Gugala<[email protected]>)

Signed-off-by: Karol Gugala <[email protected]>
Signed-off-by: Lalit Sharma <[email protected]>
Signed-off-by: Lalit Sharma <[email protected]>
Signed-off-by: Lalit Sharma <[email protected]>
Signed-off-by: Lalit Sharma <[email protected]>
Signed-off-by: Lalit Sharma <[email protected]>
Signed-off-by: Lalit Sharma <[email protected]>
Signed-off-by: Lalit Sharma <[email protected]>
Signed-off-by: Lalit Sharma <[email protected]>
Lalit Sharma and others added 21 commits October 12, 2020 13:26
Signed-off-by: Lalit Sharma <[email protected]>
Signed-off-by: Lalit Sharma <[email protected]>
Signed-off-by: Lalit Sharma <[email protected]>
Signed-off-by: Lalit Sharma <[email protected]>
Before this change, yosys required 4096 bits (or at least 50%)
of the bits in a RAM to be used, in order to implement it as a
PB-RAM. Since there are less than 1000 FFs available in the FPGA
it means that any memory using somewhere between 1k and 4k bits
will not fit in the device.

This lowers the requirements on RAM efficiency to be more in line
with the iCE40 backend, which uses comparably sized FPGAs

Signed-off-by: Olof Kindgren <[email protected]>
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There are couple open questions here:

  • Does this belong in the downstream fork at all?
  • If it does belong down here, it oaught to be in wip/ branch, rather than merged directly onto the downstream master branch

@mithro What's the plan here?

@rw1nkler
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rw1nkler commented Oct 12, 2020

This PR has been created to discuss the changes and then add it as a wip/ branch to SymbiFlow Yosys.
The code comes from the QuickLogic Yosys fork (which is actively developed):
https://github.com/QuickLogic-Corp/yosys/tree/quicklogic-rebased

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rw1nkler commented Nov 2, 2020

Is there any other issue that needs to be addressed before creating wip/quicklogic branch and regenerating Yosys master+wip branch?

@litghost
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litghost commented Nov 2, 2020

Is there any other issue that needs to be addressed before creating wip/quicklogic branch and regenerating Yosys master+wip branch?

I think the broader issue is how to maintain long term maintenance of this wip/ branch. One of the recent pushes has been to eliminate wip/ branches, either by getting the patches merged upstream, or in the case of yosys, making plugins rather than modifying yosys directly. Ideally this would go into upstream yosys, but I understand that might be hard to impossible.

If getting into upstream yosys is not going to happen, then I believe converting this PR into a plugin, likely under its own project, is my preferred path forward.

@rw1nkler
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rw1nkler commented Nov 6, 2020

I believe converting this PR into a plugin, likely under its own project, is my preferred path forward.

Ok, I will create a PR which will add those changes as a separate Yosys plugin.

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9 participants