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Sync yosys #87
Sync yosys #87
Commits on Jul 6, 2020
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Update VPR version of Xilinx carry chain.
Signed-off-by: Keith Rothman <[email protected]>
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Signed-off-by: Alessandro Comodi <[email protected]>
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Signed-off-by: Keith Rothman <[email protected]>
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Signed-off-by: Alessandro Comodi <[email protected]>
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New integration point for master+wip.
Signed-off-by: Keith Rothman <[email protected]>
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Disable RAM32X1D and RAMB36E1 until VPR support is present.
Signed-off-by: Keith Rothman <[email protected]>
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arith_map: add carry_cout also for lcu
Signed-off-by: Alessandro Comodi <[email protected]>
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Disable SRL16 until VPR/xc7 supports it.
Signed-off-by: Keith Rothman <[email protected]>
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arith_map: fix LCU carry chain definitions
Signed-off-by: Alessandro Comodi <[email protected]>
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Signed-off-by: Alessandro Comodi <[email protected]>
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Change define from based on _ABC to inverted and based on __ICARUS__.
Signed-off-by: Keith Rothman <[email protected]>
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Revert master+wip to master (8b4e83c)
Signed-off-by: Keith Rothman <[email protected]>
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Disabled inference of BRAMs with WIDTH=2 for Xilinx arch.
Signed-off-by: Maciej Kurc <[email protected]>
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Disable some tests that failed as a result of disabling some primatives.
Signed-off-by: Keith Rothman <[email protected]>
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Add CARRY4_CO_COUT, which is a CARRY4 with a dedicated COUT chain port.
This enables avoiding the co-mingling of the carry chain port with the ports that connect to the fabric. Signed-off-by: Keith Rothman <[email protected]>
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Merge branches 'wip/carry4-cout', 'wip/disable-primitives' and 'wip/d…
…isable_ramb18e_w2' into sync_yosys
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This is an Octopus Merge commit of the following branches: wip/carry4-cout wip/disable-primitives wip/disable_ramb18e_w2 Signed-off-by: Keith Rothman <[email protected]>
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