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vhdl support and configuration page #72

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nobodywasishere
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Currently GHDL / ghdl-yosys-plugin aren't in the conda file / on the conda repository, so that will have to be done before / after this (or added to this) to make sure VHDL can work for anyone. Advice on what to do about this is welcome.

Unfortunately ghdl-yosys-plugin isn't compatible with YoWASP (to the best of my knowledge) so full-fledged Yosys will have to be used for VHDL support. I could be wrong in this though, I haven't looked too much into it.

I tested this with YosysHQ/fpga-toolchain.

@mithro
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mithro commented Apr 18, 2021

Hi,

Thank you for sending the pull request! It's awesome to see you contributing to this project. However, before I can look at this request you need to add DCO sign-off to commits in this repository.

We require DCO sign-off for all commits to this repository (including all authors). Please see the following URL to see more information and BeeWare also have a Beginners guide to DCOs.

You can use git commit --amend --signoff and then a git push --force to add the signoff. You can also use git rebase --signoff.

Thanks!

Signed-off-by: Michael Riegert <[email protected]>
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mithro commented Apr 19, 2021

So the readthedocs build is failing with;

  File "/home/docs/checkouts/readthedocs.org/user_builds/sphinxcontrib-hdl-diagrams/checkouts/72/sphinxcontrib_hdl_diagrams/__init__.py", line 489, in render_diagram_html
    fname, outfn = render_diagram(self, code, options, format, skin, yosys_script)
  File "/home/docs/checkouts/readthedocs.org/user_builds/sphinxcontrib-hdl-diagrams/checkouts/72/sphinxcontrib_hdl_diagrams/__init__.py", line 425, in render_diagram
    vhdl_to_verilog(source_path, ilfn, module, self.builder.config.hdl_diagram_ghdl, yosys)
  File "/home/docs/checkouts/readthedocs.org/user_builds/sphinxcontrib-hdl-diagrams/checkouts/72/sphinxcontrib_hdl_diagrams/__init__.py", line 391, in vhdl_to_verilog
    assert yosys != "yowasp", HDLDiagramError('Cannot use YoWASP for VHDL - GHDL is not compatible with YoWASP')
AssertionError: Cannot use YoWASP for VHDL - GHDL is not compatible with YoWASP

Exception occurred:
  File "/home/docs/checkouts/readthedocs.org/user_builds/sphinxcontrib-hdl-diagrams/checkouts/72/sphinxcontrib_hdl_diagrams/__init__.py", line 391, in vhdl_to_verilog
    assert yosys != "yowasp", HDLDiagramError('Cannot use YoWASP for VHDL - GHDL is not compatible with YoWASP')
AssertionError: Cannot use YoWASP for VHDL - GHDL is not compatible with YoWASP

I think we just need to install the VHDL plugins using conda?

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mithro commented Apr 19, 2021

There is already a conda package for ghdlsynth at https://github.com/hdl/conda-eda/tree/master/syn

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Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation. - hdl/conda-eda

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Generally looks really good!

Just a few small comments.

sphinxcontrib_hdl_diagrams/__init__.py Outdated Show resolved Hide resolved
sphinxcontrib_hdl_diagrams/__init__.py Outdated Show resolved Hide resolved
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mithro commented Apr 19, 2021

I think we can just add ghdlsynth to https://github.com/SymbiFlow/sphinxcontrib-hdl-diagrams/blob/master/environment.yml#L14 and set the configuration to system rather than yowasp?

GitHub
Sphinx Extension which generates various types of diagrams from Verilog code. - SymbiFlow/sphinxcontrib-hdl-diagrams

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nobodywasishere commented Apr 19, 2021

I think we can just add ghdlsynth to https://github.com/SymbiFlow/sphinxcontrib-hdl-diagrams/blob/master/environment.yml#L14 and set the configuration to system rather than yowasp?

I tried adding it to the environment.yml locally but conda failed to find it, probably because it's not in the repositories. Otherwise, I think that can work. The conda version of yosys doesn't give an error about being unable to load plugins at runtime as well.

GitHub
Sphinx Extension which generates various types of diagrams from Verilog code. - SymbiFlow/sphinxcontrib-hdl-diagrams

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This is really nice! Just left with fixing the docs before we merge.

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umarcor commented Apr 20, 2021

FTR, Yosys on Windows does not support loading modules dynamically. They need to be built-in. Therefore, the Conda package is suitable for Linux hosts only. However, GHDL and Yosys (with built-in ghdl-yosys-plugin) are available on MSYS2. Therefore, Windows users should be able to use this extension together with Sphinx installed on MSYS2. As a matter of fact, that's how/where I build/test the docs of open source projects every day. I will give this a try.

README.rst Show resolved Hide resolved
README.rst Outdated
Which will pass ``-m ghdl`` to Yosys when calling it. Similarly, setting this to the path of a
ghdl-yosys-plugin shared library will also work.

Unfortunately, at this time GHDL and ghdl-yosys-plugin aren't supported by YoWASP.
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Let's welcome help from others explicitly!

Unfortunately, at this time GHDL and ghdl-yosys-plugin aren't supported by YoWASP. However, we'd love to have it available. Are you aware of some proof-of-concept linking WASM compiled from both C++ and Ada? Do you want to give it a try? Let us know!

@@ -0,0 +1,23 @@
library IEEE;
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Maybe add some VHDL 2008 example too? That's one relevant feature of GHDL compared to almost any other available VHDL parsing tool.

docs/conf.py Outdated
@@ -58,6 +58,10 @@
'sphinxcontrib_hdl_diagrams',
]

# Uncomment for YosysHQ/fpga-toolchain
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I wonder if this can be passed as a CLI or envvar. In #73, I use make -C docs html for building the docs. That's something I do in many other projects with Docs based on Sphinx. Hence, I'd love to do HDL_DIAGRAM=system:prebuilt make -C docs html or anything similar, instead of manually modifying the conf script.

Nonetheless, I think we can handle this a separated PR, after this is merged.

GHDL
++++

GHDL can either be prebuilt into Yosys or loaded at runtime. If it is loaded at
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There is some duplication between the info in the README and the info here, isn't it? I would suggest keeping the GHDL details in one place (here). In fact, I'd suggest moving Usage from the readme to the docs.

docs/index.rst Show resolved Hide resolved
print("Running YoWASP yosys: {}".format(ycmd))
yowasp_yosys.run_yosys(ycmd)
elif yosys == 'system':
ycmd = "yosys -p '{cmd}' {src}".format(src=src, cmd=cmd)
ycmd = "yosys {options} -p '{cmd}' {src}".format(options=options, src=src, cmd=cmd)
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There is a commit in #73 for cleaning this. You might want to pick it.

yosys_opt = "-m ghdl "
elif ghdl == "prebuilt":
yosys_opt = ""
elif os.path.exists(ghdl):
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I would use Path(ghdl).exists(). This is a Python language preference.

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Are you sure about this? I tried this as an example and got an error:

>>> from os import path
>>> path('conf.py').exists()
Traceback (most recent call last):
  File "<stdin>", line 1, in <module>
TypeError: 'module' object is not callable

On a similar note, os.path maybe should be replaced with just path throughout the code as it's imported independently from os (or the latter should be removed and use os.path everywhere). Seems redundant to have both.

import os # line 26
.
.
.
from os import path # line 33

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sphinxcontrib_hdl_diagrams/__init__.py Outdated Show resolved Hide resolved
raise HDLDiagramError("Cannot use YoWASP for VHDL (yet)")
module = options['module']
ilfn = path.join(self.builder.outdir, self.builder.imagedir, options['outname'] + '.v')
vhdl_to_verilog(source_path, ilfn, module, self.builder.config.hdl_diagram_ghdl, yosys)
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@umarcor umarcor Apr 21, 2021

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I'm not sure to understand this approach. My perception is that you are supporting Verilog sources only or VHDL sources only. Then, you convert VHDL to Verilog as a preprocess step, and then use exactly the same functions you'd use for "regular" Verilog sources. Therefore, generating drawings of mixed-language designs is not supported by this PR. Is this correct? If so, I would explain it somewhere, together with inviting people to contribute for making mixed-language diagrams possible.

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You are 100% right. After going back through the fomu workshop mixed-hdl example, I want to implement this differently than what I have now. I'm going to continue this discussion back on #65.

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So it looks like to get ghdl-yosys-plugin and ghdl added to symbiflow conda we'll have to get gcc-ada added as well (I'd recommend adding it to conda-forge instead of symbiflow). There's already one for MinGW but that doesn't help for Linux/MacOS. I've opened this issue to keep track of it. I've also started work here on updating the ghdl-yosys-plugin package recipe.

I don't think the missing package should block this from being merged, it would just mean that VHDL support wouldn't be able to be used until it does (if people are using conda for generating their docs).

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Support VHDL and mixed language designs
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