Merge with riscv-software-src/riscv-isa-sim repository #2
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- c.fsdsp need not be listed since cm.push etc. are listed - mop.r.28/mop.rr.7 don't have corresponding files in riscv/insns/ - the rest are just erroneous
We get better error checking if we list only the more specific instructions and omit the more general ones (mop.r.N/mop.rr.N).
…w-overlap Separate RV32 and RV64 C instructions into separate files
Updated README with supported Vector Cryptography Extensions
This has no effect on Spike itself, but it might matter for anyone who's using Spike as a library in a multithreaded program.
…unding-mode-thread-local Make softfloat's rounding mode thread-local
Otherwise, configure will fail with 'Could not find a version of the Boost::Asio library!'
Add a prerequisite for building
…x-warnings Fix a few compile warnings
…16-ops Add several BF16 ops to SoftFloat
…x-1696 In isa_parser, move extensionology code before error-checking code
isa_parser should already require any Zvef or Zved extensions imply F/D
…-cbo-fault Raise store/AMO access fault on CBO to shadow-stack page
There is a comment about aiming at --halted but failing to achieve so. This commit provides the behavior.
…x-1825 Fix f64_to_bf16 raising underflow when it shouldn't
Change -H flag into --halted
…eplacement for std::optional, which is a feature introduced in C++17
…introduced in C++17, with NullOpt of the created option class
…it fields are only available in c++20
…o preserve changes previously made by Dolu1990 in commits: [hpc workaround] & [add a few additionnal traces]
…o preserve changes previously made by Dolu1990 in commits: [add mmio_fetch mmio_mmu]
…o preserve changes previously made by Dolu1990 in commits: [Allow LR/SC on MMIO]
# Conflicts: # riscv/mmu.h # riscv/triggers.cc
…ember initialisers for bitfields are only available in C++20\n- class Optional : adaptation of the optional class to replace std::optional and std::nullopt, a feature introduced in C++17.
… [Allow LR/SC on MMIO]
This was referenced Oct 15, 2024
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Hi, Sure. Thanks :) |
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Hi @Dolu1990 , Knowing that I want to choose the version of the update spike branch in both conflicts, what should I do to resolve these conflicts? processor.cc
processor.h
Thanks :D |
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Hi Charles,
I have updated the RISC-V ISA simulator. I will also submit a pull request for the changes in NaxRiscv and RVLS to ensure compatibility with the updated version of the SpinalHDL/riscv-isa-sim.
Thank you