add Apb3Axis

SpinalHDL · Jan 23, 2019 · 551d7e3 · 551d7e3
1 parent b5caca5
commit 551d7e3
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Showing 2 changed files with 35 additions and 1 deletion.
diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala
@@ -166,6 +166,10 @@ case class Murax(config : MuraxConfig) extends Component{
     val uart = master(Uart())
 
     val xip = ifGen(genXip)(master(SpiXdrMaster(xipConfig.ctrl.spi)))
+
+    //AXI Streams
+    val axis_input = slave(Stream(Bits(32 bits)))
+    val axis_output = master(Stream(Bits(32 bits)))
   }
 
 
@@ -293,7 +297,7 @@ case class Murax(config : MuraxConfig) extends Component{
       val ctrl = Apb3SpiXdrMasterCtrl(xipConfig)
       ctrl.io.spi <> io.xip
       externalInterrupt setWhen(ctrl.io.interrupt)
-      apbMapping += ctrl.io.apb     -> (0x1F000, 4 kB)
+      apbMapping += ctrl.io.apb    -> (0x1F000, 4 kB)
 
       val accessBus = new PipelinedMemoryBus(PipelinedMemoryBusConfig(24,32))
       mainBusMapping += accessBus -> (0xE0000000l, 16 MB)
@@ -309,7 +313,11 @@ case class Murax(config : MuraxConfig) extends Component{
       apbMapping += bootloader.io.apb     -> (0x1E000, 4 kB)
     })
 
+    val axis = Apb3Axis( Apb3Config( addressWidth = 8, dataWidth = 32 ))
+    axis.io.input << io.axis_input
+    io.axis_output << axis.io.output
 
+    apbMapping += axis.io.apb     -> (0x30000, 4 kB)
 
     //******** Memory mappings *********
     val apbDecoder = Apb3Decoder(

diff --git a/src/main/scala/vexriscv/demo/MuraxUtiles.scala b/src/main/scala/vexriscv/demo/MuraxUtiles.scala
@@ -163,3 +163,29 @@ class MuraxApb3Timer extends Component{
   interruptCtrl.io.inputs(1) := timerB.io.full
   io.interrupt := interruptCtrl.io.pendings.orR
 }
+
+case class Apb3Axis(apb3Config: Apb3Config) extends Component {
+  val io = new Bundle {
+    val apb  = slave(Apb3(apb3Config))
+    val input = slave(Stream(Bits(32 bits)))
+    val output = master(Stream(Bits(32 bits)))
+  }
+
+  val ctrl = Apb3SlaveFactory(io.apb)
+
+  val ififo = StreamFifo( dataType = Bits(32 bits), depth    = 128 )
+  ififo.io.push << io.input
+
+  ctrl.read(ififo.io.pop.payload, address = 0);
+  val ififoPopReady = ctrl.drive(ififo.io.pop.ready, address = 4)
+  ctrl.read(ififo.io.pop.valid, address = 8);
+  when(ififo.io.pop.valid){ ififoPopReady := False }
+
+  val ofifo = StreamFifo( dataType = Bits(32 bits), depth    = 128 )
+  ofifo.io.pop >> io.output
+
+  ctrl.drive(ofifo.io.push.payload, address = 12)
+  val ofifoPushValid = ctrl.drive(ofifo.io.push.valid, address = 16)
+  ctrl.read(ofifo.io.push.ready, address = 20)
+  when(ofifo.io.push.ready){ ofifoPushValid := False }
+}