[MBIST] Add mbist infrastructure (#71)

.mill-version

@@ -1 +1 @@
-0.9.6
+0.11.2

Makefile

@@ -1,10 +1,16 @@
+RTL_OPT = --full-stacktrace -td build --target systemverilog --module $(MOD)
+
 init:
 	git submodule update --init
 	cd rocket-chip && git submodule update --init hardfloat cde
 
 compile:
 	mill -i utility.compile
 
+rtl:
+	@mkdir -p build
+	mill -i xsutils.test.runMain top.TestTop $(RTL_OPT)
+
 idea:
 	mill -i mill.scalalib.GenIdea/idea
 

build.sc

@@ -1,16 +1,19 @@
 import mill._
 import scalalib._
 import scalafmt._
+import $file.`rocket-chip`.common
+import $file.`rocket-chip`.hardfloat.common
+import $file.`rocket-chip`.cde.common
 
 val defaultVersions = Map(
-  "chisel3" -> "3.6.0",
-  "chisel3-plugin" -> "3.6.0",
-  "chiseltest" -> "0.3.2",
+  "chisel" -> "6.1.0",
+  "chisel-plugin" -> "6.1.0",
+  "chiseltest" -> "5.0.0",
   "scala" -> "2.13.10",
   "scalatest" -> "3.2.7"
 )
 
-def getVersion(dep: String, org: String = "edu.berkeley.cs", cross: Boolean = false) = {
+def getVersion(dep: String, org: String = "org.chipsalliance", cross: Boolean = false) = {
   val version = sys.env.getOrElse(dep + "Version", defaultVersions(dep))
   if (cross)
     ivy"$org:::$dep:$version"
@@ -20,50 +23,98 @@ def getVersion(dep: String, org: String = "edu.berkeley.cs", cross: Boolean = fa
 
 trait CommonModule extends ScalaModule {
   override def scalaVersion = defaultVersions("scala")
+
+  override def scalacPluginIvyDeps = Agg(getVersion("chisel-plugin", cross = true))
+
+  override def scalacOptions = super.scalacOptions() ++ Agg("-Ymacro-annotations", "-Ytasty-reader")
+
 }
 
+object rocketchip extends RocketChip
 
-object `rocket-chip` extends SbtModule with CommonModule {
+trait RocketChip
+  extends millbuild.`rocket-chip`.common.RocketChipModule
+    with SbtModule {
+  def scalaVersion: T[String] = T(defaultVersions("scala"))
 
-  override def ivyDeps = super.ivyDeps() ++ Agg(
-    ivy"${scalaOrganization()}:scala-reflect:${scalaVersion()}",
-    ivy"org.json4s::json4s-jackson:3.6.1",
-    getVersion("chisel3"),
-  )
+  override def millSourcePath = os.pwd / "rocket-chip"
+
+  def chiselModule = None
+
+  def chiselPluginJar = None
+
+  def chiselIvy = Some(getVersion("chisel"))
+
+  def chiselPluginIvy = Some(getVersion("chisel-plugin", cross = true))
+
+  def macrosModule = macros
+
+  def hardfloatModule = hardfloat
+
+  def cdeModule = cde
+
+  def mainargsIvy = ivy"com.lihaoyi::mainargs:0.5.0"
+
+  def json4sJacksonIvy = ivy"org.json4s::json4s-jackson:4.0.5"
+
+  object macros extends Macros
 
-  object macros extends SbtModule with CommonModule
+  trait Macros
+    extends millbuild.`rocket-chip`.common.MacrosModule
+      with SbtModule {
 
-  object cde extends CommonModule {
-    override def millSourcePath = super.millSourcePath / "cde" / "cde"
+    def scalaVersion: T[String] = T(defaultVersions("scala"))
+
+    def scalaReflectIvy = ivy"org.scala-lang:scala-reflect:${defaultVersions("scala")}"
   }
 
-  object hardfloat extends SbtModule with CommonModule {
-    override def ivyDeps = super.ivyDeps() ++ Agg(getVersion("chisel3"))
+  object hardfloat extends Hardfloat
+
+  trait Hardfloat
+    extends millbuild.`rocket-chip`.hardfloat.common.HardfloatModule {
+
+    def scalaVersion: T[String] = T(defaultVersions("scala"))
+
+    override def millSourcePath = os.pwd / "rocket-chip" / "hardfloat" / "hardfloat"
+
+    def chiselModule = None
+
+    def chiselPluginJar = None
+
+    def chiselIvy = Some(getVersion("chisel"))
+
+    def chiselPluginIvy = Some(getVersion("chisel-plugin", cross = true))
   }
 
-  override def moduleDeps = super.moduleDeps ++ Seq(
-    cde, macros, hardfloat
-  )
+  object cde extends CDE
+
+  trait CDE
+    extends millbuild.`rocket-chip`.cde.common.CDEModule
+      with ScalaModule {
 
+    def scalaVersion: T[String] = T(defaultVersions("scala"))
+
+    override def millSourcePath = os.pwd / "rocket-chip" / "cde" / "cde"
+  }
 }
 
-object utility extends SbtModule with ScalafmtModule with CommonModule {
 
-  override def millSourcePath = millOuterCtx.millSourcePath
+object xsutils extends SbtModule with ScalafmtModule with CommonModule {
 
+  override def millSourcePath = os.pwd
+
+  override def moduleDeps = super.moduleDeps ++ Seq(rocketchip)
 
   override def ivyDeps = super.ivyDeps() ++ Agg(
-    getVersion("chisel3"),
-    getVersion("chiseltest"),
+    getVersion("chisel"),
+    getVersion("chiseltest", "edu.berkeley.cs"),
   )
 
-  override def moduleDeps = super.moduleDeps ++ Seq(`rocket-chip`)
-
-  object test extends Tests {
+  object test extends SbtModuleTests with TestModule.ScalaTest {
     override def ivyDeps = super.ivyDeps() ++ Agg(
       getVersion("scalatest","org.scalatest")
     )
 
-    def testFrameworks = Seq("org.scalatest.tools.Framework")
+    def testFramework = "org.scalatest.tools.Framework"
   }
-}
+}

src/main/scala/utility/ClockGate.scala

@@ -16,7 +16,10 @@
 package utility
 
 import chisel3._
+import chisel3.experimental.BaseModule
 import chisel3.util.HasBlackBoxInline
+import chisel3.util.experimental.BoringUtils
+import scala.collection.mutable
 
 class ClockGate extends BlackBox with HasBlackBoxInline {
   val io = IO(new Bundle {
@@ -59,12 +62,37 @@ class ClockGate extends BlackBox with HasBlackBoxInline {
   setInline("ClockGate.v", verilog)
 }
 
+class CgteBundle extends Bundle {
+  val te = Input(Bool())
+}
+
 object ClockGate {
-  def apply(TE: Bool, E: Bool, CK: Clock) : Clock = {
-    val clock_gate = Module(new ClockGate).io
-    clock_gate.TE := TE
-    clock_gate.E  := E
-    clock_gate.CK := CK
-    clock_gate.Q
+  private val teBoringQueue = new mutable.Queue[CgteBundle]
+  private val hashModulesHasCgen = new mutable.Queue[BaseModule]
+
+  def apply(TE: Bool, E: Bool, CK: Clock): Clock = {
+    val module = Module.currentModule.get
+    val cgbd = if (hashModulesHasCgen.contains(module)) {
+      teBoringQueue.last
+    } else {
+      val cg = Wire(new CgteBundle)
+      cg.te := TE
+      dontTouch(cg)
+      teBoringQueue.append(cg)
+      hashModulesHasCgen.append(module)
+      cg
+    }
+    val clockGate = Module(new ClockGate)
+    clockGate.io.E := E
+    clockGate.io.TE := cgbd.te
+    clockGate.io.CK := CK
+    clockGate.io.Q
+  }
+
+  def getTop: CgteBundle = {
+    val cgen = Wire(new CgteBundle)
+    teBoringQueue.toSeq.foreach(BoringUtils.bore(_) := cgen)
+    teBoringQueue.clear()
+    cgen
   }
 }

src/main/scala/utility/FileRegisters.scala

@@ -3,27 +3,36 @@ package utility
 import java.io.{File, FileWriter}
 
 object FileRegisters {
-  var files: Seq[(String, () => String)] = Nil
+  var files: Seq[(String, String, () => String)] = Nil
 
   def add(filename: String, contents: => String): Unit = {
-    files = (filename, () => contents) +: files
+    add("", filename, contents)
+  }
+
+  def add(filedir:String, filename:String, contents: => String) :Unit = {
+    val fn = () => contents
+    files = (filedir, filename, fn) +: files
   }
 
   def contains(filename: String): Boolean = {
-    files.foldLeft(false)((t, s) => {s._1 == filename | t})
+    files.count(_._2 == filename) != 0
   }
 
   def write(fileDir: String = "./build", filePrefix: String = ""): Unit = {
-    files.foreach { case (filename, contents) =>
-      writeOutputFile(fileDir, filePrefix + filename, contents())
+    files.foreach { case (fd, fn, fc) =>
+      writeOutputFile(fileDir, fd, filePrefix + fn, fc())
     }
   }
 
-  def writeOutputFile(targetDir: String, fname: String, contents: String): File = {
-    val f = new File(targetDir, fname)
+  def writeOutputFile(td: String, fd: String, fn:String, fc: String): File = {
+    val dirStr = if(fd == "") td else s"$td/$fd"
+    val dir = new File(dirStr)
+    if(!dir.exists()) require(dir.mkdirs())
+    val fname = s"$dirStr/$fn"
+    val f = new File(fname)
     val fw = new FileWriter(f)
-    fw.write(contents)
-    fw.close
+    fw.write(fc)
+    fw.close()
     f
   }
 }

src/main/scala/utility/ResetGen.scala

@@ -1,48 +1,65 @@
 /***************************************************************************************
-* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
-* Copyright (c) 2020-2021 Peng Cheng Laboratory
-*
-* XiangShan is licensed under Mulan PSL v2.
-* You can use this software according to the terms and conditions of the Mulan PSL v2.
-* You may obtain a copy of Mulan PSL v2 at:
-*          http://license.coscl.org.cn/MulanPSL2
-*
-* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
-* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
-* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
-*
-* See the Mulan PSL v2 for more details.
-***************************************************************************************/
+ * Copyright (c) 2020-2022 Institute of Computing Technology, Chinese Academy of Sciences
+ * Copyright (c) 2020-2022 Peng Cheng Laboratory
+ *
+ * XiangShan is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *          http://license.coscl.org.cn/MulanPSL2
+ *
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ *
+ * See the Mulan PSL v2 for more details.
+ ***************************************************************************************/
 
 package utility
 
 import chisel3._
 import chisel3.util._
+class DFTResetSignals extends Bundle{
+  val lgc_rst_n = AsyncReset()
+  val mode = Bool()
+  val scan_mode = Bool()
+}
 
 class ResetGen(SYNC_NUM: Int = 2) extends Module {
   val o_reset = IO(Output(AsyncReset()))
+  val dft = IO(Input(new DFTResetSignals()))
+  val raw_reset = IO(Output(AsyncReset()))
+
+  val lgc_rst = !dft.lgc_rst_n.asBool
+  val real_reset = Mux(dft.mode, lgc_rst, reset.asBool).asAsyncReset
 
-  val pipe_reset = RegInit(((1L << SYNC_NUM) - 1).U(SYNC_NUM.W))
-  pipe_reset := Cat(pipe_reset(SYNC_NUM - 2, 0), 0.U(1.W))
+  withClockAndReset(clock, real_reset){
+    val pipe_reset = RegInit(((1L << SYNC_NUM) - 1).U(SYNC_NUM.W))
+    pipe_reset := Cat(pipe_reset(SYNC_NUM - 2, 0), 0.U(1.W))
+    raw_reset := pipe_reset(SYNC_NUM - 1).asAsyncReset
+  }
 
   // deassertion of the reset needs to be synchronized.
-  o_reset := pipe_reset(SYNC_NUM - 1).asAsyncReset
+  o_reset := Mux(dft.scan_mode, lgc_rst, raw_reset.asBool).asAsyncReset
 }
 
 trait ResetNode
 
 case class ModuleNode(mod: Module) extends ResetNode
 case class CellNode(reset: Reset) extends ResetNode
-
 case class ResetGenNode(children: Seq[ResetNode]) extends ResetNode
 
 object ResetGen {
-  def apply(SYNC_NUM: Int = 2): AsyncReset = {
+  def apply(SYNC_NUM: Int = 2, dft:Option[DFTResetSignals] = None): AsyncReset = {
     val resetSync = Module(new ResetGen(SYNC_NUM))
+    if(dft.isDefined) {
+      resetSync.dft := dft.get
+    } else {
+      resetSync.dft := 0.U.asTypeOf(new DFTResetSignals)
+    }
     resetSync.o_reset
   }
 
-  def apply(resetTree: ResetNode, reset: Reset, sim: Boolean): Unit = {
+  def apply(resetTree: ResetNode, reset: Reset, dft:Option[DFTResetSignals], sim: Boolean): Unit = {
     if(!sim) {
       resetTree match {
         case ModuleNode(mod) =>
@@ -52,26 +69,39 @@ object ResetGen {
         case ResetGenNode(children) =>
           val next_rst = Wire(Reset())
           withReset(reset){
-            val resetGen = Module(new ResetGen)
-            next_rst := resetGen.o_reset
+            next_rst := ResetGen(2, dft)
           }
-          children.foreach(child => apply(child, next_rst, sim))
+          children.foreach(child => apply(child, next_rst, dft, sim))
       }
     }
   }
 
-  def apply(resetChain: Seq[Seq[Module]], reset: Reset, sim: Boolean): Seq[Reset] = {
+  def apply(resetChain: Seq[Seq[Module]], reset: Reset,  dft:Option[DFTResetSignals], sim: Boolean): Seq[Reset] = {
     val resetReg = Wire(Vec(resetChain.length + 1, Reset()))
     resetReg.foreach(_ := reset)
     for ((resetLevel, i) <- resetChain.zipWithIndex) {
       if (!sim) {
         withReset(resetReg(i)) {
-          val resetGen = Module(new ResetGen)
-          resetReg(i + 1) := resetGen.o_reset
+          resetReg(i + 1) := ResetGen(2, dft)
         }
       }
       resetLevel.foreach(_.reset := resetReg(i + 1))
     }
     resetReg.tail
   }
+
+  def applyOneLevel(resetSigs: Seq[Reset], reset: Reset, sim: Boolean): DFTResetSignals = {
+    val resetReg = Wire(Reset())
+    val dft = Wire(new DFTResetSignals())
+    resetReg := reset
+    if (!sim) {
+      withReset(reset) {
+        val resetGen = Module(new ResetGen)
+        resetReg := resetGen.o_reset
+        resetGen.dft := dft
+      }
+    }
+    resetSigs.foreach(_ := resetReg)
+    dft
+  }
 }