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1. booth-multiplier booth-multiplier Public

   booth multiplier algorithm is implemented in a redix-2 and a redix-4 manner. the radix-4 is called modified booth.

   Verilog 1

2. cache_memory cache_memory Public

   Verilog

3. Booth_multiplier Booth_multiplier Public

   Verilog

4. MIPS_single_cycle_design_verilog MIPS_single_cycle_design_verilog Public

   A mips processor design is aheived using design in verilog.

   Verilog