vata axi peripheral

Notes on the VATA AXI peripheral

AXI registers

The peripheral is setup with 64 x 32 bit wide registers. The first 32 registers are primarily registers that are written to. The second 32 are registers to read out, containing information from the PL. "Write" registers can of course be read, however writing data to the "wead" registers is meaningless and does nothing.

How the AXI registers are allocated:

Write registers

• register 0: control register
• register 1 - 17 : configuration register to send to ASIC
• register 18: hold time (lowest 16 bits). True value in seconds is set value * 10 ns. Set at any point to change hold time delay.
• register 19: power cycle delay
• register 20: trigger ack timeout
• register 21: trigger ena mask:
  • Bit 0-15: Trigger from local hits on VATA 0-15.
  • Bit 16: Trigger from TM's fast-or
  • Bit 17: Trigger from TM's trigger-ack

Read registers

• register 31-47: read-only, configuration register output from ASIC
• register 48-49: running counter out
• register 50-51: live-time counter out
• register 52: Event counter out

The Control Register

Upon writing to the 0th register, some action will happen depending on what is written.

• Writing 0: set the ASIC configuation register with what is currently in AXI registers 1-17
• Writing 1: read out the current ASIC configuation register, save to AXI reg's 32-48
• Writing 2: Trigger internal calibration pulse.
• Writing 3: power cycle the asic for power cycle delay (register 19 value) number of clock cycles
• Writing 4: Reset the event counter
• Writing 5: Force trigger the asic. THIS IS BEING PHASED OUT, BEING PUT INTO SYNC DISTRIBUTION IP
• Writing >=6 (or anything else): shouldn't do anything