vata axi peripheral

Notes on the VATA AXI peripheral

VATA state machine

AXI registers

The peripheral is setup with 64 x 32 bit wide registers. The first 32 registers are primarily registers that are written to. The second 32 are registers to read out, containing information from the PL. "Write" registers can of course be read, however writing data to the "read" registers is meaningless and does nothing.

How the AXI registers are allocated:

Write registers

• register 0: control register
• register 1 - 17 : configuration register to send to ASIC
• register 18: hold time (lowest 16 bits). True value in seconds is value * 10 ns. Set at any point to change hold time delay (change takes effect immmediately)
• register 19: power cycle delay
• register 20: trigger ack timeout
• register 21: trigger ena mask:
  • Bit 0-11: Trigger from local hits on VATA 0-11.
  • Bit 12: Trigger from TM's fast-or
  • Bit 13: Trigger from TM's trigger-ack
  • Bit 14: Forced trigger

Read registers

• register 31-47: read-only, configuration register output from ASIC
• register 48-49: running counter out
• register 50-51: live-time counter out
• register 52: Event counter out

The Control Register

Upon writing to the 0th register, some action will happen depending on what is written.

• Writing 0: set the ASIC configuation register with what is currently in AXI registers 1-17
• Writing 1: read out the current ASIC configuation register, save to AXI reg's 32-48
• Writing 2: Trigger internal calibration pulse.
• Writing 3: power cycle the asic for power cycle delay (register 19 value) number of clock cycles
• Writing 4: Reset the event counter
• Writing 5: Force the VATA FSM to transition to IDLE
• Writing >5: shouldn't do anything

Triggering Conditions

The VATA state machine starts going through its data conversion and readout states once a triggering condition is satisfied. A "triggering condition" is a combination of a trigger input, and trigger enable, both of which have to be high to kick the FSM out of IDLE to start acquisition. Any trigger condition being true starts acquisition.

Trigger Inputs:

• Force trigger: force a trigger, sent from software
• TM Hit: A "fast or" trigger from the trigger module
• TM Ack: Acknowledge signal from the TM. This should be enabled when a layer is integrated into the larger instrument
• Local vata hits: Triggers generated by ASICs on the silicon layer. This is 12 bits wide.

Manipulating trigger enables

All triggers are disabled on startup (I think). So you have to do some trigger enable manipulation to get things going.

Using vatactrl

From the executable help message:

Usage: vatactrl ASIC-NUM [OPTIONS]
  ASIC-NUM : Number of the ASIC we are targeting
  OPTIONS:
    ...
    --trigger-enable-bit BIT    : enable triggering from source associated with BIT. BIT can be 'all'
    --trigger-disable-bit BIT   : disable triggering from source associated with BIT. BIT can be 'all'
    --trigger-enable-asic ASIC  : enable triggering from asic number ASIC (an on-layer asic). ASIC can be 'all'
    --trigger-disable-asic ASIC : disable triggering from asic number ASIC (an on-layer asic). ASIC can be 'all'
    --trigger-enable-tm-hit     : enable triggering from trigger module hit signal.
    --trigger-disable-tm-hit    : disable triggering from trigger module hit signal.
    --trigger-enable-tm-ack     : enable triggering from trigger module ack signal.
    --trigger-disable-tm-ack    : disable triggering from trigger module ack signal.
    --trigger-enable-forced     : enable forced triggering.
    --trigger-disable-forced    : disable forced triggering.
    --get-trigger-ena-mask      : print the trigger-enable mask to stdout
    ...

The --trigger-enable-tm-hit, --trigger-enable-tm-ack, and --trigger-enable-forced will enable TM hits, TM acks', and forced triggers, respectively (you can guess what the corresponding "disable" options do)

Using --trigger-enable-asic will enable local asic triggers from a specific asic. After the option, you specify the ASIC (0-11), or you can specify all, which is the same as a local fast-or trigger.

Examples of --trigger-enable-asic usage

So, for example, if you want to allow ASIC 5 to trigger itself:

vatactrl 5 --trigger-enable-asic 5

Or, to enable asic 5 to take triggers from its neighbors asic 4 and asic 6:

vatactrl 5 --trigger-enable-asic 4 --trigger-enable-asic 6

Or, for all asics to accept all local asic triggers:

for asic in $(seq 0 11); do
    vatactrl $asic --trigger-enable-asic all
done

The --trigger-enable-bit is useful if you know where the corresponding trigger enable lies within the trigger-enable vector. Using the other options is preferable as bit locations can change. And I'm too lazy to spell them out here.

Using the silayer.client.Client

Here are the trigger enable methods, which behave similarly to the above vatactrl command options.

Client.trigger_enable_asic

• Signature: Client.trigger_enable_asic(self, vata, asic_number=None)
• Docstring: Enable triggers from the local asic. If asic_number is None, then enable triggers from all asics (equivalent to having a local "fast-or" trigger)

Client.trigger_enable_forced

• Signature: Client.trigger_enable_forced(self, vata)
• Docstring: Enable triggering off the force-trigger signal.

Client.trigger_enable_tm_hit

• Signature: Client.trigger_enable_tm_hit(self, vata)
• Docstring: Enable triggering off the trigger-module hit signal.

Client.trigger_enable_tm_ack

• Signature: Client.trigger_enable_tm_ack(self, vata)
• Docstring: Enable triggering off the trigger-module ack signal.

Client.trigger_enable_bit

• Signature: Client.trigger_enable_bit(self, vata, bit_number=None)
• Docstring: Enable the trigger bit for the given asic. If bit_number is None, then enable all triggers.

There are "disable" methods that correspond to each of the above "enable" methods.