vata axi peripheral

Notes on the VATA AXI peripheral

AXI registers

The peripheral is setup with 64 x 32 bit wide registers. The first 32 registers are primarily registers that are written to. The second 32 are registers to read out, containing information from the PL.

How the AXI registers are allocated:

• register 0: control register

• register 1 - 17 : configuration register to send to ASIC

• register 18: hold time (lowest 16 bits). True is set value * 10 ns. Set at any point to change hold time delay.

• register 19: cal dac value (lowest 12 bits)

• register 20: power cycle delay

• registers 21: trigger ack timeout

• register 32-48: read-only, configuration register output from ASIC

• register 49-50: running counter out

• register 51-52: live-time counter out

The Control Register

Upon writing to the 0th register, some action will happen depending on what is written.

• Writing 0: set the ASIC configuation register with what is currently in AXI registers 3-19
• Writing 1: read out the current ASIC configuation register to BRAM
• Writing 2: set the calibration DAC value with what is currently in AXI register 2
• Writing 3: trigger the calibration pulse
• Writing 4: Trigger internal calibration pulse.
• Writing 5: power cycle the asic for power cycle delay (register 3 value) number of clock cycles
• Writing 6: Reset the running/live clocks
• Writing 6 (or anything else): shouldn't do anything