vata axi peripheral

Notes on the VATA AXI peripheral

AXI registers

The peripheral is setup with 32 x 32 bit wide registers, How the AXI registers are allocated:

• register 0: control register
• register 1 - 17 : configuration register
• register 18: hold time (lowest 16 bits). True delay is set value * 10 ns. Set at any point to change hold time delay.
• register 19: cal dac value (lowest 12 bits)
• register 20: power cycle delay
• registers 21: trigger ack timeout

The Control Register

Upon writing to the 0th register, some action will happen depending on what is written.

• Writing 0: set the ASIC configuation register with what is currently in AXI registers 3-19
• Writing 1: read out the current ASIC configuation register to BRAM
• Writing 2: set the calibration DAC value with what is currently in AXI register 2
• Writing 3: trigger the calibration pulse
• Writing 4: Trigger internal calibration pulse.
• Writing 5: power cycle the asic for power cycle delay (register 3 value) number of clock cycles
• Writing 6 (or anything else): indicates read data is done.