BrianHG-DDR3-Controller v1.60

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BrianHG_DDR3_Controller V1.6 Release, June 11, 2022.
Includes new BrianHG_GFX_VGA_Window_System.

Folder BrianHG_DDR3 now contains the new v1.6 controller.
Main source files:

• BrianHG_DDR3_v15_and_v16_Block_Diagram.png -> Illustration of module connections.

• Includes these following sub-modules :

  • BrianHG_DDR3_CONTROLLER_v16_top.sv -> v1.6 TOP entry to the complete project which wires the DDR3_COMMANDER_v16 to the DDR3_PHY_SEQ giving you access to all the read/write ports + access to the DDR3 IO pins.
  • BrianHG_DDR3_COMMANDER_v16.sv -> v1.6 High FMAX speed multi-port read and write requests and cache, commands the BrianHG_DDR3_PHY_SEQ.sv sequencer.
  • BrianHG_DDR3_CMD_SEQUENCER_v16.sv -> v1.6 Takes in the read and write requests, generates a stream of DDR3 commands to execute the read and writes.
  • BrianHG_DDR3_PHY_SEQ_v16.sv -> v1.6 DDR3 PHY sequencer. (If you want just a compact DDR3 controller, skip the DDR3_CONTROLLER_top & DDR3_COMMANDER and just use this module alone.)
  • BrianHG_DDR3_PLL.sv -> Generates the system clocks. (*** Currently Altera/Intel only ***)
  • BrianHG_DDR3_GEN_tCK.sv -> Generates all the tCK count clock cycles for the DDR3_PHY_SEQ so that the DDR3 clock cycle requirements are met.
  • BrianHG_DDR3_FIFOs.sv -> Serial shifting logic FIFOs.

• Includes the following test-benches :

  • BrianHG_DDR3_CONTROLLER_v16_top_tb.sv -> Test the entire 'BrianHG_DDR3_CONTROLLER_v16_top.sv' system with Mircon's DDR3 Verilog model.
  • BrianHG_DDR3_COMMANDER_v16_tb.sv -> Test just the commander_v16. The 'DDR3_PHY_SEQ' is dummy simulated. (*** This one will simulate on any vendor's ModelSim ***)
  • BrianHG_DDR3_CMD_SEQUENCER_v16_tb.sv -> Test just the DDR3 command sequencer. (*** This one will simulate on any vendor's ModelSim ***)
  • BrianHG_DDR3_PHY_SEQ_v16_tb.sv -> Test just the DDR3 PHY sequencer with Mircon's DDR3 Verilog model providing logged DDR3 command results with any access violations listed.
  • BrianHG_DDR3_PLL_tb.sv -> Test just the PLL module.

• IO port vendor specific modules :

  • BrianHG_DDR3_IO_PORT_ALTERA.sv -> Physical DDR IO pin driver specifically for Altera/Intel Cyclone III/IV/V and MAX10.

• Modelsim 'do' script files.

  • All setup_xxx.do files setup their associated Modelsim simulation.
  • All run_xxx.do files quick re-compile and run their associated Modelsim simulation.

Folder 'BrianHG_DDR3_GFX_source_v16' contains my new BrianHG_GFX_VGA_Window_System multi-window system.
Main source files:

• BrianHG_GFX_VGA_Window_System.pdf -> Visual block diagram for the graphics system and layer-swapping illustration.

• BrianHG_GFX_VGA_Window_System.txt -> Full documentation for the VGA window system.

• Includes these top hierarchy files:

  • BrianHG_GFX_VGA_Window_System.sv -> Full window system where you drive the CMD_win_xxx controls via input ports.
  • BrianHG_GFX_VGA_Window_System_DDR3_REGS.sv -> Full window system where you drive the CMD_win_xxx controls via writing to DDR3 memory addresses through any multiport.

• Modelsim 'do' script files.

  • All setup_xxx.do files setup their associated Modelsim simulation.
  • All run_xxx.do files quick re-compile and run their associated Modelsim simulation.

New Arrow DECA board demo complete projects running the v1.6 BrianHG_DDR3_Controller conected to
the BrianHG_GFX_VGA_Window_System, all at 400MHz, all 100% timing requirements met.
Source folders:

• BrianHG_DDR3_DECA_GFX_DEMO_v16_1_LAYER -> Replaces the original ellipse demo, but now uses my new BrianHG_GFX_VGA_Window_System.
• BrianHG_DDR3_DECA_GFX_DEMO_v16_2_LAYERS -> Improved ellipse demo using 2 translucent windows scrolling at different speeds.
• BrianHG_DDR3_DECA_GFX_HWREGS_v16_16_LAYERS -> Example 16 window layer system where writes to the DDR3 controls the window's regs.
• BrianHG_DDR3_DECA_RS232_DEBUG_TEST_v16 -> Single port DDR3 controller example connected to my RS232 debugger.
• BrianHG_DDR3_DECA_PHY_SEQ_only_v16 -> (No multiport controller.) Bare minimum DDR3 PHY_SEQ controller connected to my RS232 debugger.

Test hypothetical builds for Cyclone III,IV,V to see if we can meet FMAX.

• BrianHG_DDR3_CIII_GFX_TEST_v16_1_LAYER_Q13.0sp1 -> Cyclone III example using Quartus 13.0 sp1.
• BrianHG_DDR3_CIV_GFX_TEST_v16_1_LAYER -> Cyclone IV example using Quartus 20.1.
• BrianHG_DDR3_CV_GFX_TEST_v16_1_LAYER_350MHz -> Cyclone V example running only at 350MHz using Quartus 20.1.

New demos:

• New 2 window translucent layer ellipse demo included in this release.

• New 16 window layer VGA system demo controlled by RS232_Debugger included in this release.

• User 'davemuscle' created an Avalon interface wrapper comparing my DDR3 PHY_SEQ_only free controller to Altera's expensive UniPHY IP, see here:
  https://www.eevblog.com/forum/fpga/brianhg_ddr3_controller-open-source-ddr3-controller/msg4108963/#msg4108963
  (Note that both controllers should have achieve double the bandwidth and my 'BrianHG_DDR3_DECA_GFX_DEMO_v16_2_LAYERS' demo already runs at double the efficiency.)

• User 'Nockieboy' has been working on integrating my controller with his Z80 8-bit GPU project, see his first multi-layer-window test here:
  https://www.eevblog.com/forum/fpga/fpga-vga-controller-for-8-bit-computer/msg3980567/#msg3980567
  and tile mode test:
  https://www.eevblog.com/forum/fpga/fpga-vga-controller-for-8-bit-computer/msg4029019/#msg4029019

BrianHG DDR3 Controller v1.50

BrianHG-DDR3-Controller

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BrianHG_DDR3_Controller V1.5
December 3, 2021

A maddening over 11K lines of code....

See image: https://github.com/BrianHGinc/BrianHG-DDR3-Controller/blob/main/BrianHG_DDR3_v15_Block_Diagram.png for a simplified block diagram of the BrianHG_DDR3_Controller_v15 controller system.

Note that the original v1.0 source files still exist, still function, and are backwards compatible, but understand that all the source files have been updated. This includes the new .sdc files in the new demo projects.

In-depth instructions are located in the full v1.0 text release notes as well as all the parameters and ports are well documented within the source code and examples.

These are the new main source file which operate according to the simplified block diagram:

New Version 1.5 source files:

BrianHG_DDR3_COMMANDER_v15.sv

• All 16 user multiports are now read and write ports instead of a separate 16 read ports and 16 write ports.
• Radically improved FMAX where a full 16 ports should achieve at least 150Mhz on a -6 Cyclone III/IV and MAX10.
• Sadly, Cyclone V-6 should achieve at least 88MHz where it used to be only 75MHz with just 2 ports.

BrianHG_DDR3_CONTROLLER_v15_top.sv

• Uses the new commander v15.
• Has a 'TAP' port which is a copy of all the writes being send to the DDR3.

New Version 1.5 example/demo projects (Arrow DECA board compatible):

BrianHG_DDR3_DECA_RS232_DEBUG_TEST_v15_300MHz_QR

• Functional on Arrow DECA board, an entry level example 300MHz DDR3, 1/4 rate multiport with RS232 debugger interface.
• Improved .sdc file for better DDR3 timing margins.

BrianHG_DDR3_DECA_Show_1080p_v15_375Mhz_HR

• Functional on Arrow DECA board 375MHz DDR3, 1/2 rate multiport example 1080p HDMI video out with RS232 debugger interface.
• Improved .sdc file for better DDR3 timing margins.

BrianHG_DDR3_DECA_Show_1080p_v15_400MHz_QR

• Functional on Arrow DECA board 400MHz DDR3, 1/4 rate multiport example 1080p HDMI video out with RS232 debugger interface.
• Improved .sdc file for better DDR3 timing margins.

BrianHG_DDR3_DECA_GFX_DEMO_v15_300MHz_HR

• Functional on Arrow DECA board 300MHz DDR3, 1/2 rate multiport example 1080p HDMI video out with RS232 debugger interface.
• Geometry random ellipse & noise generator demo, see: https://www.eevblog.com/forum/fpga/brianhg_ddr3_controller-open-source-ddr3-controller/msg3785711/#msg3785711 for instructions.
• Improved .sdc file for better DDR3 timing margins.

BrianHG_DDR3_DECA_GFX_DEMO_v15_400MHz_QR

• Functional on Arrow DECA board 400MHz DDR3, 1/4 rate multiport example 1080p HDMI video out with RS232 debugger interface.
• Geometry random ellipse & noise generator demo, see: https://www.eevblog.com/forum/fpga/brianhg_ddr3_controller-open-source-ddr3-controller/msg3785711/#msg3785711 for instructions.
• Improved .sdc file for better DDR3 timing margins.

BrianHG_DDR3_CV_GFX_FMAX_Test_v15_350MHz_QR

• Hypothetical Cyclone V FMAX compile test of the random ellipse & noise generator demo. Note that in v1.0, Cyclone V could barely achieve 300MHz 1/4 rate multiport with 3 ports running the geometry random ellipse & noise generator demo. v1.5 can now achieve 350MHz with more ports and some head-room to spare.
• Improved .sdc file for better DDR3 timing margins.

Note that Cyclone III/IV FMAX tests were not done since in v1.0, they actually perform slightly better than the MAX10 demos.

New Version 1.5 Modelsim Testbench source files and setup script files:

Version 1.5 test-bench, multiport commander:

• BrianHG_DDR3_COMMANDER_v15_tb.sv
• setup_com_v15.do -Modelsim setup sim script file.
• run_com_v15.do -Modelsim re-compile & run script file

Version 1.5 test-bench, complete ram controller system:

• BrianHG_DDR3_CONTROLLER_v15_top_tb.sv
• setup_top_v15.do -Modelsim setup sim script file.
• run_top_v15.do -Modelsim re-compile & run script file

Minor issues to fix / things to do for upcoming releases.

1. For the 1080p output, remove the DECAs example video sync generator and writ my own proper one which will allow a few real-time video mode selection.
2. Fix a bug with my raster generator which currently only functions properly in 1080p 32bit color, offering proper support for 1/2/4/8/16/32bit color modes.
3. Shrink the video line buffer to the minimal M9K block size allowed with a 128bit memory buss interface.
4. Add a palette support for lower depth video modes.
5. Add a hardware multi-layer-superimposed window system framework.

BrianHG DDR3 Controller v1.00

BrianHG DDR3 Controller v1.00, Altera/Intel Quartus Prime 20.1 build.