Fix some instructions + Atalanta derivation

Dockerfile

@@ -1,7 +1,7 @@
 FROM efabless/openlane-tools:yosys-cfe940a98b08f1a5d08fb44427db155ba1f18b62-centos-7 AS yosys
 # ---
 
-FROM swift:5.6-centos7 AS builder
+FROM swift:5.8-centos7 AS builder
 
 # Setup Build Environment
 RUN yum install -y --setopt=skip_missing_names_on_install=False https://dl.fedoraproject.org/pub/epel/epel-release-latest-7.noarch.rpm centos-release-scl

Package.swift

@@ -1,4 +1,4 @@
-// swift-tools-version:5.4
+// swift-tools-version:5.8
 // The swift-tools-version declares the minimum version of Swift required to build this package.
 
 import PackageDescription

Sources/Fault/BenchCircuit.swift

@@ -21,6 +21,12 @@ struct BenchCircuit: Codable {
     init(cells: [BenchCell]) {
         self.cells = cells
     }
+
+    static func represent(_ item: PythonObject) -> String {
+        return Python.type(item).__name__ == "Pointer" ?
+            "\(item.var)[\(item.ptr)]" :
+            "\(item)"
+    }
 
     static func extract(definitions: PythonObject) throws -> [BenchCell] {
         var cells: [BenchCell] = []
@@ -49,13 +55,12 @@ struct BenchCircuit: Codable {
                     if type == "InstanceList" {
                         let instance = item.instances[0]
 
-                        let outArgname = String(describing: instance.portlist[0].argname)
+                        let outArgname = represent(instance.portlist[0].argname)
                         let output = (outArgname == cellOutput) ? outArgname : "__\(outArgname)___"
 
                         var benchStatement = "("
                         for hook in instance.portlist[1...] {
-                            let argname = String(describing: hook.argname)
-
+                            let argname = represent(hook.argname)
                             if cellInputs.contains(argname) {
                                 benchStatement += "\(hook.argname), "
                             } else {
@@ -65,7 +70,6 @@ struct BenchCircuit: Codable {
 
                         benchStatement = String(benchStatement.dropLast(2))
                         benchStatement += ")"
-
                         switch instance.module {
                         case "and":
                             cellStatements.append("\(output) = AND" + benchStatement)

Sources/Fault/Entries/atpg.swift

@@ -61,7 +61,7 @@ extension Fault {
         @Option(help: "A \(MemoryLayout<UInt>.size)-byte value to use as an RNG seed for test vector generators, provided as a hexadecimal string (without 0x).")
         var rngSeed: String = "DEADCAFEDEADF00D"
 
-        @Option(help: "Use an external TV Generator: Atalanta or PODEM.")
+        @Option(name: [.customShort("g"), .long], help: "Use an external TV Generator: Atalanta or PODEM.")
         var etvGen: String?
 
         @Option(name: [.short, .long], help: "Netlist in bench format. (Required iff generator is set to Atalanta or PODEM.)")

Sources/Fault/Entries/bench.swift

@@ -72,11 +72,11 @@ extension Fault {
                     cellDefinitions = matches.joined(separator: "\n")
 
                     let folderName = "\(NSTemporaryDirectory())/thr\(Unmanaged.passUnretained(Thread.current).toOpaque())"
-                    let _ = "mkdir -p \(folderName)".sh()
-
+                    try? FileManager.default.createDirectory(atPath: folderName, withIntermediateDirectories: true, attributes: nil)
                     defer {
-                        let _ = "rm -rf \(folderName)".sh()
+                        try? FileManager.default.removeItem(atPath: folderName)
                     }
+
                     let cellFile = "\(folderName)/cells.v"
 
                     try File.open(cellFile, mode: .write) {
@@ -170,7 +170,7 @@ extension Fault {
 
                     for hook in instance.portlist {
                         let portname = String(describing: hook.portname)
-                        let argname = String(describing: hook.argname)
+                        let argname = BenchCircuit.represent(hook.argname)
 
                         if portname == cell.output {
                             outputs.append(argname)
@@ -185,13 +185,8 @@ extension Fault {
                     usedInputs.append(contentsOf: Array(inputs.values))
 
                 } else if type == "Assign" {
-                    let right = Python.type(item.right.var).__name__ == "Pointer" ?
-                        "\(item.right.var.var)[\(item.right.var.ptr)]" :
-                        "\(item.right.var)"
-
-                    let left = Python.type(item.left.var).__name__ == "Pointer" ?
-                        "\(item.left.var.var)[\(item.left.var.ptr)]" :
-                        "\(item.left.var)"
+                    let right = BenchCircuit.represent(item.right.var)
+                    let left = BenchCircuit.represent(item.left.var)
 
                     if right == "1'b0" || right == "1'h0" {
                         print("[Warning]: Constants are not recognized by atalanta. Removing \(left) associated gates and nets..")

Sources/Fault/Simulation.swift

@@ -67,7 +67,7 @@ enum Simulator {
         }
 
         let folderName = "\(filePrefix)/thr\(Unmanaged.passUnretained(Thread.current).toOpaque())"
-        _ = "mkdir -p \(folderName)".sh()
+        try FileManager.default.createDirectory(atPath: folderName, withIntermediateDirectories: true, attributes: nil)
 
         var inputAssignment = ""
         var fmtString = ""
@@ -196,7 +196,7 @@ enum Simulator {
         let output = File.read(intermediate)!
         defer {
             if cleanUp {
-                _ = "rm -rf \(folderName)".sh()
+                try? FileManager.default.removeItem(atPath: folderName)
             } else {
                 print("Find testbenches at : \(folderName)")
             }

Sources/Fault/String.swift

@@ -44,7 +44,7 @@ extension String {
         let task = Process()
         task.executableURL = URL(fileURLWithPath: "/bin/sh")
         task.arguments = ["-c", self]
-
+        //print("$ \(self)")
         if silent {
             task.standardOutput = FileHandle.nullDevice
             task.standardError = FileHandle.nullDevice

Sources/Fault/TVGenerator.swift

@@ -248,13 +248,13 @@ class Atalanta: ExternalTestVectorGenerator {
         let tempDir = "\(NSTemporaryDirectory())"
 
         let folderName = "\(tempDir)thr\(Unmanaged.passUnretained(Thread.current).toOpaque())"
-        let _ = "mkdir -p '\(folderName)'".sh()
+        try? FileManager.default.createDirectory(atPath: folderName, withIntermediateDirectories: true, attributes: nil)
         defer {
-            let _ = "rm -rf '\(folderName)'".sh()
+            try? FileManager.default.removeItem(atPath: folderName)
         }
 
         let output = "\(folderName)/\(module).test"
-        let atalanta = "atalanta -t \(output) \(file) > /dev/null 2>&1".sh()
+        let atalanta = "atalanta -t \(output) \(file)".sh()
 
         if atalanta != EX_OK {
             exit(atalanta)
@@ -279,9 +279,9 @@ class PODEM: ExternalTestVectorGenerator {
         let tempDir = "\(NSTemporaryDirectory())"
 
         let folderName = "\(tempDir)thr\(Unmanaged.passUnretained(Thread.current).toOpaque())"
-        let _ = "mkdir -p '\(folderName)'".sh()
+        try? FileManager.default.createDirectory(atPath: folderName, withIntermediateDirectories: true, attributes: nil)
         defer {
-            let _ = "rm -rf '\(folderName)'".sh()
+            try? FileManager.default.removeItem(atPath: folderName)
         }
 
         let output = "\(folderName)/\(module).out"

default.nix

@@ -8,6 +8,7 @@
   python3,
   yosys,
   verilog,
+  quaigh,
   ncurses,
   makeBinaryWrapper,
 }:
@@ -42,6 +43,7 @@ stdenv.mkDerivation (finalAttrs: {
     pyenv
     yosys
     verilog
+    quaigh
   ];
 
   buildInputs = with swiftPackages; [
@@ -87,5 +89,12 @@ stdenv.mkDerivation (finalAttrs: {
       --set FAULT_IVL_BASE ${verilog}/lib/ivl
   '';
 
+  meta = with lib; {
+    description = "Open-source EDA's missing DFT toolchain";
+    homepage = "https://github.com/AUCOHL/Fault";
+    license = licenses.asl20;
+    platforms = platforms.linux ++ platforms.darwin;
+  };
+
   shellHook = finalAttrs.preCheck + finalAttrs.preBuild;
 })

docs/Source/usage.md

@@ -77,7 +77,7 @@ is increased if sufficient coverage isn't met. This is done by the following
 options:
 
 ```bash
-fault -v <initial TV count> -r <increment> -m <minCoverage> --ceiling <TV count ceiling> -c <cell models> <netlist> 
+fault -v <initial TV count> -r <increment> -m <minCoverage> --ceiling <TV count ceiling> -c <cell models> --clock <clock port> --reset <reset port> [--ignoring <ignored port 1> [--ignoring <ignored port 2> ] ] [ --activeLow] <netlist> 
 ```
 
 - `-v`: Number of the initially generated test vectors.
@@ -96,6 +96,14 @@ fault -v <initial TV count> -r <increment> -m <minCoverage> --ceiling <TV count
 
 - `-c`: The cell models to use for simulations.
 
+- `--clock`: The name of the clock port.
+
+- `--ignoring`: The name of any other ports to ignore during ATPG, which will
+  be held high.
+
+- `--activeLow`: If set, all ports specified by `--ignoring` will be held low
+  instead.
+
 In this example, we will use a minimum coverage of `95%`, an increment of `50`,
 an initial test vector set size of `100` , and a ceiling of `1000` test vectors.
 
@@ -105,7 +113,7 @@ generator will be used for pseudo-random number generation.
 To run the simulations, invoke the following:
 
 ```bash
- fault -c Tech/osu035/osu035_stdcells.v -v 100 -r 50 -m 95 --ceiling 1000 Netlists/s27.nl.v.cut.v
+fault -c Tech/osu035/osu035_stdcells.v -v 100 -r 50 -m 95 --ceiling 1000 --clock CK --ignoring reset Netlists/s27.nl.v.cut.v
 ```
 
 This will generate the coverage at the default path:
@@ -143,12 +151,12 @@ The bench netlist will be generated at ` Netlists/s27.nl.v.cut.v.bench`
 After the bench netlist is created, we can generate test vectors using atalanta
 and run fault simulations by setting the following options:
 
-- `-g`: Type of the test vector generator. Set to `atalanta`
+- `-g`: Type of the test vector generator. Set to `Atalanta`
 - `-c`: Cell models file path.
 - `-b`: Path to the bench netlist.
 
 ```bash
-    fault -g atalanta -c Tech/osu035/osu035_stdcells.v -b Netlists/s27.nl.v.cut.v.bench Netlists/s27.nl.v.cut.v
+    fault -g Atalanta -c Tech/osu035/osu035_stdcells.v -b Netlists/s27.nl.v.cut.v.bench Netlists/s27.nl.v.cut.v
 ```
 
 This will run the simulations with the default options for the initial TV count,
@@ -179,7 +187,7 @@ path at: `fault compact Netlists/s27.nl.v.cut.v.tv.json.compacted.json`
 It has the following options:
 
 ```bash
- fault chain -i <inputs-to-ingnore> --clock <clk-signal> --reset <rst-signal> -l <liberty-file> -c <cell-models-file> -o <path-to-chained-netlist> <flattened-netlist-path>
+ fault chain -i <inputs-to-ignore> --clock <clk-signal> --reset <rst-signal> -l <liberty-file> -c <cell-models-file> -o <path-to-chained-netlist> <flattened-netlist-path>
 ```
 
 - `-i`: Specifies the inputs to ignore (if any)
@@ -209,8 +217,9 @@ set the following options:
 - `-o`: Path to the output file. (Default: input + .jtag.v)
 - `--clock`: Clock signal of core logic to use in simulation
 - `--reset`: Reset signal of core logic to use in simulation.
-- `--activeLow`: Reset signal of core logic is active low instead of active
-  high.
+- `--ignoring`: Other signals to ignore
+- `--activeLow`: Ignored signals (including reset) signal of core logic are held
+  low instead of high.
 - `-c`: Cell models file to verify JTAG port using given cell model.
 - `-l`: Path to the liberty file for resynthesis.