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i2c: stm32: dma enhancement #81814

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i2c: stm32: dma enhancement #81814

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5ebd513
i2c: stm32: Add config option to enable DMA support
sgilbert182 Nov 23, 2024
253557b
i2c: stm32: Add dma settings structs to config and data structs
sgilbert182 Nov 23, 2024
ee3915e
i2c: stm32: Add macros to get settings from device tree
sgilbert182 Nov 23, 2024
5b8e89f
i2c: stm32: Add dma header files
sgilbert182 Nov 23, 2024
63538cc
i2c: stm32: Add DMA settings to yaml file
sgilbert182 Nov 23, 2024
ff5602b
i2c: stm32: Minor refactor of i2c_stm32_transfer function
sgilbert182 Nov 23, 2024
207cf56
i2c: stm32: Added DMA stop for various i2c comms conditions
sgilbert182 Nov 23, 2024
b394ecb
i2c: stm32: Clang format
sgilbert182 Nov 25, 2024
dee3c6e
i2c: stm32: Add assert catches in callbacks
sgilbert182 Nov 26, 2024
9a6a2f5
i2c: stm32: refactor use of DMA device config and settings
sgilbert182 Nov 26, 2024
8c030ea
i2c: stm32: Clang format
sgilbert182 Nov 27, 2024
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8 changes: 8 additions & 0 deletions drivers/i2c/Kconfig.stm32
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Original file line number Diff line number Diff line change
Expand Up @@ -55,4 +55,12 @@ config I2C_STM32_V2_TIMING
help
Enable STM32 driver bus to calculate the Timing.

config I2C_DMA
bool "DMA support"
depends on I2C_STM32_V2
select DMA
select CACHE_MANAGEMENT if CPU_HAS_DCACHE
help
Enable DMA support for the STM32 I2C driver.

endif # I2C_STM32
251 changes: 168 additions & 83 deletions drivers/i2c/i2c_ll_stm32.c
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Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,8 @@
* SPDX-License-Identifier: Apache-2.0
*/

#include <zephyr/drivers/dma.h>
#include <zephyr/drivers/dma/dma_stm32.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/pm/device.h>
Expand Down Expand Up @@ -63,16 +65,13 @@ int i2c_stm32_get_config(const struct device *dev, uint32_t *config)
/* I2C BIT RATE */
if (data->current_timing.i2c_speed == 100000) {
LOG_INF("timings = <%d I2C_BITRATE_STANDARD 0x%X>;",
data->current_timing.periph_clock,
data->current_timing.timing_setting);
data->current_timing.periph_clock, data->current_timing.timing_setting);
} else if (data->current_timing.i2c_speed == 400000) {
LOG_INF("timings = <%d I2C_BITRATE_FAST 0x%X>;",
data->current_timing.periph_clock,
LOG_INF("timings = <%d I2C_BITRATE_FAST 0x%X>;", data->current_timing.periph_clock,
data->current_timing.timing_setting);
} else if (data->current_timing.i2c_speed == 1000000) {
LOG_INF("timings = <%d I2C_SPEED_FAST_PLUS 0x%X>;",
data->current_timing.periph_clock,
data->current_timing.timing_setting);
data->current_timing.periph_clock, data->current_timing.timing_setting);
}
#endif /* CONFIG_I2C_STM32_V2_TIMING */

Expand Down Expand Up @@ -137,13 +136,14 @@ int i2c_stm32_runtime_configure(const struct device *dev, uint32_t config)
return ret;
}

#define OPERATION(msg) (((struct i2c_msg *) msg)->flags & I2C_MSG_RW_MASK)
#define OPERATION(msg) (((struct i2c_msg *)msg)->flags & I2C_MSG_RW_MASK)

static int i2c_stm32_transfer(const struct device *dev, struct i2c_msg *msg,
uint8_t num_msgs, uint16_t slave)
static int i2c_stm32_transfer(const struct device *dev, struct i2c_msg *msg, uint8_t num_msgs,
uint16_t slave)
{
struct i2c_stm32_data *data = dev->data;
struct i2c_msg *current, *next;
struct i2c_msg *current;
struct i2c_msg *next = NULL;
int ret = 0;

/* Check for validity of all messages, to prevent having to abort
Expand Down Expand Up @@ -369,16 +369,14 @@ static int i2c_stm32_activate(const struct device *dev)
}

/* Enable device clock. */
if (clock_control_on(clk,
(clock_control_subsys_t) &cfg->pclken[0]) != 0) {
if (clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken[0]) != 0) {
LOG_ERR("i2c: failure enabling clock");
return -EIO;
}

return 0;
}


static int i2c_stm32_init(const struct device *dev)
{
const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
Expand All @@ -391,6 +389,11 @@ static int i2c_stm32_init(const struct device *dev)
cfg->irq_config_func(dev);
#endif

#ifdef CONFIG_I2C_DMA
k_sem_init(&data->dma_rx_sem, 1, K_SEM_MAX_LIMIT);
k_sem_init(&data->dma_tx_sem, 1, K_SEM_MAX_LIMIT);
Comment on lines +393 to +394
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See definition for K_SEM_MAX_LIMIT

This is intended for use when a semaphore does not have an explicit maximum limit, and instead is just used for counting purposes.

Are you sure this is the intended behavior in this case ?

Note that we probably have other bad usages elsewhere.

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I used this to catch an unknown number of threads accessing the same I2C bus, do you have any known good usages I can follow instead?

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k_sem_init(&data->dma_rx_sem, 1, 1);
k_sem_init(&data->dma_tx_sem, 1, 1);

#endif

data->is_configured = false;
data->mode = I2CSTM32MODE_I2C;

Expand All @@ -410,9 +413,7 @@ static int i2c_stm32_init(const struct device *dev)

if (IS_ENABLED(STM32_I2C_DOMAIN_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) {
/* Enable I2C clock source */
ret = clock_control_configure(clk,
(clock_control_subsys_t) &cfg->pclken[1],
NULL);
ret = clock_control_configure(clk, (clock_control_subsys_t)&cfg->pclken[1], NULL);
if (ret < 0) {
return -EIO;
}
Expand Down Expand Up @@ -535,45 +536,88 @@ void i2c_stm32_smbalert_disable(const struct device *dev)
}
#endif /* CONFIG_SMBUS_STM32 */

#ifdef CONFIG_I2C_DMA
/* This function is executed in the interrupt context */
static void dma_rx_callback(const struct device *dma_dev, void *user_data, uint32_t channel,
int status)
{
struct i2c_stm32_data *data = (struct i2c_stm32_data *)user_data;

switch (status) {
case DMA_STATUS_COMPLETE:
data->current.is_err = 0;
dma_stop(dma_dev, channel);
break;
case DMA_STATUS_BLOCK:
__ASSERT(false, "Unsupported feature");
break;
default:
data->current.is_err = 1;
break;
}

k_sem_give(&data->device_sync_sem);
}

/* This function is executed in the interrupt context */
static void dma_tx_callback(const struct device *dma_dev, void *user_data, uint32_t channel,
int status)
{
struct i2c_stm32_data *data = (struct i2c_stm32_data *)user_data;

switch (status) {
case DMA_STATUS_COMPLETE:
data->current.is_err = 0;
dma_stop(dma_dev, channel);
break;
case DMA_STATUS_BLOCK:
__ASSERT(false, "Unsupported feature");
break;
default:
data->current.is_err = 1;
break;
}

LOG_DBG("Giving semaphore");
k_sem_give(&data->device_sync_sem);
}

#endif /* CONFIG_I2C_DMA */

/* Macros for I2C instance declaration */

#ifdef CONFIG_I2C_STM32_INTERRUPT

#ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
#define STM32_I2C_IRQ_CONNECT_AND_ENABLE(index) \
do { \
IRQ_CONNECT(DT_INST_IRQN(index), \
DT_INST_IRQ(index, priority), \
stm32_i2c_combined_isr, \
DEVICE_DT_INST_GET(index), 0); \
irq_enable(DT_INST_IRQN(index)); \
#define STM32_I2C_IRQ_CONNECT_AND_ENABLE(index) \
do { \
IRQ_CONNECT(DT_INST_IRQN(index), DT_INST_IRQ(index, priority), \
stm32_i2c_combined_isr, DEVICE_DT_INST_GET(index), 0); \
irq_enable(DT_INST_IRQN(index)); \
} while (false)
#else
#define STM32_I2C_IRQ_CONNECT_AND_ENABLE(index) \
do { \
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, event, irq), \
DT_INST_IRQ_BY_NAME(index, event, priority),\
stm32_i2c_event_isr, \
DEVICE_DT_INST_GET(index), 0); \
irq_enable(DT_INST_IRQ_BY_NAME(index, event, irq)); \
\
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, error, irq), \
DT_INST_IRQ_BY_NAME(index, error, priority),\
stm32_i2c_error_isr, \
DEVICE_DT_INST_GET(index), 0); \
irq_enable(DT_INST_IRQ_BY_NAME(index, error, irq)); \
#define STM32_I2C_IRQ_CONNECT_AND_ENABLE(index) \
do { \
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, event, irq), \
DT_INST_IRQ_BY_NAME(index, event, priority), stm32_i2c_event_isr, \
DEVICE_DT_INST_GET(index), 0); \
irq_enable(DT_INST_IRQ_BY_NAME(index, event, irq)); \
\
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, error, irq), \
DT_INST_IRQ_BY_NAME(index, error, priority), stm32_i2c_error_isr, \
DEVICE_DT_INST_GET(index), 0); \
irq_enable(DT_INST_IRQ_BY_NAME(index, error, irq)); \
} while (false)
#endif /* CONFIG_I2C_STM32_COMBINED_INTERRUPT */

#define STM32_I2C_IRQ_HANDLER_DECL(index) \
static void i2c_stm32_irq_config_func_##index(const struct device *dev)
#define STM32_I2C_IRQ_HANDLER_FUNCTION(index) \
.irq_config_func = i2c_stm32_irq_config_func_##index,
#define STM32_I2C_IRQ_HANDLER(index) \
static void i2c_stm32_irq_config_func_##index(const struct device *dev) \
{ \
STM32_I2C_IRQ_CONNECT_AND_ENABLE(index); \
}
#define STM32_I2C_IRQ_HANDLER_DECL(index) \
static void i2c_stm32_irq_config_func_##index(const struct device *dev)
#define STM32_I2C_IRQ_HANDLER_FUNCTION(index) .irq_config_func = i2c_stm32_irq_config_func_##index,
#define STM32_I2C_IRQ_HANDLER(index) \
static void i2c_stm32_irq_config_func_##index(const struct device *dev) \
{ \
STM32_I2C_IRQ_CONNECT_AND_ENABLE(index); \
}
#else

#define STM32_I2C_IRQ_HANDLER_DECL(index)
Expand All @@ -582,44 +626,85 @@ static void i2c_stm32_irq_config_func_##index(const struct device *dev) \

#endif /* CONFIG_I2C_STM32_INTERRUPT */

#define STM32_I2C_INIT(index) \
STM32_I2C_IRQ_HANDLER_DECL(index); \
\
IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \
(static const uint32_t i2c_timings_##index[] = \
DT_INST_PROP_OR(index, timings, {});)) \
\
PINCTRL_DT_INST_DEFINE(index); \
\
static const struct stm32_pclken pclken_##index[] = \
STM32_DT_INST_CLOCKS(index); \
\
static const struct i2c_stm32_config i2c_stm32_cfg_##index = { \
.i2c = (I2C_TypeDef *)DT_INST_REG_ADDR(index), \
.pclken = pclken_##index, \
.pclk_len = DT_INST_NUM_CLOCKS(index), \
STM32_I2C_IRQ_HANDLER_FUNCTION(index) \
.bitrate = DT_INST_PROP(index, clock_frequency), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
IF_ENABLED(CONFIG_I2C_STM32_BUS_RECOVERY, \
(.scl = GPIO_DT_SPEC_INST_GET_OR(index, scl_gpios, {0}),\
.sda = GPIO_DT_SPEC_INST_GET_OR(index, sda_gpios, {0}),))\
IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \
#ifdef CONFIG_I2C_DMA

#define I2C_DMA_INIT(index, dir) \
.dir##_dma = {.dev_dma = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \
(DEVICE_DT_GET(STM32_DMA_CTLR(index, dir))), (NULL)), \
.dma_channel = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \
(DT_INST_DMAS_CELL_BY_NAME(index, dir, channel)), (-1))},

#define I2C_DMA_SLOT_INIT(index, dir) \
.dma_slot = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \
(DT_INST_DMAS_CELL_BY_NAME(index, dir, slot)), (0))

#define I2C_DMA_CFG_INIT(index, name, dir, src, dest, src_addr_incr, dest_addr_incr) \
.dma_##dir##_cfg = \
{ \
I2C_DMA_SLOT_INIT(index, dir), \
.channel_direction = \
STM32_DMA_CONFIG_DIRECTION(STM32_DMA_CHANNEL_CONFIG(index, dir)), \
.source_data_size = STM32_DMA_CONFIG_##src##_DATA_SIZE( \
STM32_DMA_CHANNEL_CONFIG(index, dir)), \
.dest_data_size = STM32_DMA_CONFIG_##dest##_DATA_SIZE( \
STM32_DMA_CHANNEL_CONFIG(index, dir)), \
.source_burst_length = 1, \
.dest_burst_length = 1, \
.channel_priority = \
STM32_DMA_CONFIG_PRIORITY(STM32_DMA_CHANNEL_CONFIG(index, dir)), \
.dma_callback = dma_##dir##_callback, \
}, \
.dma_##dir##_blk_cfg = { \
.source_addr_adj = src_addr_incr, \
.dest_addr_adj = dest_addr_incr, \
},

#else

#define I2C_DMA_INIT(index, dir)

#define I2C_DMA_SLOT_INIT(index, dir)

#define I2C_DMA_CFG_INIT(index, name, dir, src, dest, src_addr_incr, dest_addr_incr)

#endif

#define STM32_I2C_INIT(index) \
STM32_I2C_IRQ_HANDLER_DECL(index); \
\
IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \
(static const uint32_t i2c_timings_##index[] = \
DT_INST_PROP_OR(index, timings, {});)) \
\
PINCTRL_DT_INST_DEFINE(index); \
\
static const struct stm32_pclken pclken_##index[] = STM32_DT_INST_CLOCKS(index); \
\
static const struct i2c_stm32_config i2c_stm32_cfg_##index = { \
.i2c = (I2C_TypeDef *)DT_INST_REG_ADDR(index), \
.pclken = pclken_##index, \
.pclk_len = DT_INST_NUM_CLOCKS(index), \
STM32_I2C_IRQ_HANDLER_FUNCTION(index).bitrate = \
DT_INST_PROP(index, clock_frequency), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
IF_ENABLED(CONFIG_I2C_STM32_BUS_RECOVERY, \
(.scl = GPIO_DT_SPEC_INST_GET_OR(index, scl_gpios, {0}), \
.sda = GPIO_DT_SPEC_INST_GET_OR(index, sda_gpios, {0}),)) \
IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \
(.timings = (const struct i2c_config_timing *) i2c_timings_##index,\
.n_timings = ARRAY_SIZE(i2c_timings_##index),)) \
}; \
\
static struct i2c_stm32_data i2c_stm32_dev_data_##index; \
\
PM_DEVICE_DT_INST_DEFINE(index, i2c_stm32_pm_action); \
\
I2C_DEVICE_DT_INST_DEFINE(index, i2c_stm32_init, \
PM_DEVICE_DT_INST_GET(index), \
&i2c_stm32_dev_data_##index, \
&i2c_stm32_cfg_##index, \
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
&api_funcs); \
\
STM32_I2C_IRQ_HANDLER(index)
.n_timings = ARRAY_SIZE(i2c_timings_##index),)) \
I2C_DMA_INIT(index, tx) \
I2C_DMA_INIT(index, \
rx)}; \
\
static struct i2c_stm32_data i2c_stm32_dev_data_##index; \
\
PM_DEVICE_DT_INST_DEFINE(index, i2c_stm32_pm_action); \
\
I2C_DEVICE_DT_INST_DEFINE(index, i2c_stm32_init, PM_DEVICE_DT_INST_GET(index), \
&i2c_stm32_dev_data_##index, &i2c_stm32_cfg_##index, \
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, &api_funcs); \
\
STM32_I2C_IRQ_HANDLER(index)

DT_INST_FOREACH_STATUS_OKAY(STM32_I2C_INIT)
21 changes: 21 additions & 0 deletions drivers/i2c/i2c_ll_stm32.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,8 @@
#include <zephyr/drivers/gpio.h>
#endif /* CONFIG_I2C_STM32_BUS_RECOVERY */

#include <zephyr/drivers/dma.h>

typedef void (*irq_config_func_t)(const struct device *port);

#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2)
Expand All @@ -31,6 +33,13 @@ struct i2c_config_timing {
};
#endif

#ifdef CONFIG_I2C_DMA
struct stream {
const struct device *dev_dma;
int32_t dma_channel;
};
#endif /* CONFIG_I2C_DMA */

struct i2c_stm32_config {
#ifdef CONFIG_I2C_STM32_INTERRUPT
irq_config_func_t irq_config_func;
Expand All @@ -48,6 +57,10 @@ struct i2c_stm32_config {
const struct i2c_config_timing *timings;
size_t n_timings;
#endif
#ifdef CONFIG_I2C_DMA
struct stream tx_dma;
struct stream rx_dma;
#endif /* CONFIG_I2C_DMA */
};

struct i2c_stm32_data {
Expand Down Expand Up @@ -91,6 +104,14 @@ struct i2c_stm32_data {
i2c_stm32_smbalert_cb_func_t smbalert_cb_func;
const struct device *smbalert_cb_dev;
#endif
#ifdef CONFIG_I2C_DMA
struct dma_config dma_tx_cfg;
struct dma_block_config dma_tx_blk_cfg;
struct k_sem dma_tx_sem;
struct dma_config dma_rx_cfg;
struct dma_block_config dma_rx_blk_cfg;
struct k_sem dma_rx_sem;
#endif /* CONFIG_I2C_DMA */
};

int32_t stm32_i2c_transaction(const struct device *dev,
Expand Down
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