-
Notifications
You must be signed in to change notification settings - Fork 621
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
RISC-V port implementation #368
Comments
[Krystian Kisielak]
We would gladly accept any feedback, thank you!
I can not really help with the code, but can tell you I am very happy to
read that you are working on an optimized RISC-V implementation. Keep
up the good work. :)
…--
Happy hacking
Petter Reinholdtsen
|
This is indeed good news. Here's a few questions/suggestions on how to proceed:
|
Ad.1 We are opting for 'somewhat capable' devices with vector units operating on floats. So fixed point is less important. |
The first thing I would check is whether you want to set OPUS_FAST_INT64 to 0 or 1 in celt/arch.h. For float, it will not make a difference for CELT, but it will have an impact on SILK. So you might want to pick whichever value makes SILK run the fastest before you optimize (because that changes the exact behaviour). |
I want to announce that we are currently working on RISC-V implementation using vector extension.
As we I mean: Samsung R&D Poland + partially RISE Project engineers
Code is being developed on feature branch at: https://github.com/k-kisielak/opus/tree/rvv_impl
Implementation is in early stage and is not deemed for merging in current form.
Current state:
We started with implementing parts of silk module:
Items under development:
We would gladly accept any feedback, thank you!
The text was updated successfully, but these errors were encountered: