From 0f1dfcf5ffe711306659586d70f4bb6bea2e4c22 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 21 Feb 2024 23:23:41 -0800 Subject: [PATCH] fpga/mqnic: Normalize RAM size settings Signed-off-by: Alex Forencich --- fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile | 2 +- fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py | 2 +- fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile | 2 +- fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py | 2 +- fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl | 2 +- fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile | 2 +- .../ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py | 2 +- fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.py | 2 +- fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g/config.tcl | 2 +- fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g_24AR0/config.tcl | 2 +- fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/config.tcl | 2 +- fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/config.tcl | 2 +- fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile | 4 ++-- .../DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py | 4 ++-- fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g/config.tcl | 2 +- .../mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g_24AR0/config.tcl | 2 +- fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile | 2 +- .../fpga/tb/fpga_core/test_fpga_core.py | 2 +- fpga/mqnic/IA_420F/fpga_100g/fpga_25g/config.tcl | 2 +- fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile | 2 +- fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py | 2 +- fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl | 2 +- fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/config.tcl | 2 +- fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile | 4 ++-- fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py | 4 ++-- fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile | 2 +- .../mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py | 2 +- fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile | 2 +- .../mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py | 2 +- fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl | 2 +- fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile | 4 ++-- fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py | 4 ++-- fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile | 2 +- fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py | 2 +- fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S/config.tcl | 2 +- fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile | 2 +- fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py | 2 +- fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile | 2 +- fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py | 2 +- .../ZCU102/fpga/tb/fpga_core_app_custom_port_demo/Makefile | 2 +- .../fpga/tb/fpga_core_app_custom_port_demo/test_fpga_core.py | 2 +- fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile | 2 +- fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py | 2 +- fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile | 2 +- fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py | 2 +- fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile | 2 +- fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py | 2 +- fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile | 2 +- fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py | 2 +- 49 files changed, 55 insertions(+), 55 deletions(-) diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile index 4a644e7d7..7dc7e4579 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile @@ -174,7 +174,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_LFC_ENABLE := 1 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 +export PARAM_RX_FIFO_DEPTH := 65536 export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 32768 diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py index 59d5b652c..33c359581 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -832,7 +832,7 @@ def test_fpga_core(request): parameters['LFC_ENABLE'] = 1 parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 65536 parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_RX_SIZE'] = 9214 parameters['TX_RAM_SIZE'] = 32768 diff --git a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile index df6bc383e..4f457fd4f 100644 --- a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile @@ -172,7 +172,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_LFC_ENABLE := 1 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 +export PARAM_RX_FIFO_DEPTH := 65536 export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 32768 diff --git a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py index 748256926..8d2c1f20b 100644 --- a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -740,7 +740,7 @@ def test_fpga_core(request): parameters['LFC_ENABLE'] = 1 parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 65536 parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_RX_SIZE'] = 9214 parameters['TX_RAM_SIZE'] = 32768 diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl index ffda59bfd..2537151ce 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl @@ -120,7 +120,7 @@ dict set params ENABLE_PADDING "1" dict set params ENABLE_DIC "1" dict set params MIN_FRAME_LENGTH "64" dict set params TX_FIFO_DEPTH "32768" -dict set params RX_FIFO_DEPTH "32768" +dict set params RX_FIFO_DEPTH "65536" dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile index d19191656..a6a7127dd 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile @@ -175,7 +175,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_LFC_ENABLE := 1 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 +export PARAM_RX_FIFO_DEPTH := 65536 export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 32768 diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py index 1b82b2a8a..e4b6d9cc1 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -835,7 +835,7 @@ def test_fpga_core(request): parameters['LFC_ENABLE'] = 1 parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 65536 parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_RX_SIZE'] = 9214 parameters['TX_RAM_SIZE'] = 32768 diff --git a/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.py index ed227a0df..9e48c64d9 100644 --- a/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -832,7 +832,7 @@ def test_fpga_core(request, qsfp_cnt, if_cnt, ports_per_if, sched_per_if): parameters['LFC_ENABLE'] = 1 parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 65536 parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_RX_SIZE'] = 9214 parameters['TX_RAM_SIZE'] = 32768 diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g/config.tcl index ea43421dc..f03961fd6 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g/config.tcl @@ -111,7 +111,7 @@ dict set params RX_FIFO_DEPTH "65536" dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" -dict set params RX_RAM_SIZE "32768" +dict set params RX_RAM_SIZE "131072" # Application block configuration dict set params APP_ID "32'h00000000" diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g_24AR0/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g_24AR0/config.tcl index 85b388257..4387c53ca 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g_24AR0/config.tcl +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g_24AR0/config.tcl @@ -111,7 +111,7 @@ dict set params RX_FIFO_DEPTH "65536" dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" -dict set params RX_RAM_SIZE "32768" +dict set params RX_RAM_SIZE "131072" # Application block configuration dict set params APP_ID "32'h00000000" diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/config.tcl b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/config.tcl index 8711c17e5..21aafea6c 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/config.tcl +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/config.tcl @@ -114,7 +114,7 @@ dict set params RX_FIFO_DEPTH "65536" dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" -dict set params RX_RAM_SIZE "32768" +dict set params RX_RAM_SIZE "131072" # Application block configuration dict set params APP_ID "32'h00000000" diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/config.tcl b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/config.tcl index 0ff3b4dc8..e1db35fb9 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/config.tcl +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/config.tcl @@ -114,7 +114,7 @@ dict set params RX_FIFO_DEPTH "65536" dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" -dict set params RX_RAM_SIZE "32768" +dict set params RX_RAM_SIZE "131072" # Application block configuration dict set params APP_ID "32'h00000000" diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile index f527ac2f3..00636d047 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile @@ -173,11 +173,11 @@ export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_LFC_ENABLE := 1 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 +export PARAM_RX_FIFO_DEPTH := 65536 export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 32768 -export PARAM_RX_RAM_SIZE := 32768 +export PARAM_RX_RAM_SIZE := 131072 # Application block configuration export PARAM_APP_ID := $(shell echo $$((0x00000000)) ) diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py index 86acc8609..e4abe5c8a 100644 --- a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -743,11 +743,11 @@ def test_fpga_core(request): parameters['LFC_ENABLE'] = 1 parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 65536 parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_RX_SIZE'] = 9214 parameters['TX_RAM_SIZE'] = 32768 - parameters['RX_RAM_SIZE'] = 32768 + parameters['RX_RAM_SIZE'] = 131072 # Application block configuration parameters['APP_ID'] = 0x00000000 diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g/config.tcl b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g/config.tcl index 147dd5e2d..04b91d3b8 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g/config.tcl +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g/config.tcl @@ -111,7 +111,7 @@ dict set params RX_FIFO_DEPTH "65536" dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" -dict set params RX_RAM_SIZE "32768" +dict set params RX_RAM_SIZE "131072" # Application block configuration dict set params APP_ID "32'h00000000" diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g_24AR0/config.tcl b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g_24AR0/config.tcl index 404c94137..5a5bc8ad0 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g_24AR0/config.tcl +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g_24AR0/config.tcl @@ -111,7 +111,7 @@ dict set params RX_FIFO_DEPTH "65536" dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" -dict set params RX_RAM_SIZE "32768" +dict set params RX_RAM_SIZE "131072" # Application block configuration dict set params APP_ID "32'h00000000" diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile index e458b275f..79a13fb53 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile @@ -174,7 +174,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_LFC_ENABLE := 1 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 +export PARAM_RX_FIFO_DEPTH := 65536 export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 32768 diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py index 666ec3ccf..c108b6be4 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py @@ -792,7 +792,7 @@ def test_fpga_core(request): parameters['LFC_ENABLE'] = 1 parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 65536 parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_RX_SIZE'] = 9214 parameters['TX_RAM_SIZE'] = 32768 diff --git a/fpga/mqnic/IA_420F/fpga_100g/fpga_25g/config.tcl b/fpga/mqnic/IA_420F/fpga_100g/fpga_25g/config.tcl index dba4a4569..e01c9698f 100644 --- a/fpga/mqnic/IA_420F/fpga_100g/fpga_25g/config.tcl +++ b/fpga/mqnic/IA_420F/fpga_100g/fpga_25g/config.tcl @@ -111,7 +111,7 @@ dict set params RX_FIFO_DEPTH "65536" dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" -dict set params RX_RAM_SIZE "32768" +dict set params RX_RAM_SIZE "131072" # Application block configuration dict set params APP_ID "32'h00000000" diff --git a/fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile b/fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile index 97db8d9af..31471e145 100644 --- a/fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile @@ -158,7 +158,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_LFC_ENABLE := 1 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 +export PARAM_RX_FIFO_DEPTH := 65536 export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 32768 diff --git a/fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py index a5e832536..5d553a09e 100644 --- a/fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py @@ -561,7 +561,7 @@ def test_fpga_core(request): parameters['LFC_ENABLE'] = 1 parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 65536 parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_RX_SIZE'] = 9214 parameters['TX_RAM_SIZE'] = 32768 diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl index ce407c146..415461518 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl +++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl @@ -111,7 +111,7 @@ dict set params RX_FIFO_DEPTH "65536" dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" -dict set params RX_RAM_SIZE "32768" +dict set params RX_RAM_SIZE "65536" # Application block configuration dict set params APP_ID "32'h00000000" diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/config.tcl b/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/config.tcl index 215db04b3..a884a34ba 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/config.tcl @@ -111,7 +111,7 @@ dict set params RX_FIFO_DEPTH "65536" dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" -dict set params RX_RAM_SIZE "32768" +dict set params RX_RAM_SIZE "65536" # Application block configuration dict set params APP_ID "32'h12348001" diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile index 19c4a371a..9e5e2f031 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile @@ -172,11 +172,11 @@ export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_LFC_ENABLE := 1 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 +export PARAM_RX_FIFO_DEPTH := 65536 export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 32768 -export PARAM_RX_RAM_SIZE := 32768 +export PARAM_RX_RAM_SIZE := 65536 # Application block configuration export PARAM_APP_ID := $(shell echo $$((0x00000000)) ) diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py index fb16eede1..79f3cd76e 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py @@ -782,11 +782,11 @@ def test_fpga_core(request): parameters['LFC_ENABLE'] = 1 parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 65536 parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_RX_SIZE'] = 9214 parameters['TX_RAM_SIZE'] = 32768 - parameters['RX_RAM_SIZE'] = 32768 + parameters['RX_RAM_SIZE'] = 65536 # Application block configuration parameters['APP_ID'] = 0x00000000 diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile index 2545fcdd4..9b791f038 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile @@ -174,7 +174,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_LFC_ENABLE := 1 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 +export PARAM_RX_FIFO_DEPTH := 65536 export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 32768 diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py index e20c2f411..d8551d282 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -832,7 +832,7 @@ def test_fpga_core(request): parameters['LFC_ENABLE'] = 1 parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 65536 parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_RX_SIZE'] = 9214 parameters['TX_RAM_SIZE'] = 32768 diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile index b52955887..debe3b490 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile @@ -175,7 +175,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_LFC_ENABLE := 1 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 +export PARAM_RX_FIFO_DEPTH := 65536 export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 32768 diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py index 79b9e0262..3fc30e8ca 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -825,7 +825,7 @@ def test_fpga_core(request): parameters['LFC_ENABLE'] = 1 parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 65536 parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_RX_SIZE'] = 9214 parameters['TX_RAM_SIZE'] = 32768 diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl index d8812c9c8..92198087f 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl @@ -124,7 +124,7 @@ dict set params RX_FIFO_DEPTH "65536" dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" -dict set params RX_RAM_SIZE "32768" +dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "2" diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile index 8518fb184..db641193e 100644 --- a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile @@ -174,11 +174,11 @@ export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_LFC_ENABLE := 1 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 +export PARAM_RX_FIFO_DEPTH := 65536 export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 32768 -export PARAM_RX_RAM_SIZE := 32768 +export PARAM_RX_RAM_SIZE := 131072 # Application block configuration export PARAM_APP_ID := $(shell echo $$((0x00000000)) ) diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py index 17f5aee35..719426b46 100644 --- a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -790,11 +790,11 @@ def test_fpga_core(request): parameters['LFC_ENABLE'] = 1 parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 65536 parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_RX_SIZE'] = 9214 parameters['TX_RAM_SIZE'] = 32768 - parameters['RX_RAM_SIZE'] = 32768 + parameters['RX_RAM_SIZE'] = 131072 # Application block configuration parameters['APP_ID'] = 0x00000000 diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile index e85ba3eff..8539490dd 100644 --- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile @@ -174,7 +174,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_LFC_ENABLE := 1 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 +export PARAM_RX_FIFO_DEPTH := 65536 export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 32768 diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py index 3d28ae297..59c35d110 100644 --- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -836,7 +836,7 @@ def test_fpga_core(request): parameters['LFC_ENABLE'] = 1 parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 65536 parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_RX_SIZE'] = 9214 parameters['TX_RAM_SIZE'] = 32768 diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S/config.tcl index eabe6fe31..cd00934fc 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S/config.tcl @@ -124,7 +124,7 @@ dict set params RX_FIFO_DEPTH "65536" dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" -dict set params RX_RAM_SIZE "32768" +dict set params RX_RAM_SIZE "131072" # RAM configuration dict set params DDR_CH "4" diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile index 3fcab9f61..d9fe00212 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile @@ -174,7 +174,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_LFC_ENABLE := 1 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 +export PARAM_RX_FIFO_DEPTH := 65536 export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 32768 diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py index 139d007d6..4a469fb56 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -833,7 +833,7 @@ def test_fpga_core(request): parameters['LFC_ENABLE'] = 1 parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 65536 parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_RX_SIZE'] = 9214 parameters['TX_RAM_SIZE'] = 32768 diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile index cd4e46bf1..b1decdd26 100644 --- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile @@ -158,7 +158,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_LFC_ENABLE := 1 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 +export PARAM_RX_FIFO_DEPTH := 65536 export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 32768 diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py index e1552380e..f02a2d18a 100644 --- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py @@ -582,7 +582,7 @@ def test_fpga_core(request): parameters['LFC_ENABLE'] = 1 parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 65536 parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_RX_SIZE'] = 9214 parameters['TX_RAM_SIZE'] = 32768 diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core_app_custom_port_demo/Makefile b/fpga/mqnic/ZCU102/fpga/tb/fpga_core_app_custom_port_demo/Makefile index a683e92d0..f69e3f485 100644 --- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core_app_custom_port_demo/Makefile +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core_app_custom_port_demo/Makefile @@ -160,7 +160,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_LFC_ENABLE := 1 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 +export PARAM_RX_FIFO_DEPTH := 65536 export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 32768 diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core_app_custom_port_demo/test_fpga_core.py b/fpga/mqnic/ZCU102/fpga/tb/fpga_core_app_custom_port_demo/test_fpga_core.py index 937fac8c9..ba3aa6894 100644 --- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core_app_custom_port_demo/test_fpga_core.py +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core_app_custom_port_demo/test_fpga_core.py @@ -588,7 +588,7 @@ def test_fpga_core(request): parameters['LFC_ENABLE'] = 1 parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 65536 parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_RX_SIZE'] = 9214 parameters['TX_RAM_SIZE'] = 32768 diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile index 36afd564d..c7e18f850 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile @@ -174,7 +174,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_LFC_ENABLE := 1 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 +export PARAM_RX_FIFO_DEPTH := 65536 export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 32768 diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py index 03efe7f1c..2f8a8b2bb 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py @@ -821,7 +821,7 @@ def test_fpga_core(request): parameters['LFC_ENABLE'] = 1 parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 65536 parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_RX_SIZE'] = 9214 parameters['TX_RAM_SIZE'] = 32768 diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile index cd4e46bf1..b1decdd26 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile @@ -158,7 +158,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_LFC_ENABLE := 1 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 +export PARAM_RX_FIFO_DEPTH := 65536 export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 32768 diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py index 2a5c155fc..b29ea5861 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py @@ -582,7 +582,7 @@ def test_fpga_core(request): parameters['LFC_ENABLE'] = 1 parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 65536 parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_RX_SIZE'] = 9214 parameters['TX_RAM_SIZE'] = 32768 diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile index cb8a317c5..5aac026df 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile @@ -175,7 +175,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_LFC_ENABLE := 1 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 +export PARAM_RX_FIFO_DEPTH := 65536 export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 32768 diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py index 806852436..5740f1f04 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -833,7 +833,7 @@ def test_fpga_core(request): parameters['LFC_ENABLE'] = 1 parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 65536 parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_RX_SIZE'] = 9214 parameters['TX_RAM_SIZE'] = 32768 diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile index 23bdde68f..715d08509 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/Makefile @@ -175,7 +175,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_LFC_ENABLE := 1 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE) export PARAM_TX_FIFO_DEPTH := 32768 -export PARAM_RX_FIFO_DEPTH := 32768 +export PARAM_RX_FIFO_DEPTH := 65536 export PARAM_MAX_TX_SIZE := 9214 export PARAM_MAX_RX_SIZE := 9214 export PARAM_TX_RAM_SIZE := 32768 diff --git a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py index 601a7cbce..0e6370a64 100644 --- a/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -830,7 +830,7 @@ def test_fpga_core(request): parameters['LFC_ENABLE'] = 1 parameters['PFC_ENABLE'] = parameters['LFC_ENABLE'] parameters['TX_FIFO_DEPTH'] = 32768 - parameters['RX_FIFO_DEPTH'] = 32768 + parameters['RX_FIFO_DEPTH'] = 65536 parameters['MAX_TX_SIZE'] = 9214 parameters['MAX_RX_SIZE'] = 9214 parameters['TX_RAM_SIZE'] = 32768