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Evaluate/support new ASAP7 6-track library #624

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harrisonliew opened this issue Oct 22, 2021 · 5 comments
Open

Evaluate/support new ASAP7 6-track library #624

harrisonliew opened this issue Oct 22, 2021 · 5 comments
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enhancement low priority Easy workaround exists, regular QoL issue

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@harrisonliew
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https://github.com/The-OpenROAD-Project/asap7/tree/master/asap7sc6t_26 added on Oct. 15, 2021
@harrisonliew harrisonliew added enhancement low priority Easy workaround exists, regular QoL issue labels Oct 22, 2021
@Waxpple
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Waxpple commented Aug 4, 2022

Have we evaluated the new asap7 version 28?

@harrisonliew
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No, we have not yet. PRs are welcome!

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Waxpple commented Aug 11, 2022

@harrisonliew
Done. Please review the PR #673 and let me know if it is not working.
I have tested it.

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Waxpple commented Aug 11, 2022 •
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There are some fixes in the newer version:

  1. ICG lib with "clock gating function and state table" has been fixed. Question related to M5, M6 spacing? The-OpenROAD-Project/asap7#3
    Edit: ICG*DC* cells with incorrect width has been fixed. DRC error regarding fin The-OpenROAD-Project/asap7#12
  2. Large ASNYC FF delay has been fixed. layout editor crashes upon opening any asap7_TechLib ivpcell crash The-OpenROAD-Project/asap7#9
  3. Multi-VT GDS files missing has been fixed.

One known issue

  1. Missing prefix in Verilog module name. Getting New LVS/DRC/PEX rule sets The-OpenROAD-Project/asap7#33

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Waxpple commented Aug 11, 2022

Also, I think somehow the timing library in version 27 caused the simulation to fail with a timeout. Still verifying this theory.

joennlae added a commit to joennlae/OpenROAD-flow-scripts that referenced this issue Sep 8, 2022
@joennlae
asap7: update to asap7 v28 + adding super low threshold option
9a3c144 
Fixes multiple issues: ucb-bar/hammer#624 (comment)

> ### There are some fixes in the newer version:
> 1. ICG lib with "clock gating function and state table" has been fixed. [ICG cells throw an error in library compiler The-OpenROAD-Project/asap7#3](The-OpenROAD-Project/asap7#3)
>    Edit: ICG*DC* cells with incorrect width has been fixed. [ICG*DC* cells have incorrect width The-OpenROAD-Project/asap7#12](The-OpenROAD-Project/asap7#12)
> 2. Large ASNYC FF delay has been fixed. [Wrong timing values (1e31) for ASYNC_DFFHx1_ASAP7_75t_R in the sc7p5t_SEQ_RVT_SS_nldm_201020 library The-OpenROAD-Project/asap7#9](The-OpenROAD-Project/asap7#9)
> 3. Multi-VT GDS files missing has been fixed.
>
> ### One known issue
> 1. Missing prefix in Verilog module name. ["AM" in the prefix of the module name "SRAM" is missing. The-OpenROAD-Project/asap7#33](The-OpenROAD-Project/asap7#33)

Signed-off-by: Jannis Schönleber <[email protected]>
joennlae added a commit to joennlae/OpenROAD-flow-scripts that referenced this issue Sep 12, 2022
@joennlae
asap7: update to asap7 v28 + adding super low threshold option
556beab 
Fixes multiple issues: ucb-bar/hammer#624 (comment)

> ### There are some fixes in the newer version:
> 1. ICG lib with "clock gating function and state table" has been fixed. [ICG cells throw an error in library compiler The-OpenROAD-Project/asap7#3](The-OpenROAD-Project/asap7#3)
>    Edit: ICG*DC* cells with incorrect width has been fixed. [ICG*DC* cells have incorrect width The-OpenROAD-Project/asap7#12](The-OpenROAD-Project/asap7#12)
> 2. Large ASNYC FF delay has been fixed. [Wrong timing values (1e31) for ASYNC_DFFHx1_ASAP7_75t_R in the sc7p5t_SEQ_RVT_SS_nldm_201020 library The-OpenROAD-Project/asap7#9](The-OpenROAD-Project/asap7#9)
> 3. Multi-VT GDS files missing has been fixed.
>
> ### One known issue
> 1. Missing prefix in Verilog module name. ["AM" in the prefix of the module name "SRAM" is missing. The-OpenROAD-Project/asap7#33](The-OpenROAD-Project/asap7#33)

Signed-off-by: Jannis Schönleber <[email protected]>
@harrisonliew harrisonliew mentioned this issue Mar 13, 2023
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