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Merge pull request #1928 from ucb-bar/vector-release
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Integrate vector unit
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jerryz123 authored Aug 6, 2024
2 parents 1f1b531 + 63e72b2 commit 5929221
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Showing 13 changed files with 263 additions and 4 deletions.
1 change: 1 addition & 0 deletions .github/actions/run-tests/action.yml
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Expand Up @@ -19,6 +19,7 @@ runs:
- name: Init submodules (since only the RTL is cached)
run: |
conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)
git submodule sync
./scripts/init-submodules-no-riscv-tools.sh
shell: bash -leo pipefail {0}

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2 changes: 1 addition & 1 deletion .github/scripts/check-commit.sh
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Expand Up @@ -46,7 +46,7 @@ search () {
}


submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc")
submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc" "saturn")
dir="generators"
branches=("master" "main" "dev")
search
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4 changes: 3 additions & 1 deletion .github/scripts/defaults.sh
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Expand Up @@ -27,7 +27,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
declare -A grouping
grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle"
grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboomv3 chipyard-dmiboomv4 chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet"
grouping["group-accels"]="chipyard-compressacc chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb chipyard-rerocc"
grouping["group-accels"]="chipyard-compressacc chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb chipyard-rerocc chipyard-rocketvector chipyard-shuttlevector"
grouping["group-constellation"]="chipyard-constellation"
grouping["group-tracegen"]="tracegen tracegen-boomv3 tracegen-boomv4"
grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar chipyard-clusters"
Expand Down Expand Up @@ -71,6 +71,8 @@ mapping["chipyard-constellation"]=" CONFIG=SharedNoCConfig"
mapping["chipyard-clusters"]=" CONFIG=ClusteredRocketConfig verilog"
mapping["chipyard-aes256ecb"]=" CONFIG=AES256ECBRocketConfig"
mapping["chipyard-rerocc"]=" CONFIG=ReRoCCTestConfig"
mapping["chipyard-rocketvector"]=" CONFIG=MINV128D64RocketConfig"
mapping["chipyard-shuttlevector"]=" CONFIG=GENV256D128ShuttleConfig"

mapping["constellation"]=" SUB_PROJECT=constellation"
mapping["firesim"]="TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig"
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1 change: 1 addition & 0 deletions .github/scripts/remote-do-rtl-build.sh
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Expand Up @@ -15,6 +15,7 @@ SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )"
source $SCRIPT_DIR/defaults.sh

cd $REMOTE_CHIPYARD_DIR
git submodule sync
./scripts/init-submodules-no-riscv-tools.sh

# Constellation can run without espresso, but this improves
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6 changes: 6 additions & 0 deletions .github/scripts/run-tests.sh
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Expand Up @@ -135,6 +135,12 @@ case $1 in
make -C $LOCAL_CHIPYARD_DIR/generators/rerocc/tests
run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/rerocc/tests/rerocc.riscv LOADMEM=1
;;
chipyard-rocketvector|chipyard-shuttlevector)
run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-sgemm.riscv LOADMEM=1
run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-strcmp.riscv LOADMEM=1
run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-daxpy.riscv LOADMEM=1
run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-memcpy.riscv LOADMEM=1
;;
tracegen)
run_tracegen
;;
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2 changes: 2 additions & 0 deletions .github/workflows/chipyard-full-flow.yml
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Expand Up @@ -18,6 +18,7 @@ env:
# temporary directories should be located in /scratch (since it's larger)
REMOTE_WORK_DIR: /scratch/buildbot/cy-ci-shared/cy-workdir-${{ github.sha }}
JAVA_TMP_DIR: /scratch/buildbot/cy-ci-shared/cy-javatmpdir-${{ github.sha }}
GIT_SSH_COMMAND: "ssh -v"

jobs:
cancel-prior-workflows:
Expand Down Expand Up @@ -84,6 +85,7 @@ jobs:
eval "$(conda shell.bash hook)"
mkdir ${{ env.JAVA_TMP_DIR }}
export MAKEFLAGS="-j32"
git submodule sync
./build-setup.sh -v
- name: Run config finder
run: |
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48 changes: 48 additions & 0 deletions .github/workflows/chipyard-run-tests.yml
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Expand Up @@ -798,6 +798,52 @@ jobs:
group-key: "group-accels"
project-key: "chipyard-rerocc"

chipyard-rocketvector-run-tests:
name: chipyard-rocketvector-run-tests
needs: prepare-chipyard-accels
runs-on: as4
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-accels"
project-key: "chipyard-rocketvector"

chipyard-shuttlevector-run-tests:
name: chipyard-shuttlevector-run-tests
needs: prepare-chipyard-accels
runs-on: as4
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-accels"
project-key: "chipyard-shuttlevector"

chipyard-gemmini-run-tests:
name: chipyard-gemmini-run-tests
needs: prepare-chipyard-accels
Expand Down Expand Up @@ -1188,6 +1234,8 @@ jobs:
chipyard-symmetric-run-tests,
chipyard-llcchiplet-run-tests,
chipyard-rerocc-run-tests,
chipyard-rocketvector-run-tests,
chipyard-shuttlevector-run-tests,
chipyard-gemmini-run-tests,
chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests,
chipyard-prefetchers-run-tests,
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5 changes: 4 additions & 1 deletion .gitmodules
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Expand Up @@ -147,4 +147,7 @@
url = https://github.com/ucb-bar/rerocc.git
[submodule "generators/compress-acc"]
path = generators/compress-acc
url = https://github.com/ucb-bar/compress-acc.git
url = https://github.com/ucb-bar/compress-acc.git
[submodule "generators/saturn"]
path = generators/saturn
url = https://github.com/ucb-bar/saturn-vectors.git
7 changes: 6 additions & 1 deletion build.sbt
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Expand Up @@ -176,7 +176,7 @@ lazy val chipyard = (project in file("generators/chipyard"))
dsptools, rocket_dsp_utils,
gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
constellation, mempress, barf, shuttle, caliptra_aes, rerocc,
compressacc)
compressacc, saturn)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(
libraryDependencies ++= Seq(
Expand All @@ -201,6 +201,11 @@ lazy val barf = (project in file("generators/bar-fetchers"))
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)

lazy val saturn = (project in file("generators/saturn"))
.dependsOn(rocketchip, shuttle)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)

lazy val constellation = (project in file("generators/constellation"))
.dependsOn(rocketchip)
.settings(libraryDependencies ++= rocketLibDeps.value)
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18 changes: 18 additions & 0 deletions docs/Generators/Saturn.rst
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@@ -0,0 +1,18 @@
Saturn
========

Saturn is a parameterized RISC-V Vector Unit generator currently supporting integration with the Rocket and Shuttle cores.
Saturn implements a compact short-vector-length vector microarchitecture suitable for deployment in a DSP-optimized core or area-efficient general-purpose core.

More documentation on Saturn will be released in the future.

* Full support for `V` application-profile RVV 1.0
* Precise traps with virtual memory
* Indexed/strided/segmented loads and stores
* Mask operations
* Register-gather + reductions
* `Zvfh` support for vector half-precision floating-point (FP16)
* `Zve64d` support for vector FP32 and FP64
* Configurable vector length, from `Zvl64b` up (tested to `Zvl4096b`)
* Configurable datapath width, from 64b up (tested to 512b)

1 change: 1 addition & 0 deletions docs/Generators/index.rst
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Expand Up @@ -23,6 +23,7 @@ so changes to the generators themselves will automatically be used when building
BOOM
Constellation
Gemmini
Saturn
IceNet
TestChipIP
Rocket-Chip-Generators
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171 changes: 171 additions & 0 deletions generators/chipyard/src/main/scala/config/SaturnConfigs.scala
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@@ -0,0 +1,171 @@
package chipyard

import org.chipsalliance.cde.config.{Config}
import saturn.common.{VectorParams}

// Rocket-integrated configs
class MINV64D64RocketConfig extends Config(
new saturn.rocket.WithRocketVectorUnit(64, 64, VectorParams.minParams) ++
new freechips.rocketchip.rocket.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

class MINV128D64RocketConfig extends Config(
new saturn.rocket.WithRocketVectorUnit(128, 64, VectorParams.minParams) ++
new freechips.rocketchip.rocket.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

class MINV256D64RocketConfig extends Config(
new saturn.rocket.WithRocketVectorUnit(256, 64, VectorParams.minParams) ++
new freechips.rocketchip.rocket.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

class REFV128D128RocketConfig extends Config(
new saturn.rocket.WithRocketVectorUnit(128, 128, VectorParams.refParams) ++
new chipyard.config.WithSystemBusWidth(128) ++
new freechips.rocketchip.rocket.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

class REFV256D64RocketConfig extends Config(
new saturn.rocket.WithRocketVectorUnit(256, 64, VectorParams.refParams) ++
new freechips.rocketchip.rocket.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

class REFV256D128RocketConfig extends Config(
new saturn.rocket.WithRocketVectorUnit(256, 128, VectorParams.refParams) ++
new chipyard.config.WithSystemBusWidth(128) ++
new freechips.rocketchip.rocket.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

class REFV512D128RocketConfig extends Config(
new saturn.rocket.WithRocketVectorUnit(512, 128, VectorParams.refParams) ++
new chipyard.config.WithSystemBusWidth(128) ++
new freechips.rocketchip.rocket.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

class REFV512D256RocketConfig extends Config(
new saturn.rocket.WithRocketVectorUnit(512, 256, VectorParams.refParams) ++
new chipyard.config.WithSystemBusWidth(256) ++
new freechips.rocketchip.rocket.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

class DMAV256D256RocketConfig extends Config(
new saturn.rocket.WithRocketVectorUnit(256, 256, VectorParams.dmaParams) ++
new chipyard.config.WithSystemBusWidth(256) ++
new freechips.rocketchip.rocket.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

// Shuttle-integrated configs
class GENV128D128ShuttleConfig extends Config(
new saturn.shuttle.WithShuttleVectorUnit(128, 128, VectorParams.genParams) ++
new chipyard.config.WithSystemBusWidth(128) ++
new shuttle.common.WithShuttleTileBeatBytes(16) ++
new shuttle.common.WithNShuttleCores(1) ++
new chipyard.config.AbstractConfig)

class REFV256D64ShuttleConfig extends Config(
new saturn.shuttle.WithShuttleVectorUnit(256, 64, VectorParams.refParams) ++
new shuttle.common.WithShuttleTileBeatBytes(16) ++
new shuttle.common.WithNShuttleCores(1) ++
new chipyard.config.AbstractConfig)

class REFV256D128ShuttleConfig extends Config(
new saturn.shuttle.WithShuttleVectorUnit(256, 128, VectorParams.refParams) ++
new chipyard.config.WithSystemBusWidth(128) ++
new shuttle.common.WithShuttleTileBeatBytes(16) ++
new shuttle.common.WithNShuttleCores(1) ++
new chipyard.config.AbstractConfig)

class DSPV256D128ShuttleConfig extends Config(
new saturn.shuttle.WithShuttleVectorUnit(256, 128, VectorParams.dspParams) ++
new chipyard.config.WithSystemBusWidth(128) ++
new shuttle.common.WithSGTCM(address=0x78000000, size=(8L << 10), banks=16) ++
new shuttle.common.WithTCM ++
new shuttle.common.WithShuttleTileBeatBytes(16) ++
new shuttle.common.WithNShuttleCores(1) ++
new chipyard.config.AbstractConfig)

class GENV256D128ShuttleConfig extends Config(
new saturn.shuttle.WithShuttleVectorUnit(256, 128, VectorParams.genParams) ++
new chipyard.config.WithSystemBusWidth(128) ++
new shuttle.common.WithShuttleTileBeatBytes(16) ++
new shuttle.common.WithNShuttleCores(1) ++
new chipyard.config.AbstractConfig)

class REFV512D128ShuttleConfig extends Config(
new saturn.shuttle.WithShuttleVectorUnit(512, 128, VectorParams.refParams) ++
new chipyard.config.WithSystemBusWidth(128) ++
new shuttle.common.WithShuttleTileBeatBytes(16) ++
new shuttle.common.WithNShuttleCores(1) ++
new chipyard.config.AbstractConfig)

class DSPV512D128ShuttleConfig extends Config(
new saturn.shuttle.WithShuttleVectorUnit(512, 128, VectorParams.dspParams) ++
new chipyard.config.WithSystemBusWidth(128) ++
new shuttle.common.WithShuttleTileBeatBytes(16) ++
new shuttle.common.WithNShuttleCores(1) ++
new chipyard.config.AbstractConfig)

class GENV512D128ShuttleConfig extends Config(
new saturn.shuttle.WithShuttleVectorUnit(512, 128, VectorParams.genParams) ++
new chipyard.config.WithSystemBusWidth(128) ++
new shuttle.common.WithShuttleTileBeatBytes(16) ++
new shuttle.common.WithNShuttleCores(1) ++
new chipyard.config.AbstractConfig)

class GENV512D256ShuttleConfig extends Config(
new saturn.shuttle.WithShuttleVectorUnit(512, 256, VectorParams.genParams) ++
new chipyard.config.WithSystemBusWidth(256) ++
new shuttle.common.WithShuttleTileBeatBytes(32) ++
new shuttle.common.WithNShuttleCores(1) ++
new chipyard.config.AbstractConfig)

class GENV1024D128ShuttleConfig extends Config(
new saturn.shuttle.WithShuttleVectorUnit(1024, 128, VectorParams.genParams) ++
new chipyard.config.WithSystemBusWidth(128) ++
new shuttle.common.WithShuttleTileBeatBytes(16) ++
new shuttle.common.WithNShuttleCores(1) ++
new chipyard.config.AbstractConfig)

class REFV256D256ShuttleConfig extends Config(
new saturn.shuttle.WithShuttleVectorUnit(256, 256, VectorParams.refParams) ++
new chipyard.config.WithSystemBusWidth(256) ++
new shuttle.common.WithShuttleTileBeatBytes(32) ++
new shuttle.common.WithNShuttleCores(1) ++
new chipyard.config.AbstractConfig)

class REFV512D256ShuttleConfig extends Config(
new saturn.shuttle.WithShuttleVectorUnit(512, 256, VectorParams.refParams) ++
new chipyard.config.WithSystemBusWidth(256) ++
new shuttle.common.WithShuttleTileBeatBytes(32) ++
new shuttle.common.WithNShuttleCores(1) ++
new chipyard.config.AbstractConfig)

class REFV512D512ShuttleConfig extends Config(
new saturn.shuttle.WithShuttleVectorUnit(512, 512, VectorParams.refParams) ++
new chipyard.config.WithSystemBusWidth(256) ++
new shuttle.common.WithShuttleTileBeatBytes(64) ++
new shuttle.common.WithNShuttleCores(1) ++
new chipyard.config.AbstractConfig)


// Cosim configs

class MINV128D64RocketCosimConfig extends Config(
new chipyard.harness.WithCospike ++
new chipyard.config.WithTraceIO ++
new saturn.rocket.WithRocketVectorUnit(128, 64, VectorParams.minParams) ++
new freechips.rocketchip.rocket.WithCease(false) ++
new freechips.rocketchip.rocket.WithDebugROB ++
new freechips.rocketchip.rocket.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

class GENV256D128ShuttleCosimConfig extends Config(
new chipyard.harness.WithCospike ++
new chipyard.config.WithTraceIO ++
new saturn.shuttle.WithShuttleVectorUnit(256, 128, VectorParams.genParams) ++
new chipyard.config.WithSystemBusWidth(128) ++
new shuttle.common.WithShuttleDebugROB ++
new shuttle.common.WithShuttleTileBeatBytes(16) ++
new shuttle.common.WithNShuttleCores(1) ++
new chipyard.config.AbstractConfig)

1 change: 1 addition & 0 deletions generators/saturn
Submodule saturn added at cca787

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