Enable vector unit without misa.V #430
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nick-knight
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e-puerto,
paul-walmsley-sifive and
sifive-eblot
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aswaterman
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Nov 8, 2021
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Hi @nick-knight , I just noticed that this pull request should be filed against the freedom-e-sdk-private project instead. Could you move it there? Can discuss further on Slack to describe what changed here. Thanks :-) |
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This PR attempts to resolve #429 by the techniques described therein:
__riscv_vectormacro;My implementation does introduce a subtle change in the semantics. Previously, if I'm understanding it correctly, this code implemented the following state transition of mstatus.VS (when misa.V was set):
Now, this code unconditionally sets mstatus.VS to Dirty.
I'm not sure I understand the previous Freedom-Metal behavior (nor the similar behavior of mstatus.FS). I feel like it would be most sensible to set these bits to Initial. Perhaps the assumption is that these bits are guaranteed to be Off at this point in execution, so they will always transition to Initial? I welcome the Freedom Metal developers to clarify their intention, and take over this PR.