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fix: Print MTI value upon hart update for machine timer interrupt visibility #620
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fix: Print MTI value upon hart update for machine timer interrupt visibility #620
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This doesn't seem to change functionality... But there's no way we're going to guarantee that this message output is stable.
Tests shouldn't be parsing log output. However since we haven't got a proper solution yet and this is a pretty small change it's probably ok for now. Just don't expect it to stay like this.
@@ -209,9 +209,14 @@ function clint_dispatch() -> unit = { | |||
then print_platform("clint::tick mtime <- " ^ BitStr(mtime)); | |||
mip[MTI] = 0b0; | |||
if mtimecmp <=_u mtime then { | |||
mip[MTI] = 0b1; |
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Can delete this line.
model/riscv_platform.sail
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mip[MTI] = 0b1 | ||
then print_platform(" clint timer pending at mtime " ^ BitStr(mtime) ^ " (mip.MTI <- " ^ BitStr(mip[MTI]) ^ ")"); | ||
} | ||
else if mtimecmp >_u mtime then { |
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Can just be else
no?
model/riscv_platform.sail
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else if mtimecmp >_u mtime then { | ||
mip[MTI] = 0b0; | ||
if get_config_print_platform() | ||
then print_platform(" clint timer pending at mtime " ^ BitStr(mtime) ^ " (mip.MTI <- " ^ BitStr(mip[MTI]) ^ ")"); |
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Message is wrong
model/riscv_platform.sail
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then print_platform(" clint timer pending at mtime " ^ BitStr(mtime) ^ " (mip.MTI <- " ^ BitStr(mip[MTI]) ^ ")"); | ||
} | ||
else if mtimecmp >_u mtime then { | ||
mip[MTI] = 0b0; |
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This is redundant due to the assignment above. Either change this to an else
and delete the assignment above or drop this assignment.
Let me see if I've got this straight. hart state gets updated at every
cycle (even a noop updates the PC.
so, does this message get printed every cycle? The count rate is then a
constant 1/cycle, and track mcycle. That's legal.
But I'm not sure how you can easily write a test where the reference model
(e.g. Sail) updates at a different rate than the DUT
- which is inevitably true since the rate is implementation dependent.
We could pass a cycle divider number into sail, so it only counts on every
n-th cycle, but that still isn't perfect.
Test don't parse the log output, as such - but tools (e.g. ISAC) rely on it.
…On Fri, Nov 22, 2024 at 12:46 PM Alexander Richardson < ***@***.***> wrote:
***@***.**** commented on this pull request.
------------------------------
In model/riscv_platform.sail
<#620 (comment)>:
> if get_config_print_platform()
- then print_platform(" clint timer pending at mtime " ^ BitStr(mtime));
- mip[MTI] = 0b1
+ then print_platform(" clint timer pending at mtime " ^ BitStr(mtime) ^ " (mip.MTI <- " ^ BitStr(mip[MTI]) ^ ")");
+ }
+ else if mtimecmp >_u mtime then {
+ mip[MTI] = 0b0;
This is redundant due to the assignment above. Either change this to an
else and delete the assignment above or drop this assignment.
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|
Thank you all for your detailed reviews and concerns. I've found a simpler solution that addresses the concerns:
This simpler version:
I've verified this gives me the coverage I need while making the code cleaner. Would this be a better approach? |
That appears to be very similar to the existing code no? I think that's fine, but why do you need to change it at all? Also you can hardcode "mip.MTI <- 1" in the message. |
But, IMO the value of mip.MTI needs to be updated using I think the reason for updating the log message for mip.MTI value is to have a similar output format as of the mip.MSI here
To explain it a bit, whenever we have a software interrupt pending (by writing a value on the base address of MSIP), we see the following message in the log:
But, for the case of timer interrupt pending which we can only be brought by making the mtime>= mtimecmp, we just simply see the following code, while on the back end (by the hart) the value of mip.MTI is updated to 1 which is not visible to the user:
Therefore, updating the log message will change it to the following and will make the updated mip.MTI visible to the user as in the case of software interrupt:
|
Additionally, as soon as we write something on the memory mapped address MSIP, we see the reflected value updated in the mip.MSi in the log something like:
Since, the value of mip.MTI depends on the mtime/mtimecmp update and IMO mip.MTI should also be visible on every mtime update by using the logic something similar to:
But, that's just a suggestion. |
So as I understand it you just want to change the logging. How about this?
Much simpler. |
Hi!
I have developed the ACTs (Architectural Compliance Tests) and coverage points for RISC-V compliance verification. As part of the coverage points, I needed support for printing the MTI (Machine Timer Interrupt) value upon a hart update to improve the visibility and tracking of machine interrupts during the test execution.
To achieve this, I made a small change to one of the print functions, ensuring that the MTI value is printed whenever the hart state is updated. This change is essential for accurate compliance verification and enhances the observability of machine interrupts.
Please review and consider adding this change to the original repository for inclusion in the RISC-V architecture test suite.