Make calculate new vl configurable

[rez5427]

I don't know whether sail-riscv needs this.
The spike uses VLMAX to calculate new vl, and sail-riscv uses (AVL + 1) / 2.

The spec says:

The number of bits implemented in vl depends on the implementation’s maximum vector
length of the smallest supported type. The smallest vector implementation with VLEN=32
and supporting SEW=8 would need at least six bits in vl to hold the values 0-32
(VLEN=32, with LMUL=8 and SEW=8, yields VLMAX=32).

[github-actions]

Test Results

396 tests  ±0   396 ✅ ±0   0s ⏱️ ±0s
  4 suites ±0     0 💤 ±0 
  1 files   ±0     0 ❌ ±0 

Results for commit 21f2417. ± Comparison against base commit 07fa23e.

♻️ This comment has been updated with latest results.

[Timmmm]

LGTM but I would add some explanation and move the if to the place where it is actually used. Also move the to_bits outside the body to make it clearer.

val sys_vext_vl_use_ceil = pure "sys_vext_vl_use_ceil" : unit -> bool

function calculate_new_vl(AVL : int, VLMAX : int) -> xlenbits = {
  // See "Constraints on Setting vl" in the vector spec.
  let vl =
    if AVL <= VLMAX then AVL
    else if AVL < 2 * VLMAX then {
      // If VLMAX < AVL < 2 * VLMAX then we can use any value
      // such that ceil(AVL / 2) <= vl <= VLMAX. Here we provide
      // two options: ceil(AVL / 2) or VLMAX.
      if sys_vext_vl_use_ceil() then (AVL + 1) / 2 else VLMAX
    }
    else VLMAX;

  to_bits(xlen, vl)
}

(Feel free to copy/paste.)

[Timmmm]

LGTM! I'm not a vector expert though so we might want to get the opinion of someone who is (although the spec seems pretty unambiguous on this point). I can ask a colleague if nobody is forthcoming.

[avakar]

@Timmmm's colleague here. LGTM.

[jrtc27]

The commit message doesn't mention that you're changing the default behaviour

[rez5427]

Sorry..., Is this commit message ok?

[Timmmm]

I'm not sure which commit message you changed... but don't worry I will squash it and write a descriptive message.