From 13edff8133fb669aeb3278afdb274672eec8d3d5 Mon Sep 17 00:00:00 2001 From: Daniel Bone Date: Thu, 8 Feb 2024 13:55:40 +0000 Subject: [PATCH 01/14] Add L1 Instruction Cache --- core/CMakeLists.txt | 1 + core/ICache.cpp | 241 ++++++++++++++++++ core/ICache.hpp | 144 +++++++++++ core/MemoryAccessInfo.hpp | 34 ++- test/CMakeLists.txt | 1 + test/core/icache/CMakeLists.txt | 8 + test/core/icache/ICacheChecker.hpp | 192 ++++++++++++++ test/core/icache/ICacheSink.hpp | 155 +++++++++++ test/core/icache/ICacheSource.hpp | 121 +++++++++ test/core/icache/ICache_test.cpp | 185 ++++++++++++++ .../expected_output/hit_case.out.EXPECTED | 28 +- .../single_access.out.EXPECTED | 20 +- 12 files changed, 1101 insertions(+), 29 deletions(-) create mode 100644 core/ICache.cpp create mode 100644 core/ICache.hpp create mode 100644 test/core/icache/CMakeLists.txt create mode 100644 test/core/icache/ICacheChecker.hpp create mode 100644 test/core/icache/ICacheSink.hpp create mode 100644 test/core/icache/ICacheSource.hpp create mode 100644 test/core/icache/ICache_test.cpp diff --git a/core/CMakeLists.txt b/core/CMakeLists.txt index 40eebfa1..fdf462b1 100644 --- a/core/CMakeLists.txt +++ b/core/CMakeLists.txt @@ -1,6 +1,7 @@ project (core) add_library(core Core.cpp + ICache.cpp Fetch.cpp Decode.cpp Rename.cpp diff --git a/core/ICache.cpp b/core/ICache.cpp new file mode 100644 index 00000000..05ef2349 --- /dev/null +++ b/core/ICache.cpp @@ -0,0 +1,241 @@ +// -*- C++ -*- + +//! +//! \file ICache.cpp +//! \brief Implementation of the CoreModel ICache unit +//! + + +#include "ICache.hpp" + +#include "OlympiaAllocators.hpp" + + +namespace olympia { + const char ICache::name[] = "instruction_cache"; + + ICache::ICache(sparta::TreeNode *node, const ICacheParameterSet *p) : + sparta::Unit(node), + l1_always_hit_(p->l1_always_hit), + cache_latency_(p->cache_latency), + pending_miss_buffer_("pending_miss_buffer", fetch_queue_size_, getClock()), + memory_access_allocator_( + sparta::notNull(olympia::OlympiaAllocators::getOlympiaAllocators(node))-> + memory_access_allocator) + { + + in_fetch_req_.registerConsumerHandler + (CREATE_SPARTA_HANDLER_WITH_DATA(ICache, getRequestFromFetch_, MemoryAccessInfoPtr)); + + in_l2cache_ack_.registerConsumerHandler + (CREATE_SPARTA_HANDLER_WITH_DATA(ICache, getAckFromL2Cache_, uint32_t)); + + in_l2cache_resp_.registerConsumerHandler + (CREATE_SPARTA_HANDLER_WITH_DATA(ICache, getRespFromL2Cache_, MemoryAccessInfoPtr)); + + // IL1 cache config + const uint32_t l1_line_size = p->l1_line_size; + const uint32_t l1_size_kb = p->l1_size_kb; + const uint32_t l1_associativity = p->l1_associativity; + std::unique_ptr repl(new sparta::cache::TreePLRUReplacement + (l1_associativity)); + l1_cache_.reset(new CacheFuncModel(getContainer(), l1_size_kb, l1_line_size, *repl)); + sparta::StartupEvent(node, CREATE_SPARTA_HANDLER(ICache, sendInitialCredits_)); + + + } + + void ICache::sendInitialCredits_() + { + out_fetch_credit_.send(fetch_queue_size_); + } + + // Access ICache + bool ICache::lookupCache_(const MemoryAccessInfoPtr & mem_access_info_ptr) + { + uint64_t phyAddr = mem_access_info_ptr->getPhyAddr(); + + bool cache_hit = false; + + if (l1_always_hit_) { + cache_hit = true; + } + else { + auto cache_line = l1_cache_->peekLine(phyAddr); + cache_hit = (cache_line != nullptr) && cache_line->isValid(); + + // Update MRU replacement state if ICache HIT + if (cache_hit) { + l1_cache_->touchMRU(*cache_line); + } + } + + if (l1_always_hit_) { + ILOG("IL1 Cache HIT all the time: phyAddr=0x" << std::hex << phyAddr); + il1_cache_hits_++; + } + else if (cache_hit) { + ILOG("IL1 Cache HIT: phyAddr=0x" << std::hex << phyAddr); + il1_cache_hits_++; + } + else { + ILOG("IL1 Cache MISS: phyAddr=0x" << std::hex << phyAddr); + il1_cache_misses_++; + } + + return cache_hit; + } + + void ICache::reloadCache_(const MemoryAccessInfoPtr & mem_access_info_ptr) + { + + auto const decoder = l1_cache_->getAddrDecoder(); + auto const reload_addr = mem_access_info_ptr->getPhyAddr(); + auto const reload_block = decoder->calcBlockAddr(reload_addr); + + auto l1_cache_line = &l1_cache_->getLineForReplacementWithInvalidCheck(reload_addr); + l1_cache_->allocateWithMRUUpdate(*l1_cache_line, reload_addr); + + // Move pending misses into the replay queue + DLOG("finding misses to replay"); + auto iter = pending_miss_buffer_.begin(); + while (iter != pending_miss_buffer_.end()) { + auto delete_iter = iter++; + + if (decoder->calcBlockAddr((*delete_iter)->getPhyAddr()) == reload_block) { + DLOG("scheduling for replay " << *delete_iter); + replay_buffer_.emplace_back(*delete_iter); + pending_miss_buffer_.erase(delete_iter); + } + } + + // Schedule next cycle + DLOG("reload completed"); + ev_arbitrate_.schedule(1); + } + + void ICache::doArbitration_() + { + if (!l2cache_resp_queue_.empty()) { + // Do a linefill + auto const mem_access_info_ptr = l2cache_resp_queue_.front(); + ILOG("doing reload " << mem_access_info_ptr); + reloadCache_(mem_access_info_ptr); + l2cache_resp_queue_.pop_front(); + } + + // Priotize replays over fetches, replays can run in parallel with a fill. + // NOTE: Ideally we'd want to prioritize demand fetches over lingering misses + // from a speculative search + if (!replay_buffer_.empty()) { + // Replay miss + auto const mem_access_info_ptr = replay_buffer_.front(); + ILOG("doing replay for fetch request " << mem_access_info_ptr); + ev_replay_ready_.preparePayload(mem_access_info_ptr) + ->schedule(sparta::Clock::Cycle(cache_latency_)); + replay_buffer_.pop_front(); + + } + else if (!fetch_req_queue_.empty()) { + // Do a read access + auto const mem_access_info_ptr = fetch_req_queue_.front(); + ILOG("doing lookup for fetch request " << mem_access_info_ptr); + if (lookupCache_(mem_access_info_ptr)) { + mem_access_info_ptr->setCacheState(MemoryAccessInfo::CacheState::HIT); + } + else { + mem_access_info_ptr->setCacheState(MemoryAccessInfo::CacheState::MISS); + addToMissQueue_(mem_access_info_ptr); + } + ev_respond_.preparePayload(mem_access_info_ptr) + ->schedule(sparta::Clock::Cycle(cache_latency_)); + fetch_req_queue_.pop_front(); + } + + if (!l2cache_resp_queue_.empty() || !replay_buffer_.empty() || !fetch_req_queue_.empty()) { + ev_arbitrate_.schedule(1); + } + } + + void ICache::addToMissQueue_(const MemoryAccessInfoPtr & mem_access_info_ptr) + { + // Don't make requests to cachelines that are already pending + auto const decoder = l1_cache_->getAddrDecoder(); + auto missed_block = decoder->calcBlockAddr(mem_access_info_ptr->getPhyAddr()); + auto same_line = [decoder, missed_block] (auto other) { + return decoder->calcBlockAddr(other->getPhyAddr()) == missed_block; + }; + auto it = std::find_if(pending_miss_buffer_.begin(), pending_miss_buffer_.end(), same_line); + if (it == pending_miss_buffer_.end()) { + DLOG("appending miss to l2 miss queue: " << mem_access_info_ptr); + miss_queue_.emplace_back(mem_access_info_ptr); + makeL2CacheRequest_(); + } + ILOG("miss request queued for replay: " << mem_access_info_ptr); + pending_miss_buffer_.push_back(mem_access_info_ptr); + } + + void ICache::getRequestFromFetch_(const MemoryAccessInfoPtr &mem_access_info_ptr) + { + ILOG("received fetch request " << mem_access_info_ptr); + fetch_req_queue_.emplace_back(mem_access_info_ptr); + ev_arbitrate_.schedule(sparta::Clock::Cycle(0)); + } + + void ICache::getRespFromL2Cache_(const MemoryAccessInfoPtr &mem_access_info_ptr) + { + ILOG("received fill response " << mem_access_info_ptr); + if (mem_access_info_ptr->getCacheState() == MemoryAccessInfo::CacheState::HIT) { + l2cache_resp_queue_.emplace_back(mem_access_info_ptr); + ev_arbitrate_.schedule(sparta::Clock::Cycle(0)); + } + } + + void ICache::getAckFromL2Cache_(const uint32_t &ack) + { + l2cache_credits_ += ack; + if (!miss_queue_.empty()) { + ev_l2cache_request_.schedule(sparta::Clock::Cycle(0)); + } + } + + // Respond misses + void ICache::sendReplay_(const MemoryAccessInfoPtr & mem_access_info_ptr) + { + // Delayed change to hit state until we're ready to send it back + mem_access_info_ptr->setCacheState(MemoryAccessInfo::CacheState::HIT); + out_fetch_resp_.send(mem_access_info_ptr); + out_fetch_credit_.send(1); + } + + void ICache::sendResponse_(const MemoryAccessInfoPtr & mem_access_info_ptr) + { + out_fetch_resp_.send(mem_access_info_ptr); + if (mem_access_info_ptr->getCacheState() == MemoryAccessInfo::CacheState::HIT) { + out_fetch_credit_.send(1); + } + } + + void ICache::makeL2CacheRequest_() + { + if (l2cache_credits_ == 0 || miss_queue_.empty()) { + return; + } + + // Create new MemoryAccessInfo to avoid propagating changes made by L2 back to the core + const auto &l2cache_req = sparta::allocate_sparta_shared_pointer( + memory_access_allocator_, *(miss_queue_.front())); + + // Forward miss to next cache level + ILOG("requesting linefill for " << l2cache_req); + out_l2cache_req_.send(l2cache_req); + --l2cache_credits_; + + miss_queue_.pop_front(); + + // Schedule another + if (l2cache_credits_ > 0 && !miss_queue_.empty()) { + ev_l2cache_request_.schedule(1); + } + } +} diff --git a/core/ICache.hpp b/core/ICache.hpp new file mode 100644 index 00000000..869edd86 --- /dev/null +++ b/core/ICache.hpp @@ -0,0 +1,144 @@ +// -*- C++ -*- + +//! +//! \file Fetch.hpp +//! \brief Definition of the CoreModel ICache unit +//! + +#pragma once + +#include "sparta/simulation/Unit.hpp" +#include "sparta/ports/DataPort.hpp" +#include "sparta/ports/SignalPort.hpp" +#include "sparta/simulation/ParameterSet.hpp" +#include "sparta/resources/Buffer.hpp" +#include "sparta/utils/LogUtils.hpp" + +#include "CacheFuncModel.hpp" +#include "Inst.hpp" +#include "cache/TreePLRUReplacement.hpp" +#include "MemoryAccessInfo.hpp" + +namespace olympia +{ + + /** + * @file ICache.hpp + * @brief The L1 Instruction Cache block -- L1 Cache unit for instruction code + * + * This is an L1 Instruction Cache that features: + * - Hit and miss under miss + * - Pipelining of requests + * - Automatic miss replay following a linefill + * Both interfaces use a credit protocol. + */ + class ICache : public sparta::Unit + { + public: + class ICacheParameterSet : public sparta::ParameterSet + { + public: + ICacheParameterSet(sparta::TreeNode* n) : sparta::ParameterSet(n) {} + + // Parameters for the IL1 cache + PARAMETER(uint32_t, l1_line_size, 64, "IL1 line size (power of 2)") + PARAMETER(uint32_t, l1_size_kb, 32, "Size of IL1 in KB (power of 2)") + PARAMETER(uint32_t, l1_associativity, 8, "IL1 associativity (power of 2)") + PARAMETER(uint32_t, cache_latency, 1, "Assumed latency of the memory system") + PARAMETER(bool, l1_always_hit, false, "IL1 will always hit") + }; + + static const char name[]; + ICache(sparta::TreeNode* n, const ICacheParameterSet* p); + + private: + + void doArbitration_(); + void sendReplay_(const MemoryAccessInfoPtr &); + void sendResponse_(const MemoryAccessInfoPtr &); + void addToMissQueue_(const MemoryAccessInfoPtr &); + void makeL2CacheRequest_(); + void reloadCache_(const MemoryAccessInfoPtr&); + bool lookupCache_(const MemoryAccessInfoPtr &); + + void sendInitialCredits_(); + + // Callbacks + void getRequestFromFetch_(const MemoryAccessInfoPtr &); + void getAckFromL2Cache_(const uint32_t &); + void getRespFromL2Cache_(const MemoryAccessInfoPtr &); + + using L1Handle = CacheFuncModel::Handle; + L1Handle l1_cache_; + const bool l1_always_hit_; + const uint32_t cache_latency_ = 0; + const uint32_t fetch_queue_size_ = 8; + + std::deque l2cache_resp_queue_; + std::deque fetch_req_queue_; + std::deque replay_buffer_; + std::deque miss_queue_; + + sparta::Buffer pending_miss_buffer_; + + // Credits for sending miss request to L2Cache + uint32_t l2cache_credits_ = 0; + + olympia::MemoryAccessInfoAllocator & memory_access_allocator_; + + //////////////////////////////////////////////////////////////////////////////// + // Input Ports + //////////////////////////////////////////////////////////////////////////////// + sparta::DataInPort in_fetch_req_{&unit_port_set_, + "in_fetch_req", 1}; + + sparta::DataInPort in_l2cache_ack_{&unit_port_set_, "in_l2cache_ack", 1}; + + sparta::DataInPort in_l2cache_resp_{&unit_port_set_, + "in_l2cache_resp", 1}; + + //////////////////////////////////////////////////////////////////////////////// + // Output Ports + //////////////////////////////////////////////////////////////////////////////// + + sparta::DataOutPort out_fetch_credit_{&unit_port_set_, + "out_fetch_credit", 0}; + + sparta::DataOutPort out_fetch_resp_{&unit_port_set_, + "out_fetch_resp", 0}; + + sparta::DataOutPort out_l2cache_req_{&unit_port_set_, + "out_l2cache_req", 0}; + + //////////////////////////////////////////////////////////////////////////////// + // Events + //////////////////////////////////////////////////////////////////////////////// + sparta::UniqueEvent<> ev_arbitrate_{&unit_event_set_, "ev_arbitrate", + CREATE_SPARTA_HANDLER(ICache, doArbitration_)}; + + sparta::UniqueEvent<> ev_l2cache_request_{&unit_event_set_, "ev_l2cache_request", + CREATE_SPARTA_HANDLER(ICache, makeL2CacheRequest_)}; + + + sparta::PayloadEvent ev_respond_{ + &unit_event_set_, "ev_respond", + CREATE_SPARTA_HANDLER_WITH_DATA(ICache, sendResponse_, MemoryAccessInfoPtr)}; + + sparta::PayloadEvent ev_replay_ready_{ + &unit_event_set_, "ev_replay_ready", + CREATE_SPARTA_HANDLER_WITH_DATA(ICache, sendReplay_, MemoryAccessInfoPtr)}; + + //////////////////////////////////////////////////////////////////////////////// + // Counters + //////////////////////////////////////////////////////////////////////////////// + sparta::Counter il1_cache_hits_{getStatisticSet(), "IL1_cache_hits", + "Number of IL1 cache hits", sparta::Counter::COUNT_NORMAL}; + + sparta::Counter il1_cache_misses_{getStatisticSet(), "IL1_cache_misses", + "Number of IL1 cache misses", + sparta::Counter::COUNT_NORMAL}; + + friend class ICacheTester; + }; + class ICacheTester; +} // namespace olympia diff --git a/core/MemoryAccessInfo.hpp b/core/MemoryAccessInfo.hpp index 50a04b31..01f7e262 100644 --- a/core/MemoryAccessInfo.hpp +++ b/core/MemoryAccessInfo.hpp @@ -67,6 +67,19 @@ namespace olympia MemoryAccessInfo(const MemoryAccessInfo &rhs) = default; + MemoryAccessInfo(const uint64_t addr) : + ldst_inst_ptr_(nullptr), + phy_addr_ready_(true), + mmu_access_state_(MMUState::NO_ACCESS), + cache_access_state_(CacheState::NO_ACCESS), + cache_data_ready_(false), + src_(ArchUnit::NO_ACCESS), + dest_(ArchUnit::NO_ACCESS), + vaddr_(addr), + paddr_(addr) + {} + + MemoryAccessInfo(const InstPtr & inst_ptr) : ldst_inst_ptr_(inst_ptr), phy_addr_ready_(false), @@ -76,7 +89,9 @@ namespace olympia cache_access_state_(CacheState::NO_ACCESS), cache_data_ready_(false), src_(ArchUnit::NO_ACCESS), - dest_(ArchUnit::NO_ACCESS) + dest_(ArchUnit::NO_ACCESS), + vaddr_(inst_ptr->getTargetVAddr()), + paddr_(inst_ptr->getRAdr()) { } @@ -104,9 +119,9 @@ namespace olympia bool getPhyAddrStatus() const { return phy_addr_ready_; } - uint64_t getPhyAddr() const { return ldst_inst_ptr_->getRAdr(); } + uint64_t getPhyAddr() const { return paddr_; } - sparta::memory::addr_t getVAddr() const { return ldst_inst_ptr_->getTargetVAddr(); } + sparta::memory::addr_t getVAddr() const { return vaddr_; } void setSrcUnit(const ArchUnit & src_unit) { src_ = src_unit; } @@ -153,7 +168,7 @@ namespace olympia private: // load/store instruction pointer - InstPtr ldst_inst_ptr_; + const InstPtr ldst_inst_ptr_; // Indicate MMU address translation status bool phy_addr_ready_; @@ -169,6 +184,12 @@ namespace olympia ArchUnit src_ = ArchUnit::NO_ACCESS; ArchUnit dest_ = ArchUnit::NO_ACCESS; + // Virtual Address + const uint64_t vaddr_; + + // Physical Address + const uint64_t paddr_; + // Pointer to next request for DEBUG/TRACK // (Note : Currently used only to track request with same cacheline in L2Cache // Not for functional/performance purpose) @@ -256,7 +277,10 @@ namespace olympia inline std::ostream & operator<<(std::ostream & os, const olympia::MemoryAccessInfo & mem) { - os << "memptr: " << mem.getInstPtr(); + os << "memptr: " << std::hex << mem.getPhyAddr() << std::dec; + if (mem.getInstPtr() != nullptr) { + os << " " << mem.getInstPtr(); + } return os; } diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt index 35bb2a8d..4eb15341 100644 --- a/test/CMakeLists.txt +++ b/test/CMakeLists.txt @@ -32,3 +32,4 @@ add_subdirectory(core/l2cache) add_subdirectory(core/rename) add_subdirectory(core/lsu) add_subdirectory(core/issue_queue) +add_subdirectory(core/icache) diff --git a/test/core/icache/CMakeLists.txt b/test/core/icache/CMakeLists.txt new file mode 100644 index 00000000..0e3acda2 --- /dev/null +++ b/test/core/icache/CMakeLists.txt @@ -0,0 +1,8 @@ +project(ICache_test) + +add_executable(ICache_test ICache_test.cpp) +target_link_libraries(ICache_test core common_test mss mavis SPARTA::sparta) + +sparta_named_test(ICache_test_single_access ICache_test --testname single_access --seed 1) +sparta_named_test(ICache_test_simple ICache_test --testname simple --seed 1) +sparta_named_test(ICache_test_random ICache_test --testname random --seed 1 -p top.sink.params.miss_rate 100) diff --git a/test/core/icache/ICacheChecker.hpp b/test/core/icache/ICacheChecker.hpp new file mode 100644 index 00000000..4019bbb8 --- /dev/null +++ b/test/core/icache/ICacheChecker.hpp @@ -0,0 +1,192 @@ +#pragma once + + +#include "core/MemoryAccessInfo.hpp" +#include "sparta/simulation/TreeNode.hpp" +#include "sparta/events/SingleCycleUniqueEvent.hpp" +#include "sparta/utils/SpartaSharedPointer.hpp" +#include "sparta/utils/LogUtils.hpp" +#include "ICache.hpp" + +#include +#include +#include + +// Basically just a way of getting to the address decoder so that the checker can +// calculate set index or block addresses +class olympia::ICacheTester +{ +public: + void setDUT(olympia::ICache *dut) { dut_ = dut; } + + uint64_t getSetIdx(uint64_t addr) + { + auto decoder = dut_->l1_cache_->getAddrDecoder(); + return decoder->calcIdx(addr); + } + + uint64_t getTag(uint64_t addr) + { + auto decoder = dut_->l1_cache_->getAddrDecoder(); + return decoder->calcTag(addr); + } + + uint64_t getBlockAddress(uint64_t addr) + { + auto decoder = dut_->l1_cache_->getAddrDecoder(); + return decoder->calcBlockAddr(addr); + } + + uint32_t getNumWays() + { + return dut_->l1_cache_->getNumWays(); + } + +private: + olympia::ICache * dut_ = nullptr; +}; + +namespace icache_test +{ + class ICacheChecker : public sparta::Unit, public olympia::ICacheTester + { + public: + static constexpr char name[] = "instruction cache checker"; + + using ICacheCheckerParameters = sparta::ParameterSet; + ICacheChecker(sparta::TreeNode * node, const ICacheCheckerParameters *p) : sparta::Unit(node) + { + + in_fetch_req_.registerConsumerHandler + (CREATE_SPARTA_HANDLER_WITH_DATA(ICacheChecker, getRequestFromFetch_, olympia::MemoryAccessInfoPtr)); + in_fetch_resp_.registerConsumerHandler + (CREATE_SPARTA_HANDLER_WITH_DATA(ICacheChecker, getResponseToFetch_, olympia::MemoryAccessInfoPtr)); + in_l2cache_req_.registerConsumerHandler + (CREATE_SPARTA_HANDLER_WITH_DATA(ICacheChecker, getRequestToL2Cache_, olympia::MemoryAccessInfoPtr)); + in_l2cache_resp_.registerConsumerHandler + (CREATE_SPARTA_HANDLER_WITH_DATA(ICacheChecker, getResponseFromL2Cache_, olympia::MemoryAccessInfoPtr)); + } + + uint32_t getICacheHitCount() const { return icache_hits_;} + uint32_t getICacheMissCount() const { return icache_misses_;} + uint32_t getL2CacheHitCount() const { return l2cache_hits_;} + uint32_t getL2CacheMissCount() const { return l2cache_misses_;} + + private: + + void getRequestFromFetch_(const olympia::MemoryAccessInfoPtr & mem_access_info_ptr) + { + fetch_pending_queue_.push_back(mem_access_info_ptr); + } + + void getResponseToFetch_(const olympia::MemoryAccessInfoPtr & mem_access_info_ptr) + { + // Should only be a HIT or MISS response + const auto cache_state = mem_access_info_ptr->getCacheState(); + if (cache_state != olympia::MemoryAccessInfo::CacheState::HIT) { + sparta_assert(cache_state == olympia::MemoryAccessInfo::CacheState::MISS); + } + + // Search for the original request + const auto fetch_req = std::find(fetch_pending_queue_.begin(), fetch_pending_queue_.end(), mem_access_info_ptr); + sparta_assert(fetch_req != fetch_pending_queue_.end(), "response received without a corresponding request"); + + auto tag = getTag(mem_access_info_ptr->getPhyAddr()); + auto set = getSetIdx(mem_access_info_ptr->getPhyAddr()); + + if (cache_state == olympia::MemoryAccessInfo::CacheState::HIT) { + auto block = getBlockAddress(mem_access_info_ptr->getPhyAddr()); + + // Check that we don't have an outstanding L2 request on this block + sparta_assert(pending_l2cache_reqs_.count(block) == 0); + + // Check that we've filled this block at least once.. + sparta_assert(filled_blocks_.count(block)); + + // Track the last tag to hit on this set + last_access_tracker_[set] = tag; + + ILOG("removing fetch request") + fetch_pending_queue_.erase(fetch_req); + + ++icache_hits_; + } + else { + // We cannot miss if we hit on this set last time with this tag + if (auto itr = last_access_tracker_.find(set); itr != last_access_tracker_.end()) { + sparta_assert(itr->second != tag); + } + + ++icache_misses_; + } + } + + void getRequestToL2Cache_(const olympia::MemoryAccessInfoPtr & mem_access_info_ptr) + { + + auto block = getBlockAddress(mem_access_info_ptr->getPhyAddr()); + auto matches_block = [this, block](auto req) { return block == getBlockAddress(req->getPhyAddr()); }; + + // Check that fetch has tried to request this address + const auto fetch_req = std::find_if(fetch_pending_queue_.begin(), fetch_pending_queue_.end(), matches_block); + sparta_assert(fetch_req != fetch_pending_queue_.end(), "response received without a corresponding request"); + + // Check that we don't have another l2cache request inflight for the same block + sparta_assert(pending_l2cache_reqs_.count(block) == 0); + pending_l2cache_reqs_.insert(block); + } + + void getResponseFromL2Cache_(const olympia::MemoryAccessInfoPtr & mem_access_info_ptr) + { + if (mem_access_info_ptr->getCacheState() == olympia::MemoryAccessInfo::CacheState::HIT) { + auto block = getBlockAddress(mem_access_info_ptr->getPhyAddr()); + + // Flag that we've filled this block atleast once + filled_blocks_.insert(block); + + // Shouldn't have received a response if we didn't request it? + sparta_assert(pending_l2cache_reqs_.erase(block)); + + ++l2cache_hits_; + } + else { + ++l2cache_misses_; + } + } + + void onStartingTeardown_() override final + { + sparta_assert(fetch_pending_queue_.empty()); + sparta_assert(pending_l2cache_reqs_.size() == 0); + } + + //////////////////////////////////////////////////////////////////////////////// + // Variables + //////////////////////////////////////////////////////////////////////////////// + + uint32_t icache_hits_ = 0; + uint32_t icache_misses_ = 0; + uint32_t l2cache_hits_ = 0; + uint32_t l2cache_misses_ = 0; + + // Track pending fetch requests + std::vector fetch_pending_queue_; + + // Track pending l2cache reqs - icache shouldn't request them again, and fetch cannot hit on them + std::set pending_l2cache_reqs_; + + // Track blocks which have been filled atleast once - fetch cannot hit on them until they're filled + std::set filled_blocks_; + + // Track the tags of the last hits on each set - fetch cannot miss on them + std::map last_access_tracker_; + + //////////////////////////////////////////////////////////////////////////////// + // Input Ports + //////////////////////////////////////////////////////////////////////////////// + sparta::DataInPort in_fetch_req_ {&unit_port_set_, "in_fetch_req", 1}; + sparta::DataInPort in_fetch_resp_ {&unit_port_set_, "in_fetch_resp", 1}; + sparta::DataInPort in_l2cache_req_ {&unit_port_set_, "in_l2cache_req", 1}; + sparta::DataInPort in_l2cache_resp_ {&unit_port_set_, "in_l2cache_resp", 1}; + }; +} \ No newline at end of file diff --git a/test/core/icache/ICacheSink.hpp b/test/core/icache/ICacheSink.hpp new file mode 100644 index 00000000..a7264d4c --- /dev/null +++ b/test/core/icache/ICacheSink.hpp @@ -0,0 +1,155 @@ +// ICacheSink.hpp +#pragma once + +#include "core/MemoryAccessInfo.hpp" +#include "sparta/simulation/TreeNode.hpp" +#include "sparta/ports/DataPort.hpp" +#include "sparta/events/SingleCycleUniqueEvent.hpp" +#include "sparta/utils/SpartaSharedPointer.hpp" +#include "sparta/utils/LogUtils.hpp" + + +namespace icache_test +{ + class ICacheSink : public sparta::Unit + { + public: + static constexpr char name[] = "icache_sink_unit"; + + class ICacheSinkParameters : public sparta::ParameterSet + { + public: + ICacheSinkParameters(sparta::TreeNode *n) : sparta::ParameterSet(n) + {} + PARAMETER(double, miss_rate, 0, "miss rate per 1k requests") + PARAMETER(uint32_t, latency, 8, "hit latency") + PARAMETER(uint32_t, miss_penalty, 32, "miss latency") + + }; + + struct ICacheResponse { + uint64_t scheduled_time; + olympia::MemoryAccessInfo::CacheState hit_state; + olympia::MemoryAccessInfoPtr access; + }; + + + ICacheSink(sparta::TreeNode *n, const ICacheSinkParameters *params) : + sparta::Unit(n), + latency_(params->latency), + miss_penalty_(params->miss_penalty), + miss_distribution_({1000, params->miss_rate}), + gen_(1) + { + in_icache_req_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(ICacheSink, getRequestFromICache_, olympia::MemoryAccessInfoPtr)); + + sparta::StartupEvent(n, CREATE_SPARTA_HANDLER(ICacheSink, sendInitialCredits_)); + ev_respond_.setContinuing(true); + + } + + void setRandomSeed(uint32_t seed) + { + gen_.seed(seed); + } + + + private: + + //////////////////////////////////////////////////////////////////////////////// + // Methods + //////////////////////////////////////////////////////////////////////////////// + + void sendInitialCredits_() + { + out_icache_credit_.send(8); + } + + void getRequestFromICache_(const olympia::MemoryAccessInfoPtr & mem_access_info_ptr) + { + // Hit's are removed from the pending queue + // Misses are retained. + // Randomly choose to miss, and also randomly generate a latency + ILOG("received request " << mem_access_info_ptr); + ICacheResponse resp; + resp.access = mem_access_info_ptr; + resp.scheduled_time = getClock()->currentCycle() + latency_; + if (miss_distribution_(gen_)) { + resp.hit_state = olympia::MemoryAccessInfo::CacheState::MISS; + } + else { + resp.hit_state = olympia::MemoryAccessInfo::CacheState::HIT; + } + response_queue_.emplace_back(resp); + // mem_access_info_ptr->setCacheState(olympia::MemoryAccessInfo::CacheState::HIT); + // ev_respond_.preparePayload(mem_access_info_ptr)->schedule(10); + ev_respond_.schedule(latency_); + out_icache_credit_.send(1); + } + + void sendResponse_() + { + // Find first response that's ready + auto response_ready = [this](ICacheResponse resp){ + return resp.scheduled_time <= getClock()->currentCycle(); + }; + auto resp_iter = std::find_if(response_queue_.begin(), response_queue_.end(), response_ready); + if (resp_iter == response_queue_.end()) { + ev_respond_.schedule(1); + return; + } + + ILOG("sending response " << resp_iter->access); + out_icache_resp_.send(resp_iter->access); + + // Replay the miss later + resp_iter->access->setCacheState(resp_iter->hit_state); + if (resp_iter->hit_state == olympia::MemoryAccessInfo::CacheState::MISS) { + resp_iter->hit_state = olympia::MemoryAccessInfo::CacheState::HIT; + resp_iter->scheduled_time = getClock()->currentCycle() + miss_penalty_; + ev_respond_.schedule(1); + } + else { + response_queue_.erase(resp_iter); + } + } + + void onStartingTeardown_() override final + { + sparta_assert(response_queue_.empty()); + } + + + //////////////////////////////////////////////////////////////////////////////// + // Variables + //////////////////////////////////////////////////////////////////////////////// + + const uint32_t latency_; + const uint32_t miss_penalty_; + + std::vector response_queue_; + + std::discrete_distribution<> miss_distribution_; + std::mt19937 gen_; + + //////////////////////////////////////////////////////////////////////////////// + // Ports + //////////////////////////////////////////////////////////////////////////////// + sparta::DataInPort in_icache_req_{&unit_port_set_, + "in_icache_req", 0}; + + sparta::DataOutPort out_icache_resp_{&unit_port_set_, + "out_icache_resp", 0}; + + sparta::DataOutPort out_icache_credit_{&unit_port_set_, + "out_icache_credit", 0}; + + //////////////////////////////////////////////////////////////////////////////// + // Events + //////////////////////////////////////////////////////////////////////////////// + sparta::UniqueEvent<> ev_respond_{ + &unit_event_set_, "ev_respond", + CREATE_SPARTA_HANDLER(ICacheSink, sendResponse_)}; + }; +} \ No newline at end of file diff --git a/test/core/icache/ICacheSource.hpp b/test/core/icache/ICacheSource.hpp new file mode 100644 index 00000000..9afc7dd0 --- /dev/null +++ b/test/core/icache/ICacheSource.hpp @@ -0,0 +1,121 @@ +// Source for ICache +#pragma once + +#include "core/MemoryAccessInfo.hpp" +#include "sparta/simulation/TreeNode.hpp" +#include "sparta/ports/DataPort.hpp" +#include "sparta/events/SingleCycleUniqueEvent.hpp" +#include "sparta/utils/SpartaSharedPointer.hpp" +#include "sparta/utils/LogUtils.hpp" + +#include "OlympiaAllocators.hpp" + +namespace icache_test +{ + class ICacheSource : public sparta::Unit + { + public: + static constexpr char name[] = "icache_source_unit"; + + class ICacheSourceParameters : public sparta::ParameterSet + { + public: + ICacheSourceParameters(sparta::TreeNode *n) : sparta::ParameterSet(n) + {} + }; + + ICacheSource(sparta::TreeNode *n, const ICacheSourceParameters *params) : + sparta::Unit(n), + memory_access_allocator_( + sparta::notNull(olympia::OlympiaAllocators::getOlympiaAllocators(n))-> + memory_access_allocator) + { + in_icache_resp_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(ICacheSource, getResponseFromICache_, olympia::MemoryAccessInfoPtr)); + in_icache_credit_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(ICacheSource, getCreditFromICache_, uint32_t)); + } + + // Queue up an ICache request for the address given + void queueRequest(const uint64_t & addr) + { + request_queue_.emplace_back(addr); + ev_send_requests_.schedule(sparta::Clock::Cycle(1)); + } + + + private: + + //////////////////////////////////////////////////////////////////////////////// + // Methods + //////////////////////////////////////////////////////////////////////////////// + + void sendRequests_() + { + if (!request_queue_.empty()) { + if (icache_credits_ > 0) { + auto addr = request_queue_.front(); + auto memory_access_info_ptr = + sparta::allocate_sparta_shared_pointer( + memory_access_allocator_, addr); + ILOG("sending " << memory_access_info_ptr); + out_icache_req_.send(memory_access_info_ptr); + icache_credits_--; + request_queue_.pop_front(); + ++outstanding_reqs_; + } + ev_send_requests_.schedule(1); + } + } + + void getResponseFromICache_(const olympia::MemoryAccessInfoPtr & mem_access_info_ptr) + { + // Hit's are removed from the pending queue + // Misses are retained. + ILOG("received response " << mem_access_info_ptr); + if (mem_access_info_ptr->getCacheState() == olympia::MemoryAccessInfo::CacheState::HIT) { + --outstanding_reqs_; + } + } + + void getCreditFromICache_(const uint32_t & credits) + { + icache_credits_ += credits; + } + + void onStartingTeardown_() override final + { + sparta_assert(outstanding_reqs_ == 0); + } + + + //////////////////////////////////////////////////////////////////////////////// + // Variables + //////////////////////////////////////////////////////////////////////////////// + + olympia::MemoryAccessInfoAllocator & memory_access_allocator_; + uint32_t icache_credits_ = 0; + std::deque request_queue_; + + uint32_t outstanding_reqs_ = 0; + + //////////////////////////////////////////////////////////////////////////////// + // Ports + //////////////////////////////////////////////////////////////////////////////// + sparta::DataOutPort out_icache_req_{&unit_port_set_, + "out_icache_req", 0}; + + sparta::DataInPort in_icache_resp_{&unit_port_set_, + "in_icache_resp", 0}; + + sparta::DataInPort in_icache_credit_{&unit_port_set_, + "in_icache_credit", 0}; + + //////////////////////////////////////////////////////////////////////////////// + // Events + //////////////////////////////////////////////////////////////////////////////// + sparta::UniqueEvent<> ev_send_requests_{&unit_event_set_, "ev_send_requests", + CREATE_SPARTA_HANDLER(ICacheSource, sendRequests_)}; + + }; +} \ No newline at end of file diff --git a/test/core/icache/ICache_test.cpp b/test/core/icache/ICache_test.cpp new file mode 100644 index 00000000..bac017fa --- /dev/null +++ b/test/core/icache/ICache_test.cpp @@ -0,0 +1,185 @@ +// ICache test + +#include "sparta/sparta.hpp" +#include "sparta/app/Simulation.hpp" +#include "sparta/app/CommandLineSimulator.hpp" +#include "sparta/simulation/ClockManager.hpp" +#include "sparta/kernel/Scheduler.hpp" +#include "sparta/utils/SpartaTester.hpp" +#include "sparta/utils/SpartaSharedPointer.hpp" +#include "sparta/utils/SpartaTester.hpp" + +#include "test/core/icache/ICacheSink.hpp" +#include "test/core/icache/ICacheSource.hpp" +#include "test/core/icache/ICacheChecker.hpp" + +#include "ICache.hpp" +#include "OlympiaAllocators.hpp" + +#include + +class ICacheSim : public sparta::app::Simulation{ +public: + ICacheSim(sparta::Scheduler *sched) : + sparta::app::Simulation("Test_special_params", sched){} + + virtual ~ICacheSim(){ + getRoot()->enterTeardown(); + } +private: + void buildTree_() override + { + auto rtn = getRoot(); + + allocators_tn_.reset(new olympia::OlympiaAllocators(rtn)); + + // ICache + tns_to_delete_.emplace_back(new sparta::ResourceTreeNode(rtn, + "icache", + sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, + "Instruction Cache", + &icache_fact)); + + // Source + tns_to_delete_.emplace_back(new sparta::ResourceTreeNode(rtn, + "source", + sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, + "Source", + &source_fact)); + // Sink + tns_to_delete_.emplace_back(new sparta::ResourceTreeNode(rtn, + "sink", + sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, + "Sink", + &sink_fact)); + + tns_to_delete_.emplace_back(new sparta::ResourceTreeNode(rtn, + "checker", + sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, + "Checker", + &checker_fact)); + + }; + void configureTree_() override{}; + void bindTree_() override + { + auto * root_node = getRoot(); + // Bind up source + sparta::bind(root_node->getChildAs("icache.ports.in_fetch_req"), + root_node->getChildAs("source.ports.out_icache_req")); + sparta::bind(root_node->getChildAs("icache.ports.out_fetch_credit"), + root_node->getChildAs("source.ports.in_icache_credit")); + sparta::bind(root_node->getChildAs("icache.ports.out_fetch_resp"), + root_node->getChildAs("source.ports.in_icache_resp")); + + // Bind up sink + sparta::bind(root_node->getChildAs("icache.ports.out_l2cache_req"), + root_node->getChildAs("sink.ports.in_icache_req")); + sparta::bind(root_node->getChildAs("icache.ports.in_l2cache_resp"), + root_node->getChildAs("sink.ports.out_icache_resp")); + sparta::bind(root_node->getChildAs("icache.ports.in_l2cache_ack"), + root_node->getChildAs("sink.ports.out_icache_credit")); + + // Bind up checker + sparta::bind(root_node->getChildAs("source.ports.out_icache_req"), + root_node->getChildAs("checker.ports.in_fetch_req")); + sparta::bind(root_node->getChildAs("icache.ports.out_fetch_resp"), + root_node->getChildAs("checker.ports.in_fetch_resp")); + sparta::bind(root_node->getChildAs("icache.ports.out_l2cache_req"), + root_node->getChildAs("checker.ports.in_l2cache_req")); + sparta::bind(root_node->getChildAs("sink.ports.out_icache_resp"), + root_node->getChildAs("checker.ports.in_l2cache_resp")); + }; + + std::unique_ptr allocators_tn_; + + sparta::ResourceFactory icache_fact; + sparta::ResourceFactory source_fact; + sparta::ResourceFactory sink_fact; + sparta::ResourceFactory checker_fact; + + std::vector> tns_to_delete_; + +}; + +const char USAGE[] = + "Usage:\n" + " \n" + "\n"; + +sparta::app::DefaultValues DEFAULTS; + +int main(int argc, char **argv) +{ + + std::string testname; + uint32_t seed = 1; + + sparta::app::CommandLineSimulator cls(USAGE, DEFAULTS); + auto & app_opts = cls.getApplicationOptions(); + app_opts.add_options() + ("testname", + sparta::app::named_value("TESTNAME", &testname)->default_value(""), + "Provide a testname to run", + "Test to run") + ("seed", + sparta::app::named_value("SEED", &seed)->default_value(1), + "Provide a value to seed the random generators", + "random seed"); + + int err_code = 0; + if(!cls.parse(argc, argv, err_code)){ + sparta_assert(false, "Command line parsing failed"); // Any errors already printed to cerr + } + + sparta::Scheduler sched; + ICacheSim sim(&sched); + cls.populateSimulation(&sim); + sparta::RootTreeNode* root = sim.getRoot(); + + icache_test::ICacheChecker *checker = root->getChild("checker")->getResourceAs(); + checker->setDUT(root->getChild("icache")->getResourceAs()); + + icache_test::ICacheSource *source = root->getChild("source")->getResourceAs(); + + icache_test::ICacheSink *sink = root->getChild("sink")->getResourceAs(); + sink->setRandomSeed(seed); + + if (testname == "single_access") { + source->queueRequest(1); + cls.runSimulator(&sim, 100); + } + else if (testname == "simple") { + for (int i = 0; i < 4; i++) { + for (int j = 0; j < 8; j++) { + source->queueRequest(8 << j); + } + } + cls.runSimulator(&sim, 1000); + } + else if (testname == "random") { + std::mt19937 gen(seed); + std::lognormal_distribution<> d(2.0, 1.0); + std::vector addrs = {1}; + for (int i = 0; i < 256; ++i) { + auto addr = addrs.back() + uint64_t(d(gen)); + addrs.push_back(addr); + } + for (int i = 0; i < 2048; ++i) { + auto idx = uint32_t(d(gen)) % addrs.size(); + source->queueRequest(addrs[idx]); + if (i % 128 == 0) { + std::shuffle(addrs.begin(), addrs.end(), gen); + } + } + cls.runSimulator(&sim, 100000); + } + else { + sparta_assert(false, "Must provide a valid testname"); + } + return 0; +} \ No newline at end of file diff --git a/test/core/l2cache/expected_output/hit_case.out.EXPECTED b/test/core/l2cache/expected_output/hit_case.out.EXPECTED index abf3ec67..c47a5eac 100644 --- a/test/core/l2cache/expected_output/hit_case.out.EXPECTED +++ b/test/core/l2cache/expected_output/hit_case.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Saturday Sat Jan 27 08:59:40 2024 -#Elapsed: 0.004092s +#Start: Thursday Thu Feb 8 10:29:35 2024 +#Elapsed: 0.024913s {0000000000 00000000 top.l2cache info} L2Cache: L2Cache construct: #4294967295 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to ICache : 8 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to DCache : 8 @@ -28,16 +28,16 @@ {0000000003 00000003 top.dcache info} ReceiveAck_: Ack: '8' Received {0000000003 00000003 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. {0000000003 00000003 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000011 00000011 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000012 00000012 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000012 00000012 top.l2cache info} appendBIUReqQueue_: Append L2Cache->BIU req queue {0000000012 00000012 top.l2cache info} handle_L2Cache_BIU_Req_: L2Cache Request sent to BIU : Current BIU credit available = 31 {0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' sinked -{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000024 00000024 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 {0000000034 00000034 top.l2cache info} getRespFromBIU_: Response received from BIU on the port @@ -48,16 +48,16 @@ {0000000035 00000035 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU {0000000035 00000035 top.l2cache info} create_Req_: Request found in miss_pending_buffer_ with SrcUnit : DCACHE {0000000036 00000036 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : BIU -{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000044 00000044 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef {0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Reload Complete: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000045 00000045 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000045 00000045 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000045 00000045 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! {0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Received -{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000046 00000046 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000046 00000046 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! {0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Received @@ -77,15 +77,15 @@ {0000000053 00000053 top.dcache info} ReceiveAck_: Ack: '8' Received {0000000053 00000053 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. {0000000053 00000053 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000061 00000061 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' +{0000000061 00000061 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' {0000000061 00000061 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000062 00000062 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' +{0000000062 00000062 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' {0000000062 00000062 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000062 00000062 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' +{0000000062 00000062 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' {0000000062 00000062 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000062 00000062 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! {0000000063 00000063 top.icache info} ReceiveInst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' ' Received -{0000000063 00000063 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' +{0000000063 00000063 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' {0000000063 00000063 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000063 00000063 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! {0000000064 00000064 top.dcache info} ReceiveInst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' ' Received diff --git a/test/core/l2cache/expected_output/single_access.out.EXPECTED b/test/core/l2cache/expected_output/single_access.out.EXPECTED index bf6d8619..d7e055da 100644 --- a/test/core/l2cache/expected_output/single_access.out.EXPECTED +++ b/test/core/l2cache/expected_output/single_access.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Saturday Sat Jan 27 08:59:40 2024 -#Elapsed: 0.003294s +#Start: Thursday Thu Feb 8 10:29:35 2024 +#Elapsed: 0.031446s {0000000000 00000000 top.l2cache info} L2Cache: L2Cache construct: #4294967295 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to ICache : 8 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to DCache : 8 @@ -28,16 +28,16 @@ {0000000003 00000003 top.dcache info} ReceiveAck_: Ack: '8' Received {0000000003 00000003 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. {0000000003 00000003 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000011 00000011 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000012 00000012 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000012 00000012 top.l2cache info} appendBIUReqQueue_: Append L2Cache->BIU req queue {0000000012 00000012 top.l2cache info} handle_L2Cache_BIU_Req_: L2Cache Request sent to BIU : Current BIU credit available = 31 {0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' sinked -{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000024 00000024 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 {0000000034 00000034 top.l2cache info} getRespFromBIU_: Response received from BIU on the port @@ -48,16 +48,16 @@ {0000000035 00000035 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU {0000000035 00000035 top.l2cache info} create_Req_: Request found in miss_pending_buffer_ with SrcUnit : DCACHE {0000000036 00000036 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : BIU -{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000044 00000044 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef {0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Reload Complete: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000045 00000045 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000045 00000045 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000045 00000045 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! {0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Received -{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' {0000000046 00000046 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000046 00000046 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! {0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Received From 431e74e72a35074e85c9bb6f0a37aee75093e9f1 Mon Sep 17 00:00:00 2001 From: Daniel Bone Date: Sun, 11 Feb 2024 23:46:28 +0000 Subject: [PATCH 02/14] Connect up ICache to Fetch --- core/CPUFactories.hpp | 10 +- core/CPUTopology.cpp | 32 +++++++ core/Fetch.cpp | 194 ++++++++++++++++++++++++++++++++------ core/Fetch.hpp | 45 ++++++++- core/Inst.cpp | 2 +- core/Inst.hpp | 17 +++- core/InstGenerator.cpp | 1 + core/MemoryAccessInfo.hpp | 8 ++ mss/BIU.cpp | 2 + mss/L2Cache.cpp | 5 +- mss/L2Cache.hpp | 2 +- 11 files changed, 280 insertions(+), 38 deletions(-) diff --git a/core/CPUFactories.hpp b/core/CPUFactories.hpp index bf0799d5..28f90dae 100644 --- a/core/CPUFactories.hpp +++ b/core/CPUFactories.hpp @@ -5,6 +5,7 @@ #include "sparta/simulation/ResourceFactory.hpp" #include "Core.hpp" +#include "ICache.hpp" #include "Fetch.hpp" #include "Decode.hpp" #include "Rename.hpp" @@ -39,6 +40,10 @@ namespace olympia{ sparta::ResourceFactory core_rf; + //! \brief Resource Factory to build an Instruction Cache Unit + sparta::ResourceFactory icache_rf; + //! \brief Resource Factory to build a Fetch Unit sparta::ResourceFactory fetch_rf; @@ -56,8 +61,7 @@ namespace olympia{ //! \brief Resource Factory to build a Execute Unit ExecuteFactory execute_rf; - - //! \brief Resource Factory to build a MMU Unit + //! \brief Resource Factory to build a Data Cache Unit sparta::ResourceFactory dcache_rf; @@ -100,7 +104,7 @@ namespace olympia{ // //! \brief Resource Factory to build a IssueQueue Unit // sparta::ResourceFactory issue_queue_rf; - + //! \brief Set up the Mavis Decode functional unit MavisFactory mavis_rf; }; // struct CPUFactories diff --git a/core/CPUTopology.cpp b/core/CPUTopology.cpp index b4260c67..9829a431 100644 --- a/core/CPUTopology.cpp +++ b/core/CPUTopology.cpp @@ -27,6 +27,14 @@ olympia::CoreTopologySimple::CoreTopologySimple(){ sparta::TreeNode::GROUP_IDX_NONE, &factories->flushmanager_rf }, + { + "icache", + "cpu.core*", + "Instruction Cache Unit", + sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, + &factories->icache_rf + }, { "fetch", "cpu.core*", @@ -152,6 +160,18 @@ olympia::CoreTopologySimple::CoreTopologySimple(){ //! Instantiating ports of this topology port_connections = { + { + "cpu.core*.fetch.ports.out_fetch_icache_req", + "cpu.core*.icache.ports.in_fetch_req" + }, + { + "cpu.core*.fetch.ports.in_icache_fetch_resp", + "cpu.core*.icache.ports.out_fetch_resp" + }, + { + "cpu.core*.fetch.ports.in_icache_fetch_credits", + "cpu.core*.icache.ports.out_fetch_credit" + }, { "cpu.core*.fetch.ports.out_fetch_queue_write", "cpu.core*.decode.ports.in_fetch_queue_write" @@ -220,6 +240,18 @@ olympia::CoreTopologySimple::CoreTopologySimple(){ "cpu.core*.dcache.ports.in_l2cache_resp", "cpu.core*.l2cache.ports.out_l2cache_dcache_resp" }, + { + "cpu.core*.icache.ports.out_l2cache_req", + "cpu.core*.l2cache.ports.in_icache_l2cache_req" + }, + { + "cpu.core*.icache.ports.in_l2cache_ack", + "cpu.core*.l2cache.ports.out_l2cache_icache_ack" + }, + { + "cpu.core*.icache.ports.in_l2cache_resp", + "cpu.core*.l2cache.ports.out_l2cache_icache_resp" + }, { "cpu.core*.l2cache.ports.out_l2cache_biu_req", "cpu.core*.biu.ports.in_biu_req" diff --git a/core/Fetch.cpp b/core/Fetch.cpp index 0629111f..b4124deb 100644 --- a/core/Fetch.cpp +++ b/core/Fetch.cpp @@ -9,6 +9,7 @@ #include "Fetch.hpp" #include "InstGenerator.hpp" #include "MavisUnit.hpp" +#include "OlympiaAllocators.hpp" #include "sparta/utils/LogUtils.hpp" #include "sparta/events/StartupEvent.hpp" @@ -22,7 +23,10 @@ namespace olympia sparta::Unit(node), num_insts_to_fetch_(p->num_to_fetch), skip_nonuser_mode_(p->skip_nonuser_mode), - my_clk_(getClock()) + my_clk_(getClock()), + ibuf_capacity_(32), // buffer up instructions read from trace + memory_access_allocator_(sparta::notNull(OlympiaAllocators::getOlympiaAllocators(node)) + ->memory_access_allocator) { in_fetch_queue_credits_. registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(Fetch, receiveFetchQueueCredits_, uint32_t)); @@ -30,8 +34,18 @@ namespace olympia in_fetch_flush_redirect_. registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(Fetch, flushFetch_, FlushManager::FlushingCriteria)); - fetch_inst_event_.reset(new sparta::SingleCycleUniqueEvent<>(&unit_event_set_, "fetch_random", - CREATE_SPARTA_HANDLER(Fetch, fetchInstruction_))); + in_icache_fetch_resp_. + registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(Fetch, receiveCacheResponse_, MemoryAccessInfoPtr)); + + in_icache_fetch_credits_. + registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(Fetch, receiveCacheCredit_, uint32_t)); + + ev_fetch_insts.reset(new sparta::SingleCycleUniqueEvent<>(&unit_event_set_, "fetch_instruction_data", + CREATE_SPARTA_HANDLER(Fetch, fetchInstruction_))); + + ev_drive_insts.reset(new sparta::SingleCycleUniqueEvent<>(&unit_event_set_, "drive_instructions_out", + CREATE_SPARTA_HANDLER(Fetch, driveInstructions_))); + // Schedule a single event to start reading from a trace file sparta::StartupEvent(node, CREATE_SPARTA_HANDLER(Fetch, initialize_)); @@ -49,52 +63,151 @@ namespace olympia workload->getValueAsString(), skip_nonuser_mode_); - fetch_inst_event_->schedule(1); + ev_fetch_insts->schedule(1); } + void Fetch::fetchInstruction_() { - const uint32_t upper = std::min(credits_inst_queue_, num_insts_to_fetch_); + // Prefill the ibuf with some instructions read from the tracefile + // keeping enough capacity to group them into cache block accesses. + for (uint32_t i = ibuf_.size(); i < ibuf_capacity_; ++i) + { + const auto & inst_ptr = inst_generator_->getNextInst(my_clk_); + if (SPARTA_EXPECT_TRUE(nullptr != inst_ptr)) { + ibuf_.emplace_back(inst_ptr); + } + else { + break; + } + } + + if (credits_icache_ == 0 || ibuf_.empty() || fetch_buffer_.size() > fetch_buffer_capacity_) { return; } + + // Gather instructions going to the same cacheblock + // TODO this should be a constant related to the ICache + const uint32_t icache_block_shift_ = 4; // 16B blocks.. + // TODO instructions which straddle should be placed into the next group + auto different_blocks = [icache_block_shift_](const auto &lhs, const auto &rhs) { + return (lhs->getPC() >> icache_block_shift_) != (rhs->getPC() >> icache_block_shift_) || + lhs->isTakenBranch() || + rhs->isCoF(); + }; + + auto block_end = std::adjacent_find(ibuf_.begin(), ibuf_.end(), different_blocks); + if (block_end != ibuf_.end()) { + ++block_end; + } + + // Send to ICache + auto memory_access_ptr = sparta::allocate_sparta_shared_pointer(memory_access_allocator_, + ibuf_.front()->getPC()); + + InstGroupPtr fetch_group_ptr = sparta::allocate_sparta_shared_pointer(instgroup_allocator); + + // Place in fetch group for the memory access, and place in fetch buffer for later processing. + for (auto iter = ibuf_.begin(); iter != block_end; iter++) { + fetch_group_ptr->emplace_back(*iter); + fetch_buffer_.emplace_back(*iter); + } + + // Set the last in block + fetch_buffer_.back()->setLastInFetchBlock(true); + + // Associate the icache transaction with the instructions + memory_access_ptr->setFetchGroup(fetch_group_ptr); + + ILOG("requesting: " << fetch_group_ptr); + + out_fetch_icache_req_.send(memory_access_ptr); + --credits_icache_; + + // We want to track blocks, not instructions. + ++fetch_buffer_occupancy_; + + ibuf_.erase(ibuf_.begin(), block_end); + if (!ibuf_.empty() && credits_icache_ > 0 && fetch_buffer_occupancy_ < fetch_buffer_capacity_) { + ev_fetch_insts->schedule(1); + } + } + + // Read instructions from the fetch buffer and send them to decode + void Fetch::driveInstructions_() + { + const uint32_t upper = std::min({credits_inst_queue_, num_insts_to_fetch_, + static_cast(fetch_buffer_.size())}); // Nothing to send. Don't need to schedule this again. - if(upper == 0) { return; } + if (upper == 0) { return ; } InstGroupPtr insts_to_send = sparta::allocate_sparta_shared_pointer(instgroup_allocator); - for(uint32_t i = 0; i < upper; ++i) + for (uint32_t i = 0; i < upper; ++i) { - InstPtr ex_inst = inst_generator_->getNextInst(my_clk_); - if(SPARTA_EXPECT_TRUE(nullptr != ex_inst)) - { - ex_inst->setSpeculative(speculative_path_); - insts_to_send->emplace_back(ex_inst); + const auto entry = fetch_buffer_.front(); - ILOG("Sending: " << ex_inst << " down the pipe"); - } - else { + // Can't send instructions that still waiting for ICache data + if (entry->getStatus() != Inst::Status::FETCHED) { break; } - } - if(false == insts_to_send->empty()) - { - out_fetch_queue_write_.send(insts_to_send); + // Don't group instructions where there has been a change of flow + if (entry->isCoF() && insts_to_send->size() > 0) { + break; + } - credits_inst_queue_ -= static_cast (insts_to_send->size()); + // Send instruction to decode + entry->setSpeculative(speculative_path_); + insts_to_send->emplace_back(entry); + ILOG("Sending: " << entry << " down the pipe") + fetch_buffer_.pop_front(); - if((credits_inst_queue_ > 0) && (false == inst_generator_->isDone())) { - fetch_inst_event_->schedule(1); + if (entry->isLastInFetchBlock()) { + --fetch_buffer_occupancy_; } - if(SPARTA_EXPECT_FALSE(info_logger_)) { - info_logger_ << "Fetch: send num_inst=" << insts_to_send->size() - << " instructions, remaining credit=" << credits_inst_queue_; + // Only one taken branch per group + if (entry->isTakenBranch()) { + break; } } - else if(SPARTA_EXPECT_FALSE(info_logger_)) { - info_logger_ << "Fetch: no instructions from trace"; + + credits_inst_queue_ -= static_cast(insts_to_send->size()); + out_fetch_queue_write_.send(insts_to_send); + + if (!fetch_buffer_.empty() && credits_inst_queue_ > 0) { + ev_drive_insts->schedule(1); + } + + ev_fetch_insts->schedule(1); + + } + + void Fetch::receiveCacheResponse_(const MemoryAccessInfoPtr &response) + { + if (response->getCacheState() == MemoryAccessInfo::CacheState::HIT) { + // Mark instructions as fetched + auto & fetched_insts = response->getFetchGroup(); + sparta_assert(fetched_insts != nullptr); + for(auto & inst : *fetched_insts) { + inst->setStatus(Inst::Status::FETCHED); + } + + ev_drive_insts->schedule(sparta::Clock::Cycle(0)); } } + // Called when ICache has room + void Fetch::receiveCacheCredit_(const uint32_t &dat) + { + credits_icache_ += dat; + + ILOG("Fetch: receive num_credits_icache=" << dat + << ", total credits_icache=" << credits_icache_); + + // Schedule a fetch event this cycle + ev_fetch_insts->schedule(sparta::Clock::Cycle(0)); + } + // Called when decode has room void Fetch::receiveFetchQueueCredits_(const uint32_t & dat) { credits_inst_queue_ += dat; @@ -103,7 +216,7 @@ namespace olympia << ", total decode_credits=" << credits_inst_queue_); // Schedule a fetch event this cycle - fetch_inst_event_->schedule(sparta::Clock::Cycle(0)); + ev_drive_insts->schedule(sparta::Clock::Cycle(0)); } // Called from FlushManager via in_fetch_flush_redirect_port @@ -126,8 +239,33 @@ namespace olympia // Cancel all previously sent instructions on the outport out_fetch_queue_write_.cancel(); + // Cancel any ICache request + out_fetch_icache_req_.cancel(); + + // Clear internal buffers + ibuf_.clear(); + fetch_buffer_.clear(); + // No longer speculative // speculative_path_ = false; } + void Fetch::dumpDebugContent_(std::ostream & output) const + { + output << "Fetch Contents" << std::endl; + for (const auto & entry : fetch_buffer_) + { + output << '\t' << entry << std::endl; + } + } + + void Fetch::onStartingTeardown_() + { + // if ((false == rob_stopped_simulation_) && (false == fetch_buffer_.empty())) + // { + // dumpDebugContent_(std::cerr); + // sparta_assert(false, "fetch buffer has pending instructions"); + // } + } + } diff --git a/core/Fetch.hpp b/core/Fetch.hpp index 1538bb17..36b4c236 100644 --- a/core/Fetch.hpp +++ b/core/Fetch.hpp @@ -19,6 +19,7 @@ #include "CoreTypes.hpp" #include "InstGroup.hpp" #include "FlushManager.hpp" +#include "MemoryAccessInfo.hpp" namespace olympia { @@ -88,6 +89,18 @@ namespace olympia sparta::DataInPort in_fetch_flush_redirect_ {&unit_port_set_, "in_fetch_flush_redirect", sparta::SchedulingPhase::Flush, 1}; + // Instruction Cache Request + sparta::DataOutPort out_fetch_icache_req_ + {&unit_port_set_, "out_fetch_icache_req"}; + + // Instruction Cache Response + sparta::DataInPort in_icache_fetch_resp_ + {&unit_port_set_, "in_icache_fetch_resp", sparta::SchedulingPhase::Tick, 1}; + + // Instruction Cache Credit + sparta::DataInPort in_icache_fetch_credits_ + {&unit_port_set_, "in_icache_fetch_credits", sparta::SchedulingPhase::Tick, 0}; + //////////////////////////////////////////////////////////////////////////////// // Instruction fetch // Number of instructions to fetch @@ -99,16 +112,34 @@ namespace olympia // Number of credits from decode that fetch has uint32_t credits_inst_queue_ = 0; + uint32_t credits_icache_ = 0; + // Unit's clock const sparta::Clock * my_clk_ = nullptr; + // Size of trace buffer (must be sized >= L1ICache bandwidth / 2B) + const uint32_t ibuf_capacity_; + + // allocator for ICache transactions + MemoryAccessInfoAllocator & memory_access_allocator_; + + uint32_t fetch_buffer_occupancy_ = 0; + const uint32_t fetch_buffer_capacity_ = 16; + // Instruction generation std::unique_ptr inst_generator_; // Fetch instruction event, triggered when there are credits // from decode. The callback set is either to fetch random // instructions or a perfect IPC set - std::unique_ptr> fetch_inst_event_; + std::unique_ptr> ev_fetch_insts; + std::unique_ptr> ev_drive_insts; + + // Buffers up instructions read from the tracefile + std::deque ibuf_; + + // Holds fetched instructions from the ICache + std::deque fetch_buffer_; //////////////////////////////////////////////////////////////////////////////// // Callbacks @@ -122,9 +153,21 @@ namespace olympia // Read data from a trace void fetchInstruction_(); + // Read instructions from the fetch buffer and send them to decode + void driveInstructions_(); + // Receive flush from FlushManager void flushFetch_(const FlushManager::FlushingCriteria &); + // Receieve the number of free credits from the instruction cache + void receiveCacheCredit_(const uint32_t &); + + // Receive read data from the instruction cache + void receiveCacheResponse_(const MemoryAccessInfoPtr &); + + void onStartingTeardown_() override; + void dumpDebugContent_(std::ostream&) const override final; + // Are we fetching a speculative path? bool speculative_path_ = false; }; diff --git a/core/Inst.cpp b/core/Inst.cpp index 9a067076..59182a65 100644 --- a/core/Inst.cpp +++ b/core/Inst.cpp @@ -54,7 +54,7 @@ namespace olympia is_condbranch_(opcode_info_->isInstType(mavis::OpcodeInfo::InstructionTypes::CONDITIONAL)), is_call_(isCallInstruction(opcode_info)), is_return_(isReturnInstruction(opcode_info)), - status_state_(Status::FETCHED) + status_state_(Status::BEFORE_FETCH) { sparta_assert(inst_arch_info_ != nullptr, "Mavis decoded the instruction, but Olympia has no uarch data for it: " diff --git a/core/Inst.hpp b/core/Inst.hpp index 66e66ef1..4465ab2b 100644 --- a/core/Inst.hpp +++ b/core/Inst.hpp @@ -83,8 +83,9 @@ namespace olympia enum class Status : std::uint16_t { - FETCHED = 0, - __FIRST = FETCHED, + BEFORE_FETCH = 0, + __FIRST = BEFORE_FETCH, + FETCHED, DECODED, RENAMED, DISPATCHED, @@ -181,6 +182,10 @@ namespace olympia // TBD -- add branch prediction void setSpeculative(bool spec) { is_speculative_ = spec; } + // Last instruction within the cache block fetched from the ICache + void setLastInFetchBlock(bool last) { last_in_fetch_block_ = last; } + bool isLastInFetchBlock() const { return last_in_fetch_block_; } + // Opcode information std::string getMnemonic() const { return opcode_info_->getMnemonic(); } @@ -221,6 +226,9 @@ namespace olympia bool isReturn() const { return is_return_; } + void setCoF(const bool &cof) { is_cof_ = cof; } + bool isCoF() const { return is_cof_; } + // Rename information core_types::RegisterBitMask & getSrcRegisterBitMask(const core_types::RegFile rf) { @@ -276,7 +284,9 @@ namespace olympia const bool is_condbranch_; const bool is_call_; const bool is_return_; + bool is_cof_ = false; // Is change of flow bool is_taken_branch_ = false; + bool last_in_fetch_block_ = false; // This is the last instruction in the fetch block sparta::Scheduleable* ev_retire_ = nullptr; Status status_state_; @@ -300,6 +310,9 @@ namespace olympia { switch (status) { + case Inst::Status::BEFORE_FETCH: + os << "BEFORE_FETCH"; + break; case Inst::Status::FETCHED: os << "FETCHED"; break; diff --git a/core/InstGenerator.cpp b/core/InstGenerator.cpp index c68c9e15..ed8dd068 100644 --- a/core/InstGenerator.cpp +++ b/core/InstGenerator.cpp @@ -203,6 +203,7 @@ namespace olympia //For misaligns, more than 1 address is provided //inst->setVAddrVector(std::move(addrs)); } + inst->setCoF(next_it_->isCoF()); if (next_it_->isBranch()) { inst->setTakenBranch(next_it_->isTakenBranch()); diff --git a/core/MemoryAccessInfo.hpp b/core/MemoryAccessInfo.hpp index 01f7e262..133f3afa 100644 --- a/core/MemoryAccessInfo.hpp +++ b/core/MemoryAccessInfo.hpp @@ -8,6 +8,7 @@ #include "sparta/utils/SpartaSharedPointer.hpp" #include "sparta/utils/SpartaSharedPointerAllocator.hpp" #include "Inst.hpp" +#include "InstGroup.hpp" namespace olympia { @@ -149,6 +150,9 @@ namespace olympia void setDataReady(bool is_ready) { cache_data_ready_ = is_ready; } + void setFetchGroup(const InstGroupPtr &group) { fetch_group_ = group; } + const InstGroupPtr & getFetchGroup() const { return fetch_group_; } + const LoadStoreInstIterator getIssueQueueIterator() const { return issue_queue_iterator_; } void setIssueQueueIterator(const LoadStoreInstIterator & iter) @@ -195,6 +199,10 @@ namespace olympia // Not for functional/performance purpose) MemoryAccessInfoPtr next_req_ = nullptr; + // Instructions that this memory access is fetching + // *USED* only for instruction fetch + InstGroupPtr fetch_group_; + LoadStoreInstIterator issue_queue_iterator_; LoadStoreInstIterator replay_queue_iterator_; }; diff --git a/mss/BIU.cpp b/mss/BIU.cpp index 82452e1f..d1e2fb7f 100644 --- a/mss/BIU.cpp +++ b/mss/BIU.cpp @@ -27,6 +27,8 @@ namespace olympia_mss sparta::StartupEvent(node, CREATE_SPARTA_HANDLER(BIU, sendInitialCredits_)); ILOG("BIU construct: #" << node->getGroupIdx()); + + ev_handle_mss_ack_ >> ev_handle_biu_req_ >> ev_handle_biu_l2cache_ack_; } diff --git a/mss/L2Cache.cpp b/mss/L2Cache.cpp index 55c877d6..e2fc24ae 100644 --- a/mss/L2Cache.cpp +++ b/mss/L2Cache.cpp @@ -247,8 +247,9 @@ namespace olympia_mss // Returning resp to ICache void L2Cache::handle_L2Cache_ICache_Ack_() { - uint32_t available_slots = icache_req_queue_size_ - icache_req_queue_.size(); - out_l2cache_icache_ack_.send(available_slots); + // uint32_t available_slots = icache_req_queue_size_ - icache_req_queue_.size(); + // out_l2cache_icache_ack_.send(available_slots); + out_l2cache_icache_ack_.send(1); ++num_acks_to_icache_; ILOG("L2Cache->ICache : Ack is sent."); diff --git a/mss/L2Cache.hpp b/mss/L2Cache.hpp index a5fb1610..22da8f99 100644 --- a/mss/L2Cache.hpp +++ b/mss/L2Cache.hpp @@ -57,7 +57,7 @@ namespace olympia_mss PARAMETER(bool, l2_always_hit, false, "L2 will always hit") PARAMETER(uint32_t, l2cache_latency, 10, "Cache Lookup HIT latency") - PARAMETER(bool, is_icache_connected, false, "Does this unit have ICache connected to it") + PARAMETER(bool, is_icache_connected, true, "Does this unit have ICache connected to it") PARAMETER(bool, is_dcache_connected, true, "Does this unit have DCache connected to it") }; From b09fd6c82b0c6d119ab660e637833a3734b75e67 Mon Sep 17 00:00:00 2001 From: Daniel Bone Date: Mon, 12 Feb 2024 10:50:36 +0000 Subject: [PATCH 03/14] Fix rename and issue tests accounting for icache latency --- .../issue_queue/test_cores/test_big_core_full.yaml | 7 +++++-- test/core/lsu/test_cores/test_small_core_full.yaml | 6 ++++-- test/core/rename/Rename_test.cpp | 10 ++++++---- test/core/rename/test_cores/test_medium_core_full.yaml | 6 ++++-- test/core/rename/test_cores/test_small_core_full.yaml | 6 ++++-- 5 files changed, 23 insertions(+), 12 deletions(-) diff --git a/test/core/issue_queue/test_cores/test_big_core_full.yaml b/test/core/issue_queue/test_cores/test_big_core_full.yaml index 66c1ec15..72e61334 100644 --- a/test/core/issue_queue/test_cores/test_big_core_full.yaml +++ b/test/core/issue_queue/test_cores/test_big_core_full.yaml @@ -1,3 +1,6 @@ +top.cpu.core0.icache.params.l1_always_hit: true +top.cpu.core0.icache.params.cache_latency: 0 + # # Set up the pipeline for a 8-wide machine # @@ -10,13 +13,13 @@ top.cpu.core0.extension.core_extensions: ["int", "mul", "i2f", "cmov"], ["int"], ["int"], - ["float", "faddsub", "fmac"], + ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], ["br"] ] issue_queue_to_pipe_map: - [ + [ ["0", "1"], ["2", "3"], ["4", "5"], diff --git a/test/core/lsu/test_cores/test_small_core_full.yaml b/test/core/lsu/test_cores/test_small_core_full.yaml index da6e5864..35899e52 100644 --- a/test/core/lsu/test_cores/test_small_core_full.yaml +++ b/test/core/lsu/test_cores/test_small_core_full.yaml @@ -4,6 +4,8 @@ top.cpu.core0: fetch.params.num_to_fetch: 2 + icache.params.l1_always_hit: true + icache.params.cache_latency: 0 decode.params.num_to_decode: 2 rename.params.num_to_rename: 2 dispatch.params.num_to_dispatch: 2 @@ -22,11 +24,11 @@ top.cpu.core0.extension.core_extensions: pipelines: [ ["int", "mul", "i2f", "cmov", "div"], - ["float", "faddsub", "fmac", "f2i"], + ["float", "faddsub", "fmac", "f2i"], ["br"] ] issue_queue_to_pipe_map: - [ + [ ["0"], ["1"], ["2"] diff --git a/test/core/rename/Rename_test.cpp b/test/core/rename/Rename_test.cpp index 12b289d1..ca3c7225 100644 --- a/test/core/rename/Rename_test.cpp +++ b/test/core/rename/Rename_test.cpp @@ -426,7 +426,7 @@ void runTest(int argc, char **argv) { root_node->getChild("cpu.core0.execute.iq1") ->getResourceAs(); olympia::IssueQueueTester issuequeue_tester; - cls.runSimulator(&sim, 7); + cls.runSimulator(&sim, 8); issuequeue_tester.test_dependent_integer_first_instruction(*my_issuequeue); issuequeue_tester.test_dependent_integer_second_instruction( *my_issuequeue1); @@ -437,7 +437,9 @@ void runTest(int argc, char **argv) { ->getResourceAs(); olympia::RenameTester rename_tester; - cls.runSimulator(&sim, 4); + // Must stop the simulation before it retires the i2f instructions, + // otherwise the register would have been moved back into the freelist + cls.runSimulator(&sim, 8); rename_tester.test_float(*my_rename); } else if (input_file == "raw_int_lsu.json") { // testing RAW dependency for address operand @@ -451,7 +453,7 @@ void runTest(int argc, char **argv) { root_node->getChild("cpu.core0.execute.iq0") ->getResourceAs(); olympia::IssueQueueTester issuequeue_tester; - cls.runSimulator(&sim, 7); + cls.runSimulator(&sim, 8); issuequeue_tester.test_dependent_integer_first_instruction(*my_issuequeue); lsu_tester.test_dependent_lsu_instruction(*my_lsu); lsu_tester.clear_entries(*my_lsu); @@ -468,7 +470,7 @@ void runTest(int argc, char **argv) { root_node->getChild("cpu.core0.execute.iq1") ->getResourceAs(); olympia::IssueQueueTester issuequeue_tester; - cls.runSimulator(&sim, 6); + cls.runSimulator(&sim, 8); issuequeue_tester.test_dependent_integer_first_instruction(*my_issuequeue); lsu_tester.test_dependent_lsu_instruction(*my_lsu); lsu_tester.clear_entries(*my_lsu); diff --git a/test/core/rename/test_cores/test_medium_core_full.yaml b/test/core/rename/test_cores/test_medium_core_full.yaml index 85f39c74..ba3c5c0f 100644 --- a/test/core/rename/test_cores/test_medium_core_full.yaml +++ b/test/core/rename/test_cores/test_medium_core_full.yaml @@ -6,6 +6,8 @@ top.cpu.core0: fetch.params.num_to_fetch: 3 + icache.params.l1_always_hit: true + icache.params.cache_latency: 0 decode.params.num_to_decode: 3 rename.params.num_to_rename: 3 dispatch.params.num_to_dispatch: 3 @@ -19,12 +21,12 @@ top.cpu.core0.extension.core_extensions: ["int", "mul", "i2f", "cmov"], ["int", "div"], ["int"], - ["float", "faddsub", "fmac"], + ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"] ] issue_queue_to_pipe_map: - [ + [ ["0"], ["1", "2"], ["3", "4"], diff --git a/test/core/rename/test_cores/test_small_core_full.yaml b/test/core/rename/test_cores/test_small_core_full.yaml index 20feb903..4a947668 100644 --- a/test/core/rename/test_cores/test_small_core_full.yaml +++ b/test/core/rename/test_cores/test_small_core_full.yaml @@ -4,6 +4,8 @@ top.cpu.core0: fetch.params.num_to_fetch: 2 + icache.params.l1_always_hit: true + icache.params.cache_latency: 0 decode.params.num_to_decode: 2 rename.params.num_to_rename: 2 dispatch.params.num_to_dispatch: 2 @@ -19,11 +21,11 @@ top.cpu.core0.extension.core_extensions: pipelines: [ ["int", "mul", "i2f", "cmov", "div"], - ["float", "faddsub", "fmac", "f2i"], + ["float", "faddsub", "fmac", "f2i"], ["br"] ] issue_queue_to_pipe_map: - [ + [ ["0"], ["1"], ["2"] From 4dee5066b074233f9151041f851393a1184f80d0 Mon Sep 17 00:00:00 2001 From: Daniel Bone Date: Mon, 12 Feb 2024 12:21:20 +0000 Subject: [PATCH 04/14] Fix LSU test accounting for extra ICache latency --- test/core/lsu/Lsu_test.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/core/lsu/Lsu_test.cpp b/test/core/lsu/Lsu_test.cpp index def392ec..02f2f261 100644 --- a/test/core/lsu/Lsu_test.cpp +++ b/test/core/lsu/Lsu_test.cpp @@ -107,7 +107,7 @@ void runTest(int argc, char **argv) olympia::LSU *my_lsu = root_node->getChild("cpu.core0.lsu")->getResourceAs(); olympia::LSUTester lsupipe_tester; lsupipe_tester.test_pipeline_stages(*my_lsu); - cls.runSimulator(&sim, 7); + cls.runSimulator(&sim, 9); lsupipe_tester.test_inst_issue(*my_lsu, 2); // Loads operand dependency meet cls.runSimulator(&sim, 52); lsupipe_tester.test_replay_issue_abort(*my_lsu, 2); // Loads operand dependency meet From 9c77264606dc5b7cc2657c5562a880946b71b46a Mon Sep 17 00:00:00 2001 From: Daniel Bone Date: Mon, 12 Feb 2024 14:33:22 +0000 Subject: [PATCH 05/14] Fix L2Cache tests. Change L2+MSS to use credit instead of ack --- core/CPUTopology.cpp | 12 ++-- core/DCache.cpp | 8 +-- core/DCache.hpp | 4 +- core/ICache.cpp | 6 +- core/ICache.hpp | 4 +- mss/BIU.cpp | 29 +++----- mss/BIU.hpp | 20 ++---- mss/L2Cache.cpp | 45 +++++------- mss/L2Cache.hpp | 34 +++------ test/core/icache/ICache_test.cpp | 2 +- test/core/l2cache/BIUSinkUnit.hpp | 8 +-- test/core/l2cache/L2Cache_test.cpp | 12 ++-- test/core/l2cache/L2SourceUnit.hpp | 23 +++--- .../expected_output/hit_case.out.EXPECTED | 70 +++++++++---------- .../single_access.out.EXPECTED | 46 ++++++------ 15 files changed, 136 insertions(+), 187 deletions(-) diff --git a/core/CPUTopology.cpp b/core/CPUTopology.cpp index 9829a431..3cc5af74 100644 --- a/core/CPUTopology.cpp +++ b/core/CPUTopology.cpp @@ -233,8 +233,8 @@ olympia::CoreTopologySimple::CoreTopologySimple(){ "cpu.core*.l2cache.ports.in_dcache_l2cache_req" }, { - "cpu.core*.dcache.ports.in_l2cache_ack", - "cpu.core*.l2cache.ports.out_l2cache_dcache_ack" + "cpu.core*.dcache.ports.in_l2cache_credits", + "cpu.core*.l2cache.ports.out_l2cache_dcache_credits" }, { "cpu.core*.dcache.ports.in_l2cache_resp", @@ -245,8 +245,8 @@ olympia::CoreTopologySimple::CoreTopologySimple(){ "cpu.core*.l2cache.ports.in_icache_l2cache_req" }, { - "cpu.core*.icache.ports.in_l2cache_ack", - "cpu.core*.l2cache.ports.out_l2cache_icache_ack" + "cpu.core*.icache.ports.in_l2cache_credits", + "cpu.core*.l2cache.ports.out_l2cache_icache_credits" }, { "cpu.core*.icache.ports.in_l2cache_resp", @@ -257,8 +257,8 @@ olympia::CoreTopologySimple::CoreTopologySimple(){ "cpu.core*.biu.ports.in_biu_req" }, { - "cpu.core*.biu.ports.out_biu_ack", - "cpu.core*.l2cache.ports.in_biu_l2cache_ack" + "cpu.core*.biu.ports.out_biu_credits", + "cpu.core*.l2cache.ports.in_biu_l2cache_credits" }, { "cpu.core*.biu.ports.out_biu_resp", diff --git a/core/DCache.cpp b/core/DCache.cpp index af8f0e37..e803108d 100644 --- a/core/DCache.cpp +++ b/core/DCache.cpp @@ -11,8 +11,8 @@ namespace olympia { in_lsu_lookup_req_.registerConsumerHandler (CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getInstsFromLSU_, MemoryAccessInfoPtr)); - in_l2cache_ack_.registerConsumerHandler - (CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getAckFromL2Cache_, uint32_t)); + in_l2cache_credits_.registerConsumerHandler + (CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getCreditsFromL2Cache_, uint32_t)); in_l2cache_resp_.registerConsumerHandler (CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getRespFromL2Cache_, MemoryAccessInfoPtr)); @@ -99,13 +99,13 @@ namespace olympia { busy_ = false; } - void DCache::getAckFromL2Cache_(const uint32_t &ack) { + void DCache::getCreditsFromL2Cache_(const uint32_t &ack) { // When DCache sends the request to L2Cache for a miss, // This bool will be set to false, and Dcache should wait for ack from // L2Cache notifying DCache that there is space in it's dcache request buffer // // Set it to true so that the following misses from DCache can be sent out to L2Cache. - dcache_l2cache_credits_ = ack; + dcache_l2cache_credits_ += ack; } } diff --git a/core/DCache.hpp b/core/DCache.hpp index e5982cbd..269d9ce0 100644 --- a/core/DCache.hpp +++ b/core/DCache.hpp @@ -38,7 +38,7 @@ namespace olympia void getInstsFromLSU_(const MemoryAccessInfoPtr & memory_access_info_ptr); - void getAckFromL2Cache_(const uint32_t & ack); + void getCreditsFromL2Cache_(const uint32_t &); void getRespFromL2Cache_(const MemoryAccessInfoPtr & memory_access_info_ptr); @@ -59,7 +59,7 @@ namespace olympia sparta::DataInPort in_lsu_lookup_req_{&unit_port_set_, "in_lsu_lookup_req", 0}; - sparta::DataInPort in_l2cache_ack_{&unit_port_set_, "in_l2cache_ack", 1}; + sparta::DataInPort in_l2cache_credits_{&unit_port_set_, "in_l2cache_credits", 1}; sparta::DataInPort in_l2cache_resp_{&unit_port_set_, "in_l2cache_resp", 1}; diff --git a/core/ICache.cpp b/core/ICache.cpp index 05ef2349..da338783 100644 --- a/core/ICache.cpp +++ b/core/ICache.cpp @@ -27,8 +27,8 @@ namespace olympia { in_fetch_req_.registerConsumerHandler (CREATE_SPARTA_HANDLER_WITH_DATA(ICache, getRequestFromFetch_, MemoryAccessInfoPtr)); - in_l2cache_ack_.registerConsumerHandler - (CREATE_SPARTA_HANDLER_WITH_DATA(ICache, getAckFromL2Cache_, uint32_t)); + in_l2cache_credits_.registerConsumerHandler + (CREATE_SPARTA_HANDLER_WITH_DATA(ICache, getCreditsFromL2Cache_, uint32_t)); in_l2cache_resp_.registerConsumerHandler (CREATE_SPARTA_HANDLER_WITH_DATA(ICache, getRespFromL2Cache_, MemoryAccessInfoPtr)); @@ -191,7 +191,7 @@ namespace olympia { } } - void ICache::getAckFromL2Cache_(const uint32_t &ack) + void ICache::getCreditsFromL2Cache_(const uint32_t &ack) { l2cache_credits_ += ack; if (!miss_queue_.empty()) { diff --git a/core/ICache.hpp b/core/ICache.hpp index 869edd86..ed18b962 100644 --- a/core/ICache.hpp +++ b/core/ICache.hpp @@ -65,7 +65,7 @@ namespace olympia // Callbacks void getRequestFromFetch_(const MemoryAccessInfoPtr &); - void getAckFromL2Cache_(const uint32_t &); + void getCreditsFromL2Cache_(const uint32_t &); void getRespFromL2Cache_(const MemoryAccessInfoPtr &); using L1Handle = CacheFuncModel::Handle; @@ -92,7 +92,7 @@ namespace olympia sparta::DataInPort in_fetch_req_{&unit_port_set_, "in_fetch_req", 1}; - sparta::DataInPort in_l2cache_ack_{&unit_port_set_, "in_l2cache_ack", 1}; + sparta::DataInPort in_l2cache_credits_{&unit_port_set_, "in_l2cache_credits", 1}; sparta::DataInPort in_l2cache_resp_{&unit_port_set_, "in_l2cache_resp", 1}; diff --git a/mss/BIU.cpp b/mss/BIU.cpp index d1e2fb7f..47aea104 100644 --- a/mss/BIU.cpp +++ b/mss/BIU.cpp @@ -28,7 +28,7 @@ namespace olympia_mss sparta::StartupEvent(node, CREATE_SPARTA_HANDLER(BIU, sendInitialCredits_)); ILOG("BIU construct: #" << node->getGroupIdx()); - ev_handle_mss_ack_ >> ev_handle_biu_req_ >> ev_handle_biu_l2cache_ack_; + ev_handle_mss_ack_ >> ev_handle_biu_req_; } @@ -38,7 +38,7 @@ namespace olympia_mss // Sending Initial credits to L2Cache void BIU::sendInitialCredits_() { - out_biu_ack_.send(biu_req_queue_size_); + out_biu_credits_.send(biu_req_queue_size_); ILOG("Sending initial credits to L2Cache : " << biu_req_queue_size_); } @@ -66,28 +66,24 @@ namespace olympia_mss } // Handle BIU request - void BIU::handle_BIU_Req_() + void BIU::handleBIUReq_() { biu_busy_ = true; out_mss_req_sync_.send(biu_req_queue_.front(), biu_latency_); - if (biu_req_queue_.size() < biu_req_queue_size_) { - // Send out the ack to L2Cache if there is space in biu_req_queue_ - ev_handle_biu_l2cache_ack_.schedule(sparta::Clock::Cycle(0)); - } - ILOG("BIU request is sent to MSS!"); } // Handle MSS Ack - void BIU::handle_MSS_Ack_() + void BIU::handleMSSAck_() { out_biu_resp_.send(biu_req_queue_.front(), biu_latency_); biu_req_queue_.pop_front(); - // Send out the ack to L2Cache through , we just created space in biu_req_queue_ - ev_handle_biu_l2cache_ack_.schedule(sparta::Clock::Cycle(0)); + // Send out a credit to L2Cache, as we just created space in biu_req_queue_ + out_biu_credits_.send(1); + biu_busy_ = false; // Schedule BIU request handling event only when: @@ -96,7 +92,7 @@ namespace olympia_mss ev_handle_biu_req_.schedule(sparta::Clock::Cycle(0)); } - ILOG("MSS Ack is sent to LSU!"); + ILOG("BIU response sent back!"); } // Receive MSS access acknowledge @@ -114,15 +110,6 @@ namespace olympia_mss sparta_assert(false, "MSS is NOT done!"); } - // Handle ack backto L2Cache - void BIU::handle_BIU_L2Cache_Ack_() - { - uint32_t available_slots = biu_req_queue_size_ - biu_req_queue_.size(); - out_biu_ack_.send(available_slots); - - ILOG("BIU->L2Cache : Ack is sent."); - } - //////////////////////////////////////////////////////////////////////////////// // Regular Function/Subroutine Call //////////////////////////////////////////////////////////////////////////////// diff --git a/mss/BIU.hpp b/mss/BIU.hpp index 55a84acd..ca7aa5ad 100644 --- a/mss/BIU.hpp +++ b/mss/BIU.hpp @@ -67,8 +67,8 @@ namespace olympia_mss // Output Ports //////////////////////////////////////////////////////////////////////////////// - sparta::DataOutPort out_biu_ack_ - {&unit_port_set_, "out_biu_ack"}; + sparta::DataOutPort out_biu_credits_ + {&unit_port_set_, "out_biu_credits"}; sparta::DataOutPort out_biu_resp_ {&unit_port_set_, "out_biu_resp"}; @@ -96,16 +96,11 @@ namespace olympia_mss // Event to handle BIU request from L2Cache sparta::UniqueEvent<> ev_handle_biu_req_ - {&unit_event_set_, "handle_biu_req", CREATE_SPARTA_HANDLER(BIU, handle_BIU_Req_)}; + {&unit_event_set_, "handle_biu_req", CREATE_SPARTA_HANDLER(BIU, handleBIUReq_)}; // Event to handle MSS Ack sparta::UniqueEvent<> ev_handle_mss_ack_ - {&unit_event_set_, "handle_mss_ack", CREATE_SPARTA_HANDLER(BIU, handle_MSS_Ack_)}; - - // Event to handleBIU ack for L2Cache - sparta::UniqueEvent<> ev_handle_biu_l2cache_ack_ - {&unit_event_set_, "ev_handle_biu_l2cache_ack", CREATE_SPARTA_HANDLER(BIU, handle_BIU_L2Cache_Ack_)}; - + {&unit_event_set_, "handle_mss_ack", CREATE_SPARTA_HANDLER(BIU, handleMSSAck_)}; //////////////////////////////////////////////////////////////////////////////// // Callbacks @@ -115,13 +110,10 @@ namespace olympia_mss void receiveReqFromL2Cache_(const olympia::MemoryAccessInfoPtr &); // Handle BIU request - void handle_BIU_Req_(); + void handleBIUReq_(); // Handle MSS Ack - void handle_MSS_Ack_(); - - // Handle ack backto L2Cache - void handle_BIU_L2Cache_Ack_(); + void handleMSSAck_(); // Receive MSS access acknowledge // Q: Does the argument list has to be "const DataType &" ? diff --git a/mss/L2Cache.cpp b/mss/L2Cache.cpp index e2fc24ae..b04aa2e7 100644 --- a/mss/L2Cache.cpp +++ b/mss/L2Cache.cpp @@ -96,8 +96,8 @@ namespace olympia_mss in_biu_resp_.registerConsumerHandler (CREATE_SPARTA_HANDLER_WITH_DATA(L2Cache, getRespFromBIU_, olympia::MemoryAccessInfoPtr)); - in_biu_ack_.registerConsumerHandler - (CREATE_SPARTA_HANDLER_WITH_DATA(L2Cache, getAckFromBIU_, uint32_t)); + in_biu_credits_.registerConsumerHandler + (CREATE_SPARTA_HANDLER_WITH_DATA(L2Cache, getCreditsFromBIU_, uint32_t)); // Pipeline collection config l2cache_pipeline_.enableCollection(node); @@ -134,12 +134,12 @@ namespace olympia_mss // Sending Initial credits to I/D-Cache void L2Cache::sendInitialCredits_() { if (is_icache_connected_) { - out_l2cache_icache_ack_.send(icache_req_queue_size_); + out_l2cache_icache_credits_.send(icache_req_queue_size_); ILOG("Sending initial credits to ICache : " << icache_req_queue_size_); } if (is_dcache_connected_) { - out_l2cache_dcache_ack_.send(dcache_req_queue_size_); + out_l2cache_dcache_credits_.send(dcache_req_queue_size_); ILOG("Sending initial credits to DCache : " << dcache_req_queue_size_); } } @@ -184,16 +184,16 @@ namespace olympia_mss } } - // Handle BIU ack - void L2Cache::getAckFromBIU_(const uint32_t & ack) { + // Handle BIU Credits + void L2Cache::getCreditsFromBIU_(const uint32_t & credits) { // Update the biu credits - l2cache_biu_credits_ = ack; + l2cache_biu_credits_ += credits; // Kickstart the pipeline issueing ev_issue_req_.schedule(1); - ILOG("Ack received from BIU on the port : Current BIU credit available = " << l2cache_biu_credits_); + ILOG("Credits received from BIU on the port : Current BIU credit available = " << l2cache_biu_credits_); } // Handle L2Cache request from DCache @@ -236,25 +236,6 @@ namespace olympia_mss } } - // Returning ack to DCache - void L2Cache::handle_L2Cache_DCache_Ack_() { - uint32_t available_slots = dcache_req_queue_size_ - dcache_req_queue_.size(); - out_l2cache_dcache_ack_.send(available_slots); - ++num_acks_to_dcache_; - - ILOG("L2Cache->DCache : Ack is sent."); - } - - // Returning resp to ICache - void L2Cache::handle_L2Cache_ICache_Ack_() { - // uint32_t available_slots = icache_req_queue_size_ - icache_req_queue_.size(); - // out_l2cache_icache_ack_.send(available_slots); - out_l2cache_icache_ack_.send(1); - ++num_acks_to_icache_; - - ILOG("L2Cache->ICache : Ack is sent."); - } - // Returning resp to DCache void L2Cache::handle_L2Cache_DCache_Resp_() { out_l2cache_dcache_resp_.send(dcache_resp_queue_.front()); @@ -338,7 +319,10 @@ namespace olympia_mss icache_req_queue_.erase(icache_req_queue_.begin()); // Send out the ack to ICache for credit management - ev_handle_l2cache_icache_ack_.schedule(sparta::Clock::Cycle(1)); + out_l2cache_icache_credits_.send(1, 1); + ILOG("L2Cache->ICache : Credit is sent."); + ++num_acks_to_icache_; + } else if (arbitration_winner == Channel::DCACHE) { @@ -354,7 +338,10 @@ namespace olympia_mss dcache_req_queue_.erase(dcache_req_queue_.begin()); // Send out the ack to DCache for credit management - ev_handle_l2cache_dcache_ack_.schedule(sparta::Clock::Cycle(1)); + out_l2cache_dcache_credits_.send(1, 1); + ILOG("L2Cache->DCache : Credit is sent."); + ++num_acks_to_dcache_; + } else if (arbitration_winner == Channel::NO_ACCESS) { // Schedule a ev_create_req_ event again to see if the the new request diff --git a/mss/L2Cache.hpp b/mss/L2Cache.hpp index 22da8f99..f367d373 100644 --- a/mss/L2Cache.hpp +++ b/mss/L2Cache.hpp @@ -107,8 +107,8 @@ namespace olympia_mss sparta::DataInPort in_biu_resp_ {&unit_port_set_, "in_biu_l2cache_resp", 1}; - sparta::DataInPort in_biu_ack_ - {&unit_port_set_, "in_biu_l2cache_ack", 1}; + sparta::DataInPort in_biu_credits_ + {&unit_port_set_, "in_biu_l2cache_credits", 1}; //////////////////////////////////////////////////////////////////////////////// @@ -124,11 +124,11 @@ namespace olympia_mss sparta::DataOutPort out_l2cache_dcache_resp_ {&unit_port_set_, "out_l2cache_dcache_resp"}; - sparta::DataOutPort out_l2cache_icache_ack_ - {&unit_port_set_, "out_l2cache_icache_ack"}; + sparta::DataOutPort out_l2cache_icache_credits_ + {&unit_port_set_, "out_l2cache_icache_credits"}; - sparta::DataOutPort out_l2cache_dcache_ack_ - {&unit_port_set_, "out_l2cache_dcache_ack"}; + sparta::DataOutPort out_l2cache_dcache_credits_ + {&unit_port_set_, "out_l2cache_dcache_credits"}; //////////////////////////////////////////////////////////////////////////////// @@ -248,14 +248,6 @@ namespace olympia_mss sparta::UniqueEvent<> ev_handle_biu_l2cache_resp_ {&unit_event_set_, "ev_handle_biu_l2cache_resp", CREATE_SPARTA_HANDLER(L2Cache, handle_BIU_L2Cache_Resp_)}; - // Event to handle L2Cache ack for ICache - sparta::UniqueEvent<> ev_handle_l2cache_icache_ack_ - {&unit_event_set_, "ev_handle_l2cache_icache_ack", CREATE_SPARTA_HANDLER(L2Cache, handle_L2Cache_ICache_Ack_)}; - - // Event to handle L2Cache ack for DCache - sparta::UniqueEvent<> ev_handle_l2cache_dcache_ack_ - {&unit_event_set_, "ev_handle_l2cache_dcache_ack", CREATE_SPARTA_HANDLER(L2Cache, handle_L2Cache_DCache_Ack_)}; - // Event to create request for pipeline and feed it to the pipeline_req_queue_ sparta::UniqueEvent ev_create_req_ {&unit_event_set_, "create_req", CREATE_SPARTA_HANDLER(L2Cache, create_Req_)}; @@ -277,8 +269,8 @@ namespace olympia_mss // Receive BIU access Response void getRespFromBIU_(const olympia::MemoryAccessInfoPtr &); - // Receive BIU ack Response - void getAckFromBIU_(const uint32_t &); + // Receive BIU credits Response + void getCreditsFromBIU_(const uint32_t &); // Handle L2Cache request from DCache void handle_DCache_L2Cache_Req_(); @@ -289,18 +281,12 @@ namespace olympia_mss // Handle L2Cache request to BIU void handle_L2Cache_BIU_Req_(); - // Handle L2Cahe resp for ICache + // Handle L2Cache resp for ICache void handle_L2Cache_ICache_Resp_(); - // Handle L2Cahe resp for DCache + // Handle L2Cache resp for DCache void handle_L2Cache_DCache_Resp_(); - // Handle L2Cahe ack for ICache - void handle_L2Cache_ICache_Ack_(); - - // Handle L2Cahe ack for DCache - void handle_L2Cache_DCache_Ack_(); - // Handle BIU resp to L2Cache void handle_BIU_L2Cache_Resp_(); diff --git a/test/core/icache/ICache_test.cpp b/test/core/icache/ICache_test.cpp index bac017fa..790fe3df 100644 --- a/test/core/icache/ICache_test.cpp +++ b/test/core/icache/ICache_test.cpp @@ -81,7 +81,7 @@ class ICacheSim : public sparta::app::Simulation{ root_node->getChildAs("sink.ports.in_icache_req")); sparta::bind(root_node->getChildAs("icache.ports.in_l2cache_resp"), root_node->getChildAs("sink.ports.out_icache_resp")); - sparta::bind(root_node->getChildAs("icache.ports.in_l2cache_ack"), + sparta::bind(root_node->getChildAs("icache.ports.in_l2cache_credits"), root_node->getChildAs("sink.ports.out_icache_credit")); // Bind up checker diff --git a/test/core/l2cache/BIUSinkUnit.hpp b/test/core/l2cache/BIUSinkUnit.hpp index 47e2b044..fe52c3df 100644 --- a/test/core/l2cache/BIUSinkUnit.hpp +++ b/test/core/l2cache/BIUSinkUnit.hpp @@ -43,23 +43,21 @@ namespace l2cache_test // Sending Initial credits to L2Cache void sendInitialCredits_() { uint32_t biu_req_queue_size_ = 32; - out_biu_ack_.send(biu_req_queue_size_); + out_biu_credits_.send(biu_req_queue_size_); ILOG("Sending initial credits to L2Cache : " << biu_req_queue_size_); } void sinkInst_(const olympia::MemoryAccessInfoPtr & mem_access_info_ptr) { ILOG("Instruction: '" << mem_access_info_ptr->getInstPtr() << "' sinked"); - uint32_t biu_req_queue_size_ = 32; - - out_biu_ack_.send(biu_req_queue_size_, sink_latency_); + out_biu_credits_.send(1, sink_latency_); out_biu_resp_.send(mem_access_info_ptr, 2*sink_latency_); } sparta::DataInPort in_biu_req_ {&unit_port_set_, "in_biu_req", sparta::SchedulingPhase::Tick, 1}; sparta::DataOutPort out_biu_resp_ {&unit_port_set_, "out_biu_resp"}; - sparta::DataOutPort out_biu_ack_ {&unit_port_set_, "out_biu_ack"}; + sparta::DataOutPort out_biu_credits_ {&unit_port_set_, "out_biu_credits"}; std::string purpose_; sparta::Clock::Cycle sink_latency_; diff --git a/test/core/l2cache/L2Cache_test.cpp b/test/core/l2cache/L2Cache_test.cpp index 76a6a169..dee33a85 100644 --- a/test/core/l2cache/L2Cache_test.cpp +++ b/test/core/l2cache/L2Cache_test.cpp @@ -134,22 +134,22 @@ class L2CacheSim : public sparta::app::Simulation root_node->getChildAs("l2cache.ports.in_dcache_l2cache_req")); sparta::bind(root_node->getChildAs("dcache.ports.in_source_resp"), root_node->getChildAs("l2cache.ports.out_l2cache_dcache_resp")); - sparta::bind(root_node->getChildAs("dcache.ports.in_source_ack"), - root_node->getChildAs("l2cache.ports.out_l2cache_dcache_ack")); + sparta::bind(root_node->getChildAs("dcache.ports.in_source_credits"), + root_node->getChildAs("l2cache.ports.out_l2cache_dcache_credits")); sparta::bind(root_node->getChildAs("icache.ports.out_source_req"), root_node->getChildAs("l2cache.ports.in_icache_l2cache_req")); sparta::bind(root_node->getChildAs("icache.ports.in_source_resp"), root_node->getChildAs("l2cache.ports.out_l2cache_icache_resp")); - sparta::bind(root_node->getChildAs("icache.ports.in_source_ack"), - root_node->getChildAs("l2cache.ports.out_l2cache_icache_ack")); + sparta::bind(root_node->getChildAs("icache.ports.in_source_credits"), + root_node->getChildAs("l2cache.ports.out_l2cache_icache_credits")); sparta::bind(root_node->getChildAs("biu.ports.in_biu_req"), root_node->getChildAs("l2cache.ports.out_l2cache_biu_req")); sparta::bind(root_node->getChildAs("biu.ports.out_biu_resp"), root_node->getChildAs("l2cache.ports.in_biu_l2cache_resp")); - sparta::bind(root_node->getChildAs("biu.ports.out_biu_ack"), - root_node->getChildAs("l2cache.ports.in_biu_l2cache_ack")); + sparta::bind(root_node->getChildAs("biu.ports.out_biu_credits"), + root_node->getChildAs("l2cache.ports.in_biu_l2cache_credits")); } // Allocators. Last thing to delete std::unique_ptr allocators_tn_; diff --git a/test/core/l2cache/L2SourceUnit.hpp b/test/core/l2cache/L2SourceUnit.hpp index 05aab52f..64c87c81 100644 --- a/test/core/l2cache/L2SourceUnit.hpp +++ b/test/core/l2cache/L2SourceUnit.hpp @@ -43,8 +43,8 @@ namespace l2cache_test in_source_resp_.registerConsumerHandler (CREATE_SPARTA_HANDLER_WITH_DATA(L2SourceUnit, ReceiveInst_, olympia::MemoryAccessInfoPtr)); - in_source_ack_.registerConsumerHandler - (CREATE_SPARTA_HANDLER_WITH_DATA(L2SourceUnit, ReceiveAck_, uint32_t)); + in_source_credits_.registerConsumerHandler + (CREATE_SPARTA_HANDLER_WITH_DATA(L2SourceUnit, ReceiveCredits_, uint32_t)); if(params->input_file != "") { inst_generator_ = olympia::InstGenerator::createGenerator(mavis_facade_, params->input_file, false); @@ -58,7 +58,7 @@ namespace l2cache_test void onStartingTeardown_() override { sparta_assert(unit_enable_ == true && pending_reqs_ == 0, "pending_reqs remaining in the L2SourceUnit"); - sparta_assert(unit_enable_ == true && pending_acks_ == 0, "pending_acks remaining in the L2SourceUnit"); + sparta_assert(unit_enable_ == true && pending_credits_ == 0, "pending_credits remaining in the L2SourceUnit"); } private: @@ -88,7 +88,7 @@ namespace l2cache_test ILOG("Instruction: '" << req_inst_queue_.front()->getInstPtr() << "' Requested"); pending_reqs_++; - pending_acks_++; + pending_credits_++; out_source_req_.send(req_inst_queue_.front()); req_inst_queue_.erase(req_inst_queue_.begin()); @@ -99,18 +99,17 @@ namespace l2cache_test ILOG("Instruction: '" << mem_info_ptr->getInstPtr() << "' Received"); } - void ReceiveAck_(const uint32_t & ack) { - pending_acks_--; - ILOG("Ack: '" << ack << "' Received"); + void ReceiveCredits_(const uint32_t & credits) { + pending_credits_--; + ILOG("Ack: '" << credits << "' Received"); } - sparta::DataInPort in_source_resp_ {&unit_port_set_, "in_source_resp", + sparta::DataInPort in_source_resp_ {&unit_port_set_, "in_source_resp", sparta::SchedulingPhase::Tick, 1}; - sparta::DataInPort in_source_ack_ {&unit_port_set_, "in_source_ack"}; + sparta::DataInPort in_source_credits_ {&unit_port_set_, "in_source_credits"}; + sparta::DataOutPort out_source_req_ {&unit_port_set_, "out_source_req"}; - sparta::DataOutPort out_source_req_ {&unit_port_set_, "out_source_req"}; - - uint32_t pending_acks_ = 1; + uint32_t pending_credits_ = 1; uint32_t pending_reqs_ = 0; uint32_t unique_id_ = 0; diff --git a/test/core/l2cache/expected_output/hit_case.out.EXPECTED b/test/core/l2cache/expected_output/hit_case.out.EXPECTED index c47a5eac..6f77671c 100644 --- a/test/core/l2cache/expected_output/hit_case.out.EXPECTED +++ b/test/core/l2cache/expected_output/hit_case.out.EXPECTED @@ -3,43 +3,43 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Thursday Thu Feb 8 10:29:35 2024 -#Elapsed: 0.024913s +#Start: Monday Mon Feb 12 14:22:32 2024 +#Elapsed: 0.002725s {0000000000 00000000 top.l2cache info} L2Cache: L2Cache construct: #4294967295 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to ICache : 8 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to DCache : 8 {0000000000 00000000 top.biu info} sendInitialCredits_: Sending initial credits to L2Cache : 32 -{0000000000 00000000 top.icache info} ReceiveAck_: Ack: '8' Received -{0000000000 00000000 top.dcache info} ReceiveAck_: Ack: '8' Received -{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Requested -{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Requested -{0000000001 00000001 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 +{0000000000 00000000 top.icache info} ReceiveCredits_: Ack: '8' Received +{0000000000 00000000 top.dcache info} ReceiveCredits_: Ack: '8' Received +{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' ' Requested +{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' ' Requested +{0000000001 00000001 top.l2cache info} getCreditsFromBIU_: Credits received from BIU on the port : Current BIU credit available = 32 {0000000001 00000001 top.l2cache info} getReqFromDCache_: Request received from DCache on the port {0000000001 00000001 top.l2cache info} appendDCacheReqQueue_: Append DCache->L2Cache request queue! {0000000001 00000001 top.l2cache info} getReqFromICache_: Request received from ICache on the port {0000000001 00000001 top.l2cache info} appendICacheReqQueue_: Append ICache->L2Cache request queue! {0000000001 00000001 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - ICache {0000000001 00000001 top.l2cache info} create_Req_: ICache request is sent to Pipeline_req_Q! -{0000000002 00000002 top.icache info} ReceiveAck_: Ack: '8' Received -{0000000002 00000002 top.l2cache info} handle_L2Cache_ICache_Ack_: L2Cache->ICache : Ack is sent. +{0000000001 00000001 top.l2cache info} create_Req_: L2Cache->ICache : Credit is sent. +{0000000002 00000002 top.icache info} ReceiveCredits_: Ack: '1' Received {0000000002 00000002 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : ICACHE {0000000002 00000002 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - DCache {0000000002 00000002 top.l2cache info} create_Req_: DCache request is sent to Pipeline_req_Q! -{0000000003 00000003 top.dcache info} ReceiveAck_: Ack: '8' Received -{0000000003 00000003 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. +{0000000002 00000002 top.l2cache info} create_Req_: L2Cache->DCache : Credit is sent. +{0000000003 00000003 top.dcache info} ReceiveCredits_: Ack: '1' Received {0000000003 00000003 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' {0000000011 00000011 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' {0000000012 00000012 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' {0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000012 00000012 top.l2cache info} appendBIUReqQueue_: Append L2Cache->BIU req queue {0000000012 00000012 top.l2cache info} handle_L2Cache_BIU_Req_: L2Cache Request sent to BIU : Current BIU credit available = 31 -{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' sinked -{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' ' sinked +{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' {0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ -{0000000024 00000024 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 +{0000000024 00000024 top.l2cache info} getCreditsFromBIU_: Credits received from BIU on the port : Current BIU credit available = 32 {0000000034 00000034 top.l2cache info} getRespFromBIU_: Response received from BIU on the port {0000000034 00000034 top.l2cache info} appendBIURespQueue_: Append BIU->L2Cache resp queue! {0000000034 00000034 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU @@ -48,44 +48,44 @@ {0000000035 00000035 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU {0000000035 00000035 top.l2cache info} create_Req_: Request found in miss_pending_buffer_ with SrcUnit : DCACHE {0000000036 00000036 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : BIU -{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' {0000000044 00000044 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef {0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Reload Complete: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' {0000000045 00000045 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' {0000000045 00000045 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000045 00000045 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! -{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Received -{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' ' Received +{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' {0000000046 00000046 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000046 00000046 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! -{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Received -{0000000050 00000050 top.dcache info} req_inst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' ' Requested -{0000000050 00000050 top.icache info} req_inst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' ' Requested +{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' ' Received +{0000000050 00000050 top.dcache info} req_inst_: Instruction: 'uid: 1 BEFORE_FETCH 0 pid: 2 'lw 5,3,4' ' Requested +{0000000050 00000050 top.icache info} req_inst_: Instruction: 'uid: 1 BEFORE_FETCH 0 pid: 2 'lw 5,3,4' ' Requested {0000000051 00000051 top.l2cache info} getReqFromDCache_: Request received from DCache on the port {0000000051 00000051 top.l2cache info} appendDCacheReqQueue_: Append DCache->L2Cache request queue! {0000000051 00000051 top.l2cache info} getReqFromICache_: Request received from ICache on the port {0000000051 00000051 top.l2cache info} appendICacheReqQueue_: Append ICache->L2Cache request queue! {0000000051 00000051 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - ICache {0000000051 00000051 top.l2cache info} create_Req_: ICache request is sent to Pipeline_req_Q! -{0000000052 00000052 top.icache info} ReceiveAck_: Ack: '8' Received -{0000000052 00000052 top.l2cache info} handle_L2Cache_ICache_Ack_: L2Cache->ICache : Ack is sent. +{0000000051 00000051 top.l2cache info} create_Req_: L2Cache->ICache : Credit is sent. +{0000000052 00000052 top.icache info} ReceiveCredits_: Ack: '1' Received {0000000052 00000052 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : ICACHE {0000000052 00000052 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - DCache {0000000052 00000052 top.l2cache info} create_Req_: DCache request is sent to Pipeline_req_Q! -{0000000053 00000053 top.dcache info} ReceiveAck_: Ack: '8' Received -{0000000053 00000053 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. +{0000000052 00000052 top.l2cache info} create_Req_: L2Cache->DCache : Credit is sent. +{0000000053 00000053 top.dcache info} ReceiveCredits_: Ack: '1' Received {0000000053 00000053 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000061 00000061 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' +{0000000061 00000061 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 1 BEFORE_FETCH 0 pid: 2 'lw 5,3,4' {0000000061 00000061 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000062 00000062 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' +{0000000062 00000062 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 1 BEFORE_FETCH 0 pid: 2 'lw 5,3,4' {0000000062 00000062 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000062 00000062 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' +{0000000062 00000062 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 1 BEFORE_FETCH 0 pid: 2 'lw 5,3,4' {0000000062 00000062 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000062 00000062 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! -{0000000063 00000063 top.icache info} ReceiveInst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' ' Received -{0000000063 00000063 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' +{0000000063 00000063 top.icache info} ReceiveInst_: Instruction: 'uid: 1 BEFORE_FETCH 0 pid: 2 'lw 5,3,4' ' Received +{0000000063 00000063 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 1 BEFORE_FETCH 0 pid: 2 'lw 5,3,4' {0000000063 00000063 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000063 00000063 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! -{0000000064 00000064 top.dcache info} ReceiveInst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 'lw 5,3,4' ' Received +{0000000064 00000064 top.dcache info} ReceiveInst_: Instruction: 'uid: 1 BEFORE_FETCH 0 pid: 2 'lw 5,3,4' ' Received diff --git a/test/core/l2cache/expected_output/single_access.out.EXPECTED b/test/core/l2cache/expected_output/single_access.out.EXPECTED index d7e055da..eb45aa14 100644 --- a/test/core/l2cache/expected_output/single_access.out.EXPECTED +++ b/test/core/l2cache/expected_output/single_access.out.EXPECTED @@ -3,43 +3,43 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Thursday Thu Feb 8 10:29:35 2024 -#Elapsed: 0.031446s +#Start: Monday Mon Feb 12 14:21:20 2024 +#Elapsed: 0.003237s {0000000000 00000000 top.l2cache info} L2Cache: L2Cache construct: #4294967295 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to ICache : 8 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to DCache : 8 {0000000000 00000000 top.biu info} sendInitialCredits_: Sending initial credits to L2Cache : 32 -{0000000000 00000000 top.icache info} ReceiveAck_: Ack: '8' Received -{0000000000 00000000 top.dcache info} ReceiveAck_: Ack: '8' Received -{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Requested -{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Requested -{0000000001 00000001 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 +{0000000000 00000000 top.icache info} ReceiveCredits_: Ack: '8' Received +{0000000000 00000000 top.dcache info} ReceiveCredits_: Ack: '8' Received +{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' ' Requested +{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' ' Requested +{0000000001 00000001 top.l2cache info} getCreditsFromBIU_: Credits received from BIU on the port : Current BIU credit available = 32 {0000000001 00000001 top.l2cache info} getReqFromDCache_: Request received from DCache on the port {0000000001 00000001 top.l2cache info} appendDCacheReqQueue_: Append DCache->L2Cache request queue! {0000000001 00000001 top.l2cache info} getReqFromICache_: Request received from ICache on the port {0000000001 00000001 top.l2cache info} appendICacheReqQueue_: Append ICache->L2Cache request queue! {0000000001 00000001 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - ICache {0000000001 00000001 top.l2cache info} create_Req_: ICache request is sent to Pipeline_req_Q! -{0000000002 00000002 top.icache info} ReceiveAck_: Ack: '8' Received -{0000000002 00000002 top.l2cache info} handle_L2Cache_ICache_Ack_: L2Cache->ICache : Ack is sent. +{0000000001 00000001 top.l2cache info} create_Req_: L2Cache->ICache : Credit is sent. +{0000000002 00000002 top.icache info} ReceiveCredits_: Ack: '1' Received {0000000002 00000002 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : ICACHE {0000000002 00000002 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - DCache {0000000002 00000002 top.l2cache info} create_Req_: DCache request is sent to Pipeline_req_Q! -{0000000003 00000003 top.dcache info} ReceiveAck_: Ack: '8' Received -{0000000003 00000003 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. +{0000000002 00000002 top.l2cache info} create_Req_: L2Cache->DCache : Credit is sent. +{0000000003 00000003 top.dcache info} ReceiveCredits_: Ack: '1' Received {0000000003 00000003 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' {0000000011 00000011 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' {0000000012 00000012 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' {0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000012 00000012 top.l2cache info} appendBIUReqQueue_: Append L2Cache->BIU req queue {0000000012 00000012 top.l2cache info} handle_L2Cache_BIU_Req_: L2Cache Request sent to BIU : Current BIU credit available = 31 -{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' sinked -{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' ' sinked +{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' {0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ -{0000000024 00000024 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 +{0000000024 00000024 top.l2cache info} getCreditsFromBIU_: Credits received from BIU on the port : Current BIU credit available = 32 {0000000034 00000034 top.l2cache info} getRespFromBIU_: Response received from BIU on the port {0000000034 00000034 top.l2cache info} appendBIURespQueue_: Append BIU->L2Cache resp queue! {0000000034 00000034 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU @@ -48,16 +48,16 @@ {0000000035 00000035 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU {0000000035 00000035 top.l2cache info} create_Req_: Request found in miss_pending_buffer_ with SrcUnit : DCACHE {0000000036 00000036 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : BIU -{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' {0000000044 00000044 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef {0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Reload Complete: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' {0000000045 00000045 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' {0000000045 00000045 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000045 00000045 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! -{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Received -{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 FETCHED 0 pid: 1 'sw 3' +{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' ' Received +{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' {0000000046 00000046 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000046 00000046 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! -{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 'sw 3' ' Received +{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' ' Received From 7fd5471044e3f6ee80c0071637c6c591c91e7022 Mon Sep 17 00:00:00 2001 From: Daniel Bone Date: Fri, 16 Feb 2024 12:51:44 +0000 Subject: [PATCH 06/14] Add fetch block size, and buffer size parameters to Fetch --- core/Fetch.cpp | 57 ++++++++++++++++++++++++++++++++----------------- core/Fetch.hpp | 46 +++++++++++++++++++++++++++------------ core/ICache.cpp | 2 +- 3 files changed, 70 insertions(+), 35 deletions(-) diff --git a/core/Fetch.cpp b/core/Fetch.cpp index b4124deb..26b81f77 100644 --- a/core/Fetch.cpp +++ b/core/Fetch.cpp @@ -11,6 +11,7 @@ #include "MavisUnit.hpp" #include "OlympiaAllocators.hpp" +#include "sparta/utils/MathUtils.hpp" #include "sparta/utils/LogUtils.hpp" #include "sparta/events/StartupEvent.hpp" @@ -21,10 +22,12 @@ namespace olympia Fetch::Fetch(sparta::TreeNode * node, const FetchParameterSet * p) : sparta::Unit(node), + my_clk_(getClock()), num_insts_to_fetch_(p->num_to_fetch), skip_nonuser_mode_(p->skip_nonuser_mode), - my_clk_(getClock()), - ibuf_capacity_(32), // buffer up instructions read from trace + icache_block_shift_(sparta::utils::floor_log2(p->block_width.getValue())), + ibuf_capacity_(std::ceil(p->block_width / 2)), // buffer up instructions read from trace + fetch_buffer_capacity_(p->fetch_buffer_size), memory_access_allocator_(sparta::notNull(OlympiaAllocators::getOlympiaAllocators(node)) ->memory_access_allocator) { @@ -43,12 +46,16 @@ namespace olympia ev_fetch_insts.reset(new sparta::SingleCycleUniqueEvent<>(&unit_event_set_, "fetch_instruction_data", CREATE_SPARTA_HANDLER(Fetch, fetchInstruction_))); - ev_drive_insts.reset(new sparta::SingleCycleUniqueEvent<>(&unit_event_set_, "drive_instructions_out", - CREATE_SPARTA_HANDLER(Fetch, driveInstructions_))); + ev_send_insts.reset(new sparta::SingleCycleUniqueEvent<>(&unit_event_set_, "send_instructions_out", + CREATE_SPARTA_HANDLER(Fetch, sendInstructions_))); // Schedule a single event to start reading from a trace file sparta::StartupEvent(node, CREATE_SPARTA_HANDLER(Fetch, initialize_)); + // Capture when the simulation is stopped prematurely by the ROB i.e. hitting retire limit + node->getParent()->registerForNotification( + this, "rob_stopped_notif_channel", false /* ROB maybe not be constructed yet */); + } Fetch::~Fetch() {} @@ -85,10 +92,9 @@ namespace olympia if (credits_icache_ == 0 || ibuf_.empty() || fetch_buffer_.size() > fetch_buffer_capacity_) { return; } // Gather instructions going to the same cacheblock - // TODO this should be a constant related to the ICache - const uint32_t icache_block_shift_ = 4; // 16B blocks.. - // TODO instructions which straddle should be placed into the next group - auto different_blocks = [icache_block_shift_](const auto &lhs, const auto &rhs) { + // NOTE: This doesn't deal with instructions straddling the blocks, + // they should be placed into the next group + auto different_blocks = [this](const auto &lhs, const auto &rhs) { return (lhs->getPC() >> icache_block_shift_) != (rhs->getPC() >> icache_block_shift_) || lhs->isTakenBranch() || rhs->isCoF(); @@ -132,7 +138,7 @@ namespace olympia } // Read instructions from the fetch buffer and send them to decode - void Fetch::driveInstructions_() + void Fetch::sendInstructions_() { const uint32_t upper = std::min({credits_inst_queue_, num_insts_to_fetch_, static_cast(fetch_buffer_.size())}); @@ -175,7 +181,7 @@ namespace olympia out_fetch_queue_write_.send(insts_to_send); if (!fetch_buffer_.empty() && credits_inst_queue_ > 0) { - ev_drive_insts->schedule(1); + ev_send_insts->schedule(1); } ev_fetch_insts->schedule(1); @@ -184,15 +190,21 @@ namespace olympia void Fetch::receiveCacheResponse_(const MemoryAccessInfoPtr &response) { + const auto & fetched_insts = response->getFetchGroup(); + sparta_assert(fetched_insts != nullptr, "no instructions set for cache request"); if (response->getCacheState() == MemoryAccessInfo::CacheState::HIT) { + ILOG("Cache hit response recieved for insts: " << fetched_insts); // Mark instructions as fetched - auto & fetched_insts = response->getFetchGroup(); - sparta_assert(fetched_insts != nullptr); for(auto & inst : *fetched_insts) { inst->setStatus(Inst::Status::FETCHED); } + ev_send_insts->schedule(sparta::Clock::Cycle(0)); + } - ev_drive_insts->schedule(sparta::Clock::Cycle(0)); + // Log misses + if (SPARTA_EXPECT_FALSE(info_logger_) && + response->getCacheState() == MemoryAccessInfo::CacheState::MISS) { + ILOG("Cache miss on insts: " << fetched_insts); } } @@ -216,7 +228,7 @@ namespace olympia << ", total decode_credits=" << credits_inst_queue_); // Schedule a fetch event this cycle - ev_drive_insts->schedule(sparta::Clock::Cycle(0)); + ev_send_insts->schedule(sparta::Clock::Cycle(0)); } // Called from FlushManager via in_fetch_flush_redirect_port @@ -250,9 +262,14 @@ namespace olympia // speculative_path_ = false; } + void Fetch::onROBTerminate_(const bool & stopped) + { + rob_stopped_simulation_ = stopped; + } + void Fetch::dumpDebugContent_(std::ostream & output) const { - output << "Fetch Contents" << std::endl; + output << "Fetch Buffer Contents" << std::endl; for (const auto & entry : fetch_buffer_) { output << '\t' << entry << std::endl; @@ -261,11 +278,11 @@ namespace olympia void Fetch::onStartingTeardown_() { - // if ((false == rob_stopped_simulation_) && (false == fetch_buffer_.empty())) - // { - // dumpDebugContent_(std::cerr); - // sparta_assert(false, "fetch buffer has pending instructions"); - // } + if ((false == rob_stopped_simulation_) && (false == fetch_buffer_.empty())) + { + dumpDebugContent_(std::cerr); + sparta_assert(false, "fetch buffer has pending instructions"); + } } } diff --git a/core/Fetch.hpp b/core/Fetch.hpp index 36b4c236..8eb46c38 100644 --- a/core/Fetch.hpp +++ b/core/Fetch.hpp @@ -57,6 +57,8 @@ namespace olympia PARAMETER(uint32_t, num_to_fetch, 4, "Number of instructions to fetch") PARAMETER(bool, skip_nonuser_mode, false, "For STF traces, skip system instructions if present") + PARAMETER(uint32_t, block_width, 16, "Block width of memory read requests, in bytes") + PARAMETER(uint32_t, fetch_buffer_size, 8, "Size of fetch buffer in blocks") }; /** @@ -103,6 +105,9 @@ namespace olympia //////////////////////////////////////////////////////////////////////////////// // Instruction fetch + + // Unit's clock + const sparta::Clock * my_clk_ = nullptr; // Number of instructions to fetch const uint32_t num_insts_to_fetch_; @@ -112,34 +117,45 @@ namespace olympia // Number of credits from decode that fetch has uint32_t credits_inst_queue_ = 0; + // Number of credits available in the ICache uint32_t credits_icache_ = 0; - // Unit's clock - const sparta::Clock * my_clk_ = nullptr; + // Amount to left shift an Instructions PC to get the ICache block number + const uint32_t icache_block_shift_; + + // Buffers up instructions read from the tracefile + std::deque ibuf_; // Size of trace buffer (must be sized >= L1ICache bandwidth / 2B) const uint32_t ibuf_capacity_; + // Fetch buffer: Holds a queue of instructions that are either + // waiting for an ICache hit response, or they're ready to be + // send to decode + std::deque fetch_buffer_; + + // Size of fetch buffer, tracked separately as it sized + // in terms of icache block requests, not instructions. + const uint32_t fetch_buffer_capacity_; + uint32_t fetch_buffer_occupancy_ = 0; + // allocator for ICache transactions MemoryAccessInfoAllocator & memory_access_allocator_; - uint32_t fetch_buffer_occupancy_ = 0; - const uint32_t fetch_buffer_capacity_ = 16; + // ROB terminated simulation + bool rob_stopped_simulation_ {false}; // Instruction generation std::unique_ptr inst_generator_; - // Fetch instruction event, triggered when there are credits - // from decode. The callback set is either to fetch random - // instructions or a perfect IPC set + // Fetch instruction event, the callback is set to request + // instructions from the instruction cache and place them in the + // fetch buffer. std::unique_ptr> ev_fetch_insts; - std::unique_ptr> ev_drive_insts; - // Buffers up instructions read from the tracefile - std::deque ibuf_; - - // Holds fetched instructions from the ICache - std::deque fetch_buffer_; + // Send instructions event, the callback is set to read instructions + // from the fetch buffer and send them to the decode unit + std::unique_ptr> ev_send_insts; //////////////////////////////////////////////////////////////////////////////// // Callbacks @@ -154,7 +170,7 @@ namespace olympia void fetchInstruction_(); // Read instructions from the fetch buffer and send them to decode - void driveInstructions_(); + void sendInstructions_(); // Receive flush from FlushManager void flushFetch_(const FlushManager::FlushingCriteria &); @@ -165,6 +181,8 @@ namespace olympia // Receive read data from the instruction cache void receiveCacheResponse_(const MemoryAccessInfoPtr &); + // Debug callbacks, used to log fetch buffer contents + void onROBTerminate_(const bool&); void onStartingTeardown_() override; void dumpDebugContent_(std::ostream&) const override final; diff --git a/core/ICache.cpp b/core/ICache.cpp index da338783..b78b8a58 100644 --- a/core/ICache.cpp +++ b/core/ICache.cpp @@ -12,7 +12,7 @@ namespace olympia { - const char ICache::name[] = "instruction_cache"; + const char ICache::name[] = "icache"; ICache::ICache(sparta::TreeNode *node, const ICacheParameterSet *p) : sparta::Unit(node), From 50acbb1347df636bd9e9ba96daf6170c3beda59f Mon Sep 17 00:00:00 2001 From: Daniel Bone Date: Mon, 26 Feb 2024 14:48:03 +0000 Subject: [PATCH 07/14] update dcache comments on L2Cache credits --- core/DCache.cpp | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/core/DCache.cpp b/core/DCache.cpp index e803108d..367bd60e 100644 --- a/core/DCache.cpp +++ b/core/DCache.cpp @@ -78,7 +78,9 @@ namespace olympia { memory_access_info_ptr->setCacheState(MemoryAccessInfo::CacheState::HIT); }else{ memory_access_info_ptr->setCacheState(MemoryAccessInfo::CacheState::MISS); - // Poll on dcache_l2cache_credits_ > 0 which means + // DCache is blocking for now. Busy is set on miss, until the miss is + // resolved by the L2. + // For NB behaviour: Poll on dcache_l2cache_credits_ > 0 which means // that L2Cache can accept requests from DCache. // Provide a corresponsing backpressure mechanism up the pipeline. if(!busy_) { @@ -100,11 +102,6 @@ namespace olympia { } void DCache::getCreditsFromL2Cache_(const uint32_t &ack) { - // When DCache sends the request to L2Cache for a miss, - // This bool will be set to false, and Dcache should wait for ack from - // L2Cache notifying DCache that there is space in it's dcache request buffer - // - // Set it to true so that the following misses from DCache can be sent out to L2Cache. dcache_l2cache_credits_ += ack; } From 9b46b07737216069f72d04b861d50a290c8ff343 Mon Sep 17 00:00:00 2001 From: Shobhit Date: Thu, 26 Sep 2024 22:45:14 +0530 Subject: [PATCH 08/14] Resolve conflicts between branch 'master' and 'danbone/issue_143_icache' of https://github.com/danbone/riscv-perf-model --- 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c99586cf..45ee168d 100755 --- a/.github/actions/build/entrypoint.sh +++ b/.github/actions/build/entrypoint.sh @@ -2,7 +2,7 @@ set -x -source "/usr/share/miniconda/etc/profile.d/conda.sh" +source $CONDA/etc/profile.d/conda.sh conda activate riscv_perf_model echo "Starting Build Entry" @@ -23,7 +23,7 @@ echo "Building Sparta Infra" cd ${GITHUB_WORKSPACE}/map/sparta mkdir -p release cd release -CC=$COMPILER CXX=$CXX_COMPILER cmake .. -DCMAKE_BUILD_TYPE=$OLYMPIA_BUILD_TYPE -DGEN_DEBUG_INFO=OFF -DCMAKE_INSTALL_PREFIX=${CONDA_PREFIX} +CC=$COMPILER CXX=$CXX_COMPILER cmake .. -DCMAKE_BUILD_TYPE=Release -DGEN_DEBUG_INFO=OFF -DCMAKE_INSTALL_PREFIX=${CONDA_PREFIX} if [ $? -ne 0 ]; then echo "ERROR: Cmake for Sparta framework failed" exit 1 diff --git a/.github/workflows/conda/macos_env.yml b/.github/workflows/conda/macos_env.yml new file mode 100644 index 00000000..4893d8dc --- /dev/null +++ b/.github/workflows/conda/macos_env.yml @@ -0,0 +1,183 @@ +name: riscv_perf_model +channels: + - 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libuuid=2.32.* + - libuv=1.44.* + - libvorbis=1.3.* + - libwebp-base=1.2.* + - libxcb=1.* + - libxml2=2.10.* + - libzlib=1.2.* + - lld=15.0.7 + - llvm-openmp=15.0.* + - llvm-tools=14.0.* + - lz4-c=1.9.* + - make=4.* + - matplotlib-base=3.7.* + - matplotlib-inline=0.1.* + - mpfr=4.1.* + - munkres=1.1.* + - ncurses=6.* + - numpy=1.21.* + - openjpeg=2.5.* + - openssl=3.0.* + - packaging=23.* + - pango=1.50.* + - parso=0.8.* + - pathlib2 + - pcre2=10.* + - pcre=8.* + - pexpect=4.8.* + - pickleshare=0.7.* + - pillow=9.4.* + - pip=23.0.* + - pixman=0.40.* + - popt=1.* + - prompt-toolkit=3.0.* + - pthread-stubs=0.* + - ptyprocess=0.7.* + - pure_eval=0.2.* + - pycparser=2.* + - pygments=2.11.* + - pyopenssl=23.0.* + - pyparsing=3.0.* + - pysocks=1.7.* + - python=3.10.* + - python_abi=3.* + - python-dateutil=2.8.* + - pyyaml=6.* + - rapidjson=1.1.* + - readline=8.1.* + - requests=2.28.* + - rhash=1.4.* + - rsync=3.2.* + - setuptools=67.4.* + - sigtool=0.1.* + - six=1.16.* + - sqlite=3.40.* + - stack_data=0.6.* + - sysroot_linux-64=2.* + - tapi=1100.0.* + - texlive-core + - tk=8.6.* + - traitlets=5.9.* + - tzdata + - unicodedata2=15.0.* + - urllib3=1.26.* + - wcwidth=0.2.* + - wheel=0.38.* + - wxpython=4.2.* + - xorg-kbproto=1.0.* + - xorg-libice=1.0.* + - xorg-libsm=1.2.* + - xorg-libx11=1.7.* + - xorg-libxau=1.0.* + - xorg-libxdmcp=1.1.* + - xorg-libxext=1.3.* + - xorg-libxrender=0.9.* + - xorg-renderproto=0.11.* + - xorg-xextproto=7.3.* + - xorg-xproto=7.0.* + - xxhash=0.8.* + - xz=5.2.* + - yaml=0.2.* + - yaml-cpp=0.7.* + - zlib=1.2.* + - zstd=1.5.* diff --git a/.github/workflows/macos-build.yml b/.github/workflows/macos-build.yml new file mode 100644 index 00000000..4c3ef2da --- /dev/null +++ b/.github/workflows/macos-build.yml @@ -0,0 +1,89 @@ +on: + pull_request: + branches: + - master + +env: + CACHE_VERSION: v1 + +name: Regress Olympia on MacOS +jobs: + build_test_job: + strategy: + # Strategy is a matrix of debug and release builds/regression + matrix: + os: [macos-12] + BUILD_TYPE: [Debug] + COMPILER: [clang] + + name: MacOS-${{ matrix.BUILD_TYPE }}-${{matrix.COMPILER}} + runs-on: ${{ matrix.os }} + + # Set up a global environment variable for build scripts + env: + OLYMPIA_BUILD_TYPE: ${{ matrix.BUILD_TYPE }} + COMPILER: ${{ matrix.COMPILER }} + + steps: + + # Get Olympia + - name: Checkout Olympia + uses: actions/checkout@v3 + with: + submodules: recursive + + # Get Sparta + - name: Checkout Sparta + uses: actions/checkout@v3 + with: + repository: sparcians/map + path: map + ref: map_v2.0.13 + + # Setup Conda and build environment + - name: Grab Python v3.8 + uses: actions/setup-python@v3 + with: + python-version: 3.8 + + # Cache the conda dependencies to + - name: Cache conda deps + uses: actions/cache@v3 + with: + key: ${{ matrix.os }}-${{ matrix.BUILD_TYPE }}-${{ matrix.COMPILER }}-conda-${{ hashFiles('.github/workflows/conda/macos_env.yml') }} + path: /usr/share/miniconda/envs/riscv_perf_model # Default path for conda + + # Setup CCache to cache builds + - name: ccache + uses: hendrikmuhs/ccache-action@v1.2 + with: + key: ${{ matrix.os }}-${{ matrix.BUILD_TYPE }}-${{ matrix.COMPILER }}-ccache-${{ github.ref_name }} + restore-keys: | + ${{ matrix.os }}-${{ matrix.BUILD_TYPE }}-${{ matrix.COMPILER }}-ccache-master + ${{ matrix.os }}-${{ matrix.BUILD_TYPE }}-${{ matrix.COMPILER }}-ccache + + - name: Setup Conda Environment + uses: conda-incubator/setup-miniconda@v2 + with: + miniforge-variant: Mambaforge + channels: conda-forge,defaults + channel-priority: true + activate-environment: riscv_perf_model + environment-file: .github/workflows/conda/macos_env.yml + + # Build + - name: Build & Regress + run: ./.github/actions/build/entrypoint.sh + + # Save error logs, etc + - name: Save artifacts + if: failure() + uses: actions/upload-artifact@main + with: + name: ErrorLogs-${{matrix.BUILD_TYPE}}-${{matrix.COMPILER}} + path: ${{matrix.BUILD_TYPE}}/test/ + + #- name: CTest + # # Run CTests without Valgrind tests otherwise the runtime will be TOO long + # if: ${{ env.DABBLE_BUILD_TYPE == 'release' }} && ${{ env.VALGRIND == 'false' }} + # uses: ./.github/actions/ctest # Uses an action.yml in directory diff --git a/.gitmodules b/.gitmodules index 47909a15..1587bd6c 100644 --- a/.gitmodules +++ b/.gitmodules @@ -4,3 +4,6 @@ [submodule "stf_lib"] path = stf_lib url = https://github.com/sparcians/stf_lib.git +[submodule "fsl"] + path = fsl + url = https://github.com/Condor-Performance-Modeling/fsl diff --git a/.idea/.gitignore b/.idea/.gitignore new file mode 100644 index 00000000..13566b81 --- /dev/null +++ b/.idea/.gitignore @@ -0,0 +1,8 @@ +# Default ignored files +/shelf/ +/workspace.xml +# Editor-based HTTP Client requests +/httpRequests/ +# Datasource local storage ignored files +/dataSources/ +/dataSources.local.xml diff --git a/.idea/codeStyles/Project.xml b/.idea/codeStyles/Project.xml new file mode 100644 index 00000000..7b6888de --- /dev/null +++ b/.idea/codeStyles/Project.xml @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/codeStyles/codeStyleConfig.xml b/.idea/codeStyles/codeStyleConfig.xml new file mode 100644 index 00000000..79ee123c --- /dev/null +++ b/.idea/codeStyles/codeStyleConfig.xml @@ -0,0 +1,5 @@ + + + + \ No newline at end of file diff --git a/.idea/editor.xml b/.idea/editor.xml new file mode 100644 index 00000000..adc7cfa7 --- /dev/null +++ b/.idea/editor.xml @@ -0,0 +1,15 @@ + + + + + \ No newline at end of file diff --git a/.idea/misc.xml b/.idea/misc.xml new file mode 100644 index 00000000..8e9eec95 --- /dev/null +++ b/.idea/misc.xml @@ -0,0 +1,11 @@ + + + + + + + + \ No newline at end of file diff --git a/.idea/modules.xml b/.idea/modules.xml new file mode 100644 index 00000000..5f64bbe2 --- /dev/null +++ b/.idea/modules.xml @@ -0,0 +1,8 @@ + + + + + + + + \ No newline at end of file diff --git a/.idea/riscv-perf-model.iml b/.idea/riscv-perf-model.iml new file mode 100644 index 00000000..f08604bb --- /dev/null +++ b/.idea/riscv-perf-model.iml @@ -0,0 +1,2 @@ + + \ No newline at end of file diff --git a/.idea/vcs.xml b/.idea/vcs.xml new file mode 100644 index 00000000..df7835b2 --- /dev/null +++ b/.idea/vcs.xml @@ -0,0 +1,10 @@ + + + + + + + + + + \ No newline at end of file diff --git a/CMakeLists.txt b/CMakeLists.txt index bee99e2c..b106725b 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -35,12 +35,14 @@ include_directories(${SPARTA_INCLUDE_DIRS}) # Set up STF library set (STF_LIB_BASE ${PROJECT_SOURCE_DIR}/stf_lib) set (DISABLE_STF_DOXYGEN ON) +set (DISABLE_STF_TESTS ON) if (CMAKE_BUILD_TYPE MATCHES "^[Rr]elease") set (FULL_LTO true) - include(${STF_LIB_BASE}/cmake/stf_linker_setup.cmake) - setup_stf_linker(false) endif() +include(${STF_LIB_BASE}/cmake/stf_linker_setup.cmake) +setup_stf_linker(false) + # Use ccache if installed find_program (CCACHE_PROGRAM ccache) @@ -60,14 +62,20 @@ set(CMAKE_CXX_FLAGS_DEBUG "-O0 -g") # Include directories include_directories (core mss sim) +include_directories (SYSTEM fsl) include_directories (SYSTEM mavis) include_directories (SYSTEM stf_lib) -# Mavis, the Core, MSS, and the simulator +# Mavis, the Core, MSS, the simulator and Fusion + add_subdirectory (mavis) add_subdirectory (core) add_subdirectory (mss) +# Tell FSL to use the top mavis submodule, instead of fsl's submodule +set(FSL_MAVIS_PATH "${CMAKE_CURRENT_SOURCE_DIR}/mavis") +add_subdirectory (fsl) + # Add STF library to the build add_subdirectory (${STF_LIB_BASE}) diff --git a/arches/big_core.yaml b/arches/big_core.yaml index a6a6a656..37566b97 100644 --- a/arches/big_core.yaml +++ b/arches/big_core.yaml @@ -11,6 +11,7 @@ top.cpu.core0: rename.params.num_to_rename: 8 rename.params.num_integer_renames: 64 rename.params.num_float_renames: 64 + rename.params.num_vector_renames: 64 dispatch.params.num_to_dispatch: 8 rob.params.num_to_retire: 8 dcache.params: @@ -23,7 +24,7 @@ top.cpu.core0.extension.core_extensions: # targets of: "int" and "div" pipelines: [ - ["int"], # exe0 + ["sys"], # exe0 ["int", "div"], # exe1 ["int", "mul"], # exe2 ["int", "mul", "i2f", "cmov"], # exe3 @@ -32,7 +33,8 @@ top.cpu.core0.extension.core_extensions: ["float", "faddsub", "fmac"], # exe6 ["float", "f2i"], # exe7 ["br"], # exe8 - ["br"] # exe9 + ["br"], # exe9 + ["vint", "vset", "vdiv", "vmul"] ] # this is used to set how many units per queue # ["0", "3"] means iq0 has exe0, exe1, exe2, and exe3, so it's inclusive @@ -47,25 +49,37 @@ top.cpu.core0.extension.core_extensions: ["2", "3"], # iq1 -> exe2, exe3 ["4", "5"], # iq2 -> exe4, exe5 ["6", "7"], # iq3 -> exe6, exe7 - ["8", "9"] # iq4 -> exe8, exe9 + ["8", "9"], # iq4 -> exe8, exe9 + ["10"] # iq5 -> exe10 ] top.cpu.core0.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/arches/fusion.yaml b/arches/fusion.yaml new file mode 100644 index 00000000..d944d6e9 --- /dev/null +++ b/arches/fusion.yaml @@ -0,0 +1,13 @@ +include: big_core.yaml +top.cpu.core0: + decode: + params: + num_to_decode: 8 + fusion_enable: false + fusion_debug: false + fusion_enable_register: 0xFFFFFFFF + fusion_max_latency: 8 + fusion_match_max_tries: 1023 + fusion_max_group_size: 8 + fusion_summary_report: fusion_summary.txt + fusion_group_definitions: [ arches/fusion/dhrystone.json ] diff --git a/arches/fusion/dhrystone.json b/arches/fusion/dhrystone.json new file mode 100644 index 00000000..3672f241 --- /dev/null +++ b/arches/fusion/dhrystone.json @@ -0,0 +1,37 @@ +{ + "fusiongroups" : [ + { "name" : "uf039", "uids" : ["0xd","0xa"], "tx" : "dfltXform_" }, + { "name" : "uf038", "uids" : ["0x3","0xe"], "tx" : "dfltXform_" }, + { "name" : "uf037", "uids" : ["0x20","0x4"], "tx" : "dfltXform_" }, + { "name" : "uf036", "uids" : ["0x9","0x2d"], "tx" : "dfltXform_" }, + { "name" : "uf035", "uids" : ["0x18","0xe"], "tx" : "dfltXform_" }, + { "name" : "uf034", "uids" : ["0x20","0x18"], "tx" : "dfltXform_" }, + { "name" : "uf033", "uids" : ["0xe","0xd","0xa"], "tx" : "dfltXform_" }, + { "name" : "uf032", "uids" : ["0x10","0x10"], "tx" : "dfltXform_" }, + { "name" : "uf031", "uids" : ["0x18","0x20"], "tx" : "dfltXform_" }, + { "name" : "uf030", "uids" : ["0x22","0x26"], "tx" : "dfltXform_" }, + { "name" : "uf029", "uids" : ["0x26","0x34"], "tx" : "dfltXform_" }, + { "name" : "uf028", "uids" : ["0x21","0x20"], "tx" : "dfltXform_" }, + { "name" : "uf027", "uids" : ["0x34","0x35"], "tx" : "dfltXform_" }, + { "name" : "uf026", "uids" : ["0x2d","0x22"], "tx" : "dfltXform_" }, + { "name" : "uf025", "uids" : ["0x2e","0x2d"], "tx" : "dfltXform_" }, + { "name" : "uf024", "uids" : ["0x2e","0x21"], "tx" : "dfltXform_" }, + { "name" : "uf023", "uids" : ["0xd","0xa","0x22"], "tx" : "dfltXform_" }, + { "name" : "uf022", "uids" : ["0x26","0x34","0x9"], "tx" : "dfltXform_" }, + { "name" : "uf021", "uids" : ["0xa","0x22","0x26"], "tx" : "dfltXform_" }, + { "name" : "uf020", "uids" : ["0x18","0x20","0x4"], "tx" : "dfltXform_" }, + { "name" : "uf019", "uids" : ["0x22","0x26","0x34"], "tx" : "dfltXform_" }, + { "name" : "uf018", "uids" : ["0x2e","0x21","0x20"], "tx" : "dfltXform_" }, + { "name" : "uf017", "uids" : ["0x21","0x20","0x18"], "tx" : "dfltXform_" }, + { "name" : "uf016", "uids" : ["0x20","0x18","0x20"], "tx" : "dfltXform_" }, + { "name" : "uf008", "uids" : ["0xd","0x35"], "tx" : "dfltXform_" }, + { "name" : "uf007", "uids" : ["0xa","0x22"], "tx" : "dfltXform_" }, + { "name" : "uf005", "uids" : ["0xe","0xd"], "tx" : "dfltXform_" }, + { "name" : "uf004", "uids" : ["0xe","0x34"], "tx" : "dfltXform_" }, + { "name" : "uf003", "uids" : ["0x34","0x9"], "tx" : "dfltXform_" }, + { "name" : "uf002", "uids" : ["0x2e","0x35"], "tx" : "dfltXform_" }, + { "name" : "uf001", "uids" : ["0x35","0x35"], "tx" : "dfltXform_" }, + { "name" : "uf213", "uids" : ["0x2e","0x2e"], "tx" : "dfltXform_" }, + { "name" : "uf000", "uids" : ["0x35","0x2e"], "tx" : "dfltXform_" } + ] +} diff --git a/arches/isa_json/gen_uarch_rv64v_json.py b/arches/isa_json/gen_uarch_rv64v_json.py new file mode 100755 index 00000000..5c258be0 --- /dev/null +++ b/arches/isa_json/gen_uarch_rv64v_json.py @@ -0,0 +1,294 @@ +#!/usr/bin/env python + +import os +import json + +MAVIS = os.environ.get('MAVIS', "../../mavis/") +JSON = os.environ.get('JSON', "olympia_uarch_rv64v.json") + +SUPPORTED_INSTS = { +# Vector Config Setting Instructions + "vsetvli" : {"pipe" : "vset", "latency" : 1}, + "vsetvl" : {"pipe" : "vset", "latency" : 1}, + "vsetivli" : {"pipe" : "vset", "latency" : 1}, + +# TODO: Vector Loads and Stores: Vector Unit-Stride Instructions +# TODO: Vector Loads and Stores: Vector Strided Instructions +# TODO: Vector Loads and Stores: Vector Indexed Instructions +# TODO: Vector Loads and Stores: Unit-stride Fault-Only-First Loads +# TODO: Vector Loads and Stores: Vector Load/Store Segment Instructions +# TODO: Vector Loads and Stores: Vector Load/Store Whole Register Instructions + +# Vector Integer Arithmetic Instructions: Vector Single-Width Integer Add and Subtract + "vadd.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vadd.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vadd.vi" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vsub.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vsub.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vrsub.vi" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vrsub.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + +# Vector Integer Arithmetic Instructions: Vector Widening Integer Add/Subtract + "vwaddu.vv" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwaddu.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwsubu.vv" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwsubu.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwadd.vv" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwadd.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwsub.vv" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwsub.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwaddu.wv" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwaddu.wx" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwsubu.wv" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwsubu.wx" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwadd.wv" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwadd.wx" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwsub.wv" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + "vwsub.wx" : {"pipe" : "vint", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 1}, + +# TODO: Vector Integer Arithmetic Instructions: Vector Integer Extension +# FIXME: Requires Mavis fix to support correctly +# "vzext.vf2" : {"pipe" : "vint", "uop_gen" : "ARITH_EXT", "latency" : 1}, +# "vsext.vf2" : {"pipe" : "vint", "uop_gen" : "ARITH_EXT", "latency" : 1}, +# "vzext.vf4" : {"pipe" : "vint", "uop_gen" : "ARITH_EXT", "latency" : 1}, +# "vsext.vf4" : {"pipe" : "vint", "uop_gen" : "ARITH_EXT", "latency" : 1}, +# "vzext.vf8" : {"pipe" : "vint", "uop_gen" : "ARITH_EXT", "latency" : 1}, +# "vsext.vf8" : {"pipe" : "vint", "uop_gen" : "ARITH_EXT", "latency" : 1}, + +# Vector Integer Arithmetic Instructions: Vector Integer Add-with-Carry/Subtract-with-Borrow Instructions +# FIXME: Requires Mavis fix to include vector mask + "vadc.vvm" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vadc.vxm" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vadc.vim" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmadc.vvm" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmadc.vxm" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmadc.vim" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmadc.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmadc.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmadc.vi" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vsbc.vvm" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vsbc.vxm" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmsbc.vvm" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmsbc.vxm" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmsbc.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmsbc.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + +# Vector Integer Arithmetic Instructions: Vector Bitwise Logical Instructions + "vand.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vand.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vand.vi" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vor.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vor.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vor.vi" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vxor.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vxor.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vxor.vi" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + +# Vector Integer Arithmetic Instructions: Vector Single-Width Shift Instructions + "vsll.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vsll.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vsll.vi" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vsrl.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vsrl.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vsrl.vi" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vsra.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vsra.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vsra.vi" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + +# Vector Integer Arithmetic Instructions: Vector Narrowing Integer Right Shift Instructions + "vnsrl.wv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vnsrl.wx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vnsrl.wi" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vnsra.wv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vnsra.wx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vnsra.wi" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + +# Vector Integer Arithmetic Instructions: Vector Integer Compare Instructions + "vmseq.vv" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmseq.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmseq.vi" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsne.vv" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsne.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsne.vi" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsltu.vv" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsltu.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmslt.vv" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmslt.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsleu.vv" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsleu.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsleu.vi" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsle.vv" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsle.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsle.vi" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsgtu.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsgtu.vi" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsgt.vx" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + "vmsgt.vi" : {"pipe" : "vint", "uop_gen" : "ARITH_SINGLE_DEST", "latency" : 1}, + +# Vector Integer Arithmetic Instructions: Vector Integer Min/Max Instructions + "vminu.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vminu.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmin.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmin.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmaxu.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmaxu.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmax.vv" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmax.vx" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + +# Vector Integer Arithmetic Instructions: Vector Single-Width Integer Multiply Instructions + "vmul.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH", "latency" : 3}, + "vmul.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH", "latency" : 3}, + "vmulhu.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH", "latency" : 3}, + "vmulhu.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH", "latency" : 3}, + "vmulh.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH", "latency" : 3}, + "vmulh.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH", "latency" : 3}, + "vmulhsu.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH", "latency" : 3}, + "vmulhsu.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH", "latency" : 3}, + +# Vector Integer Arithmetic Instructions: Vector Integer Divide Instructions + "vdiv.vv" : {"pipe" : "vdiv", "uop_gen" : "ARITH", "latency" : 23}, + "vdiv.vx" : {"pipe" : "vdiv", "uop_gen" : "ARITH", "latency" : 23}, + "vdivu.vv" : {"pipe" : "vdiv", "uop_gen" : "ARITH", "latency" : 23}, + "vdivu.vx" : {"pipe" : "vdiv", "uop_gen" : "ARITH", "latency" : 23}, + "vremu.vv" : {"pipe" : "vdiv", "uop_gen" : "ARITH", "latency" : 23}, + "vremu.vx" : {"pipe" : "vdiv", "uop_gen" : "ARITH", "latency" : 23}, + "vrem.vv" : {"pipe" : "vdiv", "uop_gen" : "ARITH", "latency" : 23}, + "vrem.vx" : {"pipe" : "vdiv", "uop_gen" : "ARITH", "latency" : 23}, + +# Vector Integer Arithmetic Instructions: Vector Widening Integer Multiply Instructions + "vwmul.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 3}, + "vwmul.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 3}, + "vwmulu.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 3}, + "vwmulu.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 3}, + "vwmulsu.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 3}, + "vwmulsu.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH_WIDE_DEST", "latency" : 3}, + +# Vector Integer Arithmetic Instructions: Vector Single-Width Integer Multiply-Add Instructions + "vmacc.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH_MAC", "latency" : 3}, + "vmacc.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH_MAC", "latency" : 3}, + "vnmsac.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH_MAC", "latency" : 3}, + "vnmsac.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH_MAC", "latency" : 3}, + "vmadd.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH_MAC", "latency" : 3}, + "vmadd.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH_MAC", "latency" : 3}, + "vnmsub.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH_MAC", "latency" : 3}, + "vnmsub.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH_MAC", "latency" : 3}, + +# Vector Integer Arithmetic Instructions: Vector Widening Integer Multiply-Add Instructions + "vwmaccu.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH_MAC_WIDE_DEST", "latency" : 3}, + "vwmaccu.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH_MAC_WIDE_DEST", "latency" : 3}, + "vwmacc.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH_MAC_WIDE_DEST", "latency" : 3}, + "vwmacc.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH_MAC_WIDE_DEST", "latency" : 3}, + "vwmaccsu.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH_MAC_WIDE_DEST", "latency" : 3}, + "vwmaccsu.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH_MAC_WIDE_DEST", "latency" : 3}, + "vwmaccus.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH_MAC_WIDE_DEST", "latency" : 3}, + +# Vector Integer Arithmetic Instructions: Vector Integer Merge Instructions +# FIXME: Requires Mavis fix to include vector mask + "vmerge.vvm" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmerge.vxm" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmerge.vim" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + +# Vector Integer Arithmetic Instructions: Vector Integer Move Instructions + "vmv.v.v" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmv.v.x" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + "vmv.v.i" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1}, + +# TODO: Vector Fixed-Point Arithmetic Instructions: Vector Single-Width Saturating Add and Subtract +# TODO: Vector Fixed-Point Arithmetic Instructions: Vector Single-Width Averaging Add and Subtract +# Vector Fixed-Point Arithmetic Instructions: Vector Single-Width Fractional Multiply with Rounding and Saturation + "vsmul.vx" : {"pipe" : "vmul", "uop_gen" : "ARITH", "latency" : 3}, + "vsmul.vv" : {"pipe" : "vmul", "uop_gen" : "ARITH", "latency" : 3}, + +# TODO: Vector Fixed-Point Arithmetic Instructions: Vector Single-Width Scaling Shift Instructions +# TODO: Vector Fixed-Point Arithmetic Instructions: Vector Narrowing Fixed-Point Clip Instructions + +# TODO: Vector Floating-Point Instructions: Vector Floating-Point Exception Flags +# TODO: Vector Floating-Point Instructions: Vector Single-Width Floating-Point Add/Subtract Instructions +# TODO: Vector Floating-Point Instructions: Vector Widening Floating-Point Add/Subtract Instructions +# TODO: Vector Floating-Point Instructions: Vector Single-Width Floating-Point Multiply/Divide Instructions +# TODO: Vector Floating-Point Instructions: Vector Widening Floating-Point Multiply +# TODO: Vector Floating-Point Instructions: Vector Single-Width Floating-Point Fused Multiply-Add Instructions +# TODO: Vector Floating-Point Instructions: Vector Widening Floating-Point Fused Multiply-Add Instructions +# TODO: Vector Floating-Point Instructions: Vector Floating-Point Square-Root Instruction +# TODO: Vector Floating-Point Instructions: Vector Floating-Point Reciprocal Square-Root Estimate Instruction +# TODO: Vector Floating-Point Instructions: Vector Floating-Point Reciprocal Estimate Instruction +# TODO: Vector Floating-Point Instructions: Vector Floating-Point MIN/MAX Instructions +# TODO: Vector Floating-Point Instructions: Vector Floating-Point Sign-Injection Instructions +# TODO: Vector Floating-Point Instructions: Vector Floating-Point Compare Instructions +# TODO: Vector Floating-Point Instructions: Vector Floating-Point Classify Instruction +# TODO: Vector Floating-Point Instructions: Vector Floating-Point Merge Instruction +# TODO: Vector Floating-Point Instructions: Vector Floating-Point Move Instruction +# TODO: Vector Floating-Point Instructions: Single-Width Floating-Point/Integer Type-Convert Instructions +# TODO: Vector Floating-Point Instructions: Widening Floating-Point/Integer Type-Convert Instructions +# TODO: Vector Floating-Point Instructions: Narrowing Floating-Point/Integer Type-Convert Instructions + +# TODO: Vector Reduction Operations: Vector Single-Width Integer Reduction Instructions +# TODO: Vector Reduction Operations: Vector Widening Integer Reduction Instructions +# TODO: Vector Reduction Operations: Vector Single-Width Floating-Point Reduction Instructions +# TODO: Vector Reduction Operations: Vector Widening Floating-Point Reduction Instructions + +# Vector Mask Instructions: Vector Mask-Register Logical Instructions + "vmandn.mm" : {"pipe" : "vmask", "uop_gen" : "NONE", "latency" : 1}, + "vmand.mm" : {"pipe" : "vmask", "uop_gen" : "NONE", "latency" : 1}, + "vmor.mm" : {"pipe" : "vmask", "uop_gen" : "NONE", "latency" : 1}, + "vmxor.mm" : {"pipe" : "vmask", "uop_gen" : "NONE", "latency" : 1}, + "vmorn.mm" : {"pipe" : "vmask", "uop_gen" : "NONE", "latency" : 1}, + "vmnand.mm" : {"pipe" : "vmask", "uop_gen" : "NONE", "latency" : 1}, + "vmnor.mm" : {"pipe" : "vmask", "uop_gen" : "NONE", "latency" : 1}, + "vmxnor.mm" : {"pipe" : "vmask", "uop_gen" : "NONE", "latency" : 1}, + +# TODO: Vector Mask Instructions: Vector count population in mask vcpop.m +# TODO: Vector Mask Instructions: vfirst nd-rst-set mask bit +# TODO: Vector Mask Instructions: vmsbf.m set-before-rst mask bit +# TODO: Vector Mask Instructions: vmsif.m set-including-rst mask bit +# TODO: Vector Mask Instructions: vmsof.m set-only-rst mask bit +# TODO: Vector Mask Instructions: Vector Iota Instruction +# TODO: Vector Mask Instructions: Vector Element Index Instruction + +# TODO: Vector Permutation Instructions: Integer Scalar Move Instructions +# TODO: Vector Permutation Instructions: Floating-Point Scalar Move Instructions +# TODO: Vector Permutation Instructions: Vector Slide Instructions +# TODO: Vector Permutation Instructions: Vector Register Gather Instructions +# TODO: Vector Permutation Instructions: Vector Compress Instruction +# TODO: Vector Permutation Instructions: Whole Vector Register Move +} + +# Get a list of all vector insts from Mavis +mavis_rv64v_json = [] +with open(MAVIS+"json/isa_rv64v.json", "r") as f: + mavis_rv64v_json.extend(json.load(f)) +with open(MAVIS+"json/isa_rv64vf.json", "r") as f: + mavis_rv64v_json.extend(json.load(f)) + +# Sort alphabetically by mnemonic +mavis_rv64v_json.sort(key=lambda opcode: opcode["mnemonic"]) + +# Construct the uarch json +uarch_json = [] +for opcode in mavis_rv64v_json: + mnemonic = opcode["mnemonic"] + + # Assume inst is unsupported + opcode_entry = { + "mnemonic" : mnemonic, + "pipe" : "?", + "uop_gen" : "NONE", + "latency" : 0 + } + + # If it is supported, get the pipe and latency + if mnemonic in SUPPORTED_INSTS.keys(): + opcode_entry["mnemonic"] = mnemonic + opcode_entry["pipe"] = SUPPORTED_INSTS[mnemonic]["pipe"] + if(SUPPORTED_INSTS[mnemonic].get("uop_gen")): + opcode_entry["uop_gen"] = SUPPORTED_INSTS[mnemonic]["uop_gen"] + opcode_entry["pipe"] = SUPPORTED_INSTS[mnemonic]["pipe"] + opcode_entry["latency"] = SUPPORTED_INSTS[mnemonic]["latency"] + + uarch_json.append(opcode_entry) + +# Write the json to the file +with open(JSON, "w") as f: + print("Writing rv64v uarch json to "+JSON) + json.dump(uarch_json, f, indent=4) + diff --git a/arches/isa_json/olympia_uarch_rv64v.json b/arches/isa_json/olympia_uarch_rv64v.json new file mode 100644 index 00000000..118e5b97 --- /dev/null +++ b/arches/isa_json/olympia_uarch_rv64v.json @@ -0,0 +1,2228 @@ +[ + { + "mnemonic": "vaadd.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vaadd.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vaaddu.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vaaddu.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vadc.vim", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vadc.vvm", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vadc.vxm", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vadd.vi", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vadd.vv", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vadd.vx", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vand.vi", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vand.vv", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vand.vx", + "pipe": "vint", + "uop_gen": "ARITH", + "latency": 1 + }, + { + "mnemonic": "vasub.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vasub.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vasubu.vv", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vasubu.vx", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vcompress.vm", + "pipe": "?", + "uop_gen": "NONE", + "latency": 0 + }, + { + "mnemonic": "vdiv.vv", + "pipe": "vdiv", + "uop_gen": "ARITH", + "latency": 23 + }, + { + "mnemonic": "vdiv.vx", + "pipe": "vdiv", + "uop_gen": "ARITH", + "latency": 23 + }, + { + "mnemonic": "vdivu.vv", + "pipe": "vdiv", + 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# exe0 + ["sys", "int", "mul", "i2f", "cmov"], # exe0 ["int", "div"], # exe1 ["int"], # exe2 ["float", "faddsub", "fmac"], # exe3 ["float", "f2i"], # exe4 - ["br"] # exe5 + ["br"], # exe5 + ["vint", "vset", "vdiv", "vmul"] # exe6 ] # this is used to set how many units per queue @@ -40,7 +41,8 @@ top.cpu.core0.extension.core_extensions: ["0"], # iq0 -> exe0 ["1", "2"], # iq1 -> exe1, exe2 ["3", "4"], # iq2 -> exe3, exe4 - ["5"] # iq3 -> exe5 + ["5"], # iq3 -> exe5 + ["6"] ] top.cpu.core0.rename.scoreboards: @@ -48,16 +50,26 @@ top.cpu.core0.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] diff --git a/arches/small_core.yaml b/arches/small_core.yaml index 7ad9d7d8..67cb94db 100644 --- a/arches/small_core.yaml +++ b/arches/small_core.yaml @@ -18,9 +18,10 @@ top.cpu.core0.extension.core_extensions: # targets of: "int" and "div" pipelines: [ - ["int", "mul", "i2f", "cmov", "div"], # exe0 + ["sys", "int", "mul", "i2f", "cmov", "div"], # exe0 ["float", "faddsub", "fmac", "f2i"], # exe1 - ["br"] # exe2 + ["br"], # exe2 + ["vint", "vset", "vdiv", "vmul"] # exe3 ] # this is used to set how many units per queue # ["0", "3"] means iq0 has exe0, exe1, exe2, and exe3, so it's inclusive @@ -32,7 +33,8 @@ top.cpu.core0.extension.core_extensions: [ ["0"], # iq0 -> exe0 ["1"], # iq1 -> exe1 - ["2"] # iq2 -> exe2 + ["2"], # iq2 -> exe2 + ["3"], # iq3 -> exe3 ] top.cpu.core0.rename.scoreboards: @@ -40,14 +42,23 @@ top.cpu.core0.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] diff --git a/cmake-build-debug/.cmake/api/v1/query/cache-v2 b/cmake-build-debug/.cmake/api/v1/query/cache-v2 new file mode 100644 index 00000000..e69de29b diff --git a/cmake-build-debug/.cmake/api/v1/query/cmakeFiles-v1 b/cmake-build-debug/.cmake/api/v1/query/cmakeFiles-v1 new file mode 100644 index 00000000..e69de29b diff --git a/cmake-build-debug/.cmake/api/v1/query/codemodel-v2 b/cmake-build-debug/.cmake/api/v1/query/codemodel-v2 new file mode 100644 index 00000000..e69de29b diff --git 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DEC(__IBMCPP__ % 10) + +#elif defined(__open_xl__) && defined(__clang__) +# define COMPILER_ID "IBMClang" +# define COMPILER_VERSION_MAJOR DEC(__open_xl_version__) +# define COMPILER_VERSION_MINOR DEC(__open_xl_release__) +# define COMPILER_VERSION_PATCH DEC(__open_xl_modification__) +# define COMPILER_VERSION_TWEAK DEC(__open_xl_ptf_fix_level__) + + +#elif defined(__ibmxl__) && defined(__clang__) +# define COMPILER_ID "XLClang" +# define COMPILER_VERSION_MAJOR DEC(__ibmxl_version__) +# define COMPILER_VERSION_MINOR DEC(__ibmxl_release__) +# define COMPILER_VERSION_PATCH DEC(__ibmxl_modification__) +# define COMPILER_VERSION_TWEAK DEC(__ibmxl_ptf_fix_level__) + + +#elif defined(__IBMCPP__) && !defined(__COMPILER_VER__) && __IBMCPP__ >= 800 +# define COMPILER_ID "XL" + /* __IBMCPP__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMCPP__ % 10) + +#elif defined(__IBMCPP__) && !defined(__COMPILER_VER__) && __IBMCPP__ < 800 +# define COMPILER_ID "VisualAge" + /* __IBMCPP__ = VRP */ +# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100) +# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10) +# define COMPILER_VERSION_PATCH DEC(__IBMCPP__ % 10) + +#elif defined(__NVCOMPILER) +# define COMPILER_ID "NVHPC" +# define COMPILER_VERSION_MAJOR DEC(__NVCOMPILER_MAJOR__) +# define COMPILER_VERSION_MINOR DEC(__NVCOMPILER_MINOR__) +# if defined(__NVCOMPILER_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__NVCOMPILER_PATCHLEVEL__) +# endif + +#elif defined(__PGI) +# define COMPILER_ID "PGI" +# define COMPILER_VERSION_MAJOR DEC(__PGIC__) +# define COMPILER_VERSION_MINOR DEC(__PGIC_MINOR__) +# if defined(__PGIC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__PGIC_PATCHLEVEL__) +# endif + +#elif defined(__clang__) && defined(__cray__) +# define COMPILER_ID "CrayClang" +# define COMPILER_VERSION_MAJOR DEC(__cray_major__) +# define COMPILER_VERSION_MINOR DEC(__cray_minor__) +# define COMPILER_VERSION_PATCH DEC(__cray_patchlevel__) +# define COMPILER_VERSION_INTERNAL_STR __clang_version__ + + +#elif defined(_CRAYC) +# define COMPILER_ID "Cray" +# define COMPILER_VERSION_MAJOR DEC(_RELEASE_MAJOR) +# define COMPILER_VERSION_MINOR DEC(_RELEASE_MINOR) + +#elif defined(__TI_COMPILER_VERSION__) +# define COMPILER_ID "TI" + /* __TI_COMPILER_VERSION__ = VVVRRRPPP */ +# define COMPILER_VERSION_MAJOR DEC(__TI_COMPILER_VERSION__/1000000) +# define COMPILER_VERSION_MINOR DEC(__TI_COMPILER_VERSION__/1000 % 1000) +# define COMPILER_VERSION_PATCH DEC(__TI_COMPILER_VERSION__ % 1000) + +#elif defined(__CLANG_FUJITSU) +# define COMPILER_ID "FujitsuClang" +# define COMPILER_VERSION_MAJOR DEC(__FCC_major__) +# define COMPILER_VERSION_MINOR DEC(__FCC_minor__) +# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__) +# define COMPILER_VERSION_INTERNAL_STR __clang_version__ + + +#elif defined(__FUJITSU) +# define COMPILER_ID "Fujitsu" +# if defined(__FCC_version__) +# define COMPILER_VERSION __FCC_version__ +# elif defined(__FCC_major__) +# define COMPILER_VERSION_MAJOR DEC(__FCC_major__) +# define COMPILER_VERSION_MINOR DEC(__FCC_minor__) +# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__) +# endif +# if defined(__fcc_version) +# define COMPILER_VERSION_INTERNAL DEC(__fcc_version) +# elif defined(__FCC_VERSION) +# define COMPILER_VERSION_INTERNAL DEC(__FCC_VERSION) +# endif + + +#elif defined(__ghs__) +# define COMPILER_ID "GHS" +/* __GHS_VERSION_NUMBER = VVVVRP */ +# ifdef __GHS_VERSION_NUMBER +# define COMPILER_VERSION_MAJOR DEC(__GHS_VERSION_NUMBER / 100) +# define COMPILER_VERSION_MINOR DEC(__GHS_VERSION_NUMBER / 10 % 10) +# define COMPILER_VERSION_PATCH DEC(__GHS_VERSION_NUMBER % 10) +# endif + +#elif defined(__TASKING__) +# define COMPILER_ID "Tasking" + # define COMPILER_VERSION_MAJOR DEC(__VERSION__/1000) + # define COMPILER_VERSION_MINOR DEC(__VERSION__ % 100) +# define COMPILER_VERSION_INTERNAL DEC(__VERSION__) + +#elif defined(__ORANGEC__) +# define COMPILER_ID "OrangeC" +# define COMPILER_VERSION_MAJOR DEC(__ORANGEC_MAJOR__) +# define COMPILER_VERSION_MINOR DEC(__ORANGEC_MINOR__) +# define COMPILER_VERSION_PATCH DEC(__ORANGEC_PATCHLEVEL__) + +#elif defined(__SCO_VERSION__) +# define COMPILER_ID "SCO" + +#elif defined(__ARMCC_VERSION) && !defined(__clang__) +# define COMPILER_ID "ARMCC" +#if __ARMCC_VERSION >= 1000000 + /* __ARMCC_VERSION = VRRPPPP */ + # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/1000000) + # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 100) + # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000) +#else + /* __ARMCC_VERSION = VRPPPP */ + # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/100000) + # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 10) + # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000) +#endif + + +#elif defined(__clang__) && defined(__apple_build_version__) +# define COMPILER_ID "AppleClang" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# define COMPILER_VERSION_MAJOR DEC(__clang_major__) +# define COMPILER_VERSION_MINOR DEC(__clang_minor__) +# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__) +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif +# define COMPILER_VERSION_TWEAK DEC(__apple_build_version__) + +#elif defined(__clang__) && defined(__ARMCOMPILER_VERSION) +# define COMPILER_ID "ARMClang" + # define COMPILER_VERSION_MAJOR DEC(__ARMCOMPILER_VERSION/1000000) + # define COMPILER_VERSION_MINOR DEC(__ARMCOMPILER_VERSION/10000 % 100) + # define COMPILER_VERSION_PATCH DEC(__ARMCOMPILER_VERSION/100 % 100) +# define COMPILER_VERSION_INTERNAL DEC(__ARMCOMPILER_VERSION) + +#elif defined(__clang__) && defined(__ti__) +# define COMPILER_ID "TIClang" + # define COMPILER_VERSION_MAJOR DEC(__ti_major__) + # define COMPILER_VERSION_MINOR DEC(__ti_minor__) + # define COMPILER_VERSION_PATCH DEC(__ti_patchlevel__) +# define COMPILER_VERSION_INTERNAL DEC(__ti_version__) + +#elif defined(__clang__) +# define COMPILER_ID "Clang" +# if defined(_MSC_VER) +# define SIMULATE_ID "MSVC" +# endif +# define COMPILER_VERSION_MAJOR DEC(__clang_major__) +# define COMPILER_VERSION_MINOR DEC(__clang_minor__) +# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__) +# if defined(_MSC_VER) + /* _MSC_VER = VVRR */ +# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) +# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) +# endif + +#elif defined(__LCC__) && (defined(__GNUC__) || defined(__GNUG__) || defined(__MCST__)) +# define COMPILER_ID "LCC" +# define COMPILER_VERSION_MAJOR DEC(__LCC__ / 100) +# define COMPILER_VERSION_MINOR DEC(__LCC__ % 100) +# if defined(__LCC_MINOR__) +# define COMPILER_VERSION_PATCH DEC(__LCC_MINOR__) +# endif +# if defined(__GNUC__) && defined(__GNUC_MINOR__) +# define SIMULATE_ID "GNU" +# define SIMULATE_VERSION_MAJOR DEC(__GNUC__) +# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__) +# if defined(__GNUC_PATCHLEVEL__) +# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +# endif +# endif + +#elif defined(__GNUC__) || defined(__GNUG__) +# define COMPILER_ID "GNU" +# if defined(__GNUC__) +# define COMPILER_VERSION_MAJOR DEC(__GNUC__) +# else +# define COMPILER_VERSION_MAJOR DEC(__GNUG__) +# endif +# if defined(__GNUC_MINOR__) +# define COMPILER_VERSION_MINOR DEC(__GNUC_MINOR__) +# endif +# if defined(__GNUC_PATCHLEVEL__) +# define COMPILER_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) +# endif + +#elif defined(_MSC_VER) +# define COMPILER_ID "MSVC" + /* _MSC_VER = VVRR */ +# define COMPILER_VERSION_MAJOR DEC(_MSC_VER / 100) +# define COMPILER_VERSION_MINOR DEC(_MSC_VER % 100) +# if defined(_MSC_FULL_VER) +# if _MSC_VER >= 1400 + /* _MSC_FULL_VER = VVRRPPPPP */ +# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 100000) +# else + /* _MSC_FULL_VER = VVRRPPPP */ +# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 10000) +# endif +# endif +# if defined(_MSC_BUILD) +# define COMPILER_VERSION_TWEAK DEC(_MSC_BUILD) +# endif + +#elif defined(_ADI_COMPILER) +# define COMPILER_ID "ADSP" +#if defined(__VERSIONNUM__) + /* __VERSIONNUM__ = 0xVVRRPPTT */ +# define COMPILER_VERSION_MAJOR DEC(__VERSIONNUM__ >> 24 & 0xFF) +# define COMPILER_VERSION_MINOR DEC(__VERSIONNUM__ >> 16 & 0xFF) +# define COMPILER_VERSION_PATCH DEC(__VERSIONNUM__ >> 8 & 0xFF) +# define COMPILER_VERSION_TWEAK DEC(__VERSIONNUM__ & 0xFF) +#endif + +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) +# define COMPILER_ID "IAR" +# if defined(__VER__) && defined(__ICCARM__) +# define COMPILER_VERSION_MAJOR DEC((__VER__) / 1000000) +# define COMPILER_VERSION_MINOR DEC(((__VER__) / 1000) % 1000) +# define COMPILER_VERSION_PATCH DEC((__VER__) % 1000) +# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) +# elif defined(__VER__) && (defined(__ICCAVR__) || defined(__ICCRX__) || defined(__ICCRH850__) || defined(__ICCRL78__) || defined(__ICC430__) || defined(__ICCRISCV__) || defined(__ICCV850__) || defined(__ICC8051__) || defined(__ICCSTM8__)) +# define COMPILER_VERSION_MAJOR DEC((__VER__) / 100) +# define COMPILER_VERSION_MINOR DEC((__VER__) - (((__VER__) / 100)*100)) +# define COMPILER_VERSION_PATCH DEC(__SUBVERSION__) +# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) +# endif + + +/* These compilers are either not known or too old to define an + identification macro. Try to identify the platform and guess that + it is the native compiler. */ +#elif defined(__hpux) || defined(__hpua) +# define COMPILER_ID "HP" + +#else /* unknown compiler */ +# define COMPILER_ID "" +#endif + +/* Construct the string literal in pieces to prevent the source from + getting matched. Store it in a pointer rather than an array + because some compilers will just produce instructions to fill the + array rather than assigning a pointer to a static array. */ +char const* info_compiler = "INFO" ":" "compiler[" COMPILER_ID "]"; +#ifdef SIMULATE_ID +char const* info_simulate = "INFO" ":" "simulate[" SIMULATE_ID "]"; +#endif + +#ifdef __QNXNTO__ +char const* qnxnto = "INFO" ":" "qnxnto[]"; +#endif + +#if defined(__CRAYXT_COMPUTE_LINUX_TARGET) +char const *info_cray = "INFO" ":" "compiler_wrapper[CrayPrgEnv]"; +#endif + +#define STRINGIFY_HELPER(X) #X +#define STRINGIFY(X) STRINGIFY_HELPER(X) + +/* Identify known platforms by name. */ +#if defined(__linux) || defined(__linux__) || defined(linux) +# define PLATFORM_ID "Linux" + +#elif defined(__MSYS__) +# define PLATFORM_ID "MSYS" + +#elif defined(__CYGWIN__) +# define PLATFORM_ID "Cygwin" + +#elif defined(__MINGW32__) +# define PLATFORM_ID "MinGW" + +#elif defined(__APPLE__) +# define PLATFORM_ID "Darwin" + +#elif defined(_WIN32) || defined(__WIN32__) || defined(WIN32) +# define PLATFORM_ID "Windows" + +#elif defined(__FreeBSD__) || defined(__FreeBSD) +# define PLATFORM_ID "FreeBSD" + +#elif defined(__NetBSD__) || defined(__NetBSD) +# define PLATFORM_ID "NetBSD" + +#elif defined(__OpenBSD__) || defined(__OPENBSD) +# define PLATFORM_ID "OpenBSD" + +#elif defined(__sun) || defined(sun) +# define PLATFORM_ID "SunOS" + +#elif defined(_AIX) || defined(__AIX) || defined(__AIX__) || defined(__aix) || defined(__aix__) +# define PLATFORM_ID "AIX" + +#elif defined(__hpux) || defined(__hpux__) +# define PLATFORM_ID "HP-UX" + +#elif defined(__HAIKU__) +# define PLATFORM_ID "Haiku" + +#elif defined(__BeOS) || defined(__BEOS__) || defined(_BEOS) +# define PLATFORM_ID "BeOS" + +#elif defined(__QNX__) || defined(__QNXNTO__) +# define PLATFORM_ID "QNX" + +#elif defined(__tru64) || defined(_tru64) || defined(__TRU64__) +# define PLATFORM_ID "Tru64" + +#elif defined(__riscos) || defined(__riscos__) +# define PLATFORM_ID "RISCos" + +#elif defined(__sinix) || defined(__sinix__) || defined(__SINIX__) +# define PLATFORM_ID "SINIX" + +#elif defined(__UNIX_SV__) +# define PLATFORM_ID "UNIX_SV" + +#elif defined(__bsdos__) +# define PLATFORM_ID "BSDOS" + +#elif defined(_MPRAS) || defined(MPRAS) +# define PLATFORM_ID "MP-RAS" + +#elif defined(__osf) || defined(__osf__) +# define PLATFORM_ID "OSF1" + +#elif defined(_SCO_SV) || defined(SCO_SV) || defined(sco_sv) +# define PLATFORM_ID "SCO_SV" + +#elif defined(__ultrix) || defined(__ultrix__) || defined(_ULTRIX) +# define PLATFORM_ID "ULTRIX" + +#elif defined(__XENIX__) || defined(_XENIX) || defined(XENIX) +# define PLATFORM_ID "Xenix" + +#elif defined(__WATCOMC__) +# if defined(__LINUX__) +# define PLATFORM_ID "Linux" + +# elif defined(__DOS__) +# define PLATFORM_ID "DOS" + +# elif defined(__OS2__) +# define PLATFORM_ID "OS2" + +# elif defined(__WINDOWS__) +# define PLATFORM_ID "Windows3x" + +# elif defined(__VXWORKS__) +# define PLATFORM_ID "VxWorks" + +# else /* unknown platform */ +# define PLATFORM_ID +# endif + +#elif defined(__INTEGRITY) +# if defined(INT_178B) +# define PLATFORM_ID "Integrity178" + +# else /* regular Integrity */ +# define PLATFORM_ID "Integrity" +# endif + +# elif defined(_ADI_COMPILER) +# define PLATFORM_ID "ADSP" + +#else /* unknown platform */ +# define PLATFORM_ID + +#endif + +/* For windows compilers MSVC and Intel we can determine + the architecture of the compiler being used. This is because + the compilers do not have flags that can change the architecture, + but rather depend on which compiler is being used +*/ +#if defined(_WIN32) && defined(_MSC_VER) +# if defined(_M_IA64) +# define ARCHITECTURE_ID "IA64" + +# elif defined(_M_ARM64EC) +# define ARCHITECTURE_ID "ARM64EC" + +# elif defined(_M_X64) || defined(_M_AMD64) +# define ARCHITECTURE_ID "x64" + +# elif defined(_M_IX86) +# define ARCHITECTURE_ID "X86" + +# elif defined(_M_ARM64) +# define ARCHITECTURE_ID "ARM64" + +# elif defined(_M_ARM) +# if _M_ARM == 4 +# define ARCHITECTURE_ID "ARMV4I" +# elif _M_ARM == 5 +# define ARCHITECTURE_ID "ARMV5I" +# else +# define ARCHITECTURE_ID "ARMV" STRINGIFY(_M_ARM) +# endif + +# elif defined(_M_MIPS) +# define ARCHITECTURE_ID "MIPS" + +# elif defined(_M_SH) +# define ARCHITECTURE_ID "SHx" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__WATCOMC__) +# if defined(_M_I86) +# define ARCHITECTURE_ID "I86" + +# elif defined(_M_IX86) +# define ARCHITECTURE_ID "X86" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) +# if defined(__ICCARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__ICCRX__) +# define ARCHITECTURE_ID "RX" + +# elif defined(__ICCRH850__) +# define ARCHITECTURE_ID "RH850" + +# elif defined(__ICCRL78__) +# define ARCHITECTURE_ID "RL78" + +# elif defined(__ICCRISCV__) +# define ARCHITECTURE_ID "RISCV" + +# elif defined(__ICCAVR__) +# define ARCHITECTURE_ID "AVR" + +# elif defined(__ICC430__) +# define ARCHITECTURE_ID "MSP430" + +# elif defined(__ICCV850__) +# define ARCHITECTURE_ID "V850" + +# elif defined(__ICC8051__) +# define ARCHITECTURE_ID "8051" + +# elif defined(__ICCSTM8__) +# define ARCHITECTURE_ID "STM8" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__ghs__) +# if defined(__PPC64__) +# define ARCHITECTURE_ID "PPC64" + +# elif defined(__ppc__) +# define ARCHITECTURE_ID "PPC" + +# elif defined(__ARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__x86_64__) +# define ARCHITECTURE_ID "x64" + +# elif defined(__i386__) +# define ARCHITECTURE_ID "X86" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__clang__) && defined(__ti__) +# if defined(__ARM_ARCH) +# define ARCHITECTURE_ID "Arm" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +#elif defined(__TI_COMPILER_VERSION__) +# if defined(__TI_ARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__MSP430__) +# define ARCHITECTURE_ID "MSP430" + +# elif defined(__TMS320C28XX__) +# define ARCHITECTURE_ID "TMS320C28x" + +# elif defined(__TMS320C6X__) || defined(_TMS320C6X) +# define ARCHITECTURE_ID "TMS320C6x" + +# else /* unknown architecture */ +# define ARCHITECTURE_ID "" +# endif + +# elif defined(__ADSPSHARC__) +# define ARCHITECTURE_ID "SHARC" + +# elif defined(__ADSPBLACKFIN__) +# define ARCHITECTURE_ID "Blackfin" + +#elif defined(__TASKING__) + +# if defined(__CTC__) || defined(__CPTC__) +# define ARCHITECTURE_ID "TriCore" + +# elif defined(__CMCS__) +# define ARCHITECTURE_ID "MCS" + +# elif defined(__CARM__) +# define ARCHITECTURE_ID "ARM" + +# elif defined(__CARC__) +# define ARCHITECTURE_ID "ARC" + +# elif defined(__C51__) +# define ARCHITECTURE_ID "8051" + +# elif defined(__CPCP__) +# define ARCHITECTURE_ID "PCP" + +# else +# define ARCHITECTURE_ID "" +# endif + +#else +# define ARCHITECTURE_ID +#endif + +/* Convert integer to decimal digit literals. */ +#define DEC(n) \ + ('0' + (((n) / 10000000)%10)), \ + ('0' + (((n) / 1000000)%10)), \ + ('0' + (((n) / 100000)%10)), \ + ('0' + (((n) / 10000)%10)), \ + ('0' + (((n) / 1000)%10)), \ + ('0' + (((n) / 100)%10)), \ + ('0' + (((n) / 10)%10)), \ + ('0' + ((n) % 10)) + +/* Convert integer to hex digit literals. */ +#define HEX(n) \ + ('0' + ((n)>>28 & 0xF)), \ + ('0' + ((n)>>24 & 0xF)), \ + ('0' + ((n)>>20 & 0xF)), \ + ('0' + ((n)>>16 & 0xF)), \ + ('0' + ((n)>>12 & 0xF)), \ + ('0' + ((n)>>8 & 0xF)), \ + ('0' + ((n)>>4 & 0xF)), \ + ('0' + ((n) & 0xF)) + +/* Construct a string literal encoding the version number. */ +#ifdef COMPILER_VERSION +char const* info_version = "INFO" ":" "compiler_version[" COMPILER_VERSION "]"; + +/* Construct a string literal encoding the version number components. */ +#elif defined(COMPILER_VERSION_MAJOR) +char const info_version[] = { + 'I', 'N', 'F', 'O', ':', + 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','[', + COMPILER_VERSION_MAJOR, +# ifdef COMPILER_VERSION_MINOR + '.', COMPILER_VERSION_MINOR, +# ifdef COMPILER_VERSION_PATCH + '.', COMPILER_VERSION_PATCH, +# ifdef COMPILER_VERSION_TWEAK + '.', COMPILER_VERSION_TWEAK, +# endif +# endif +# endif + ']','\0'}; +#endif + +/* Construct a string literal encoding the internal version number. */ +#ifdef COMPILER_VERSION_INTERNAL +char const info_version_internal[] = { + 'I', 'N', 'F', 'O', ':', + 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','_', + 'i','n','t','e','r','n','a','l','[', + COMPILER_VERSION_INTERNAL,']','\0'}; +#elif defined(COMPILER_VERSION_INTERNAL_STR) +char const* info_version_internal = "INFO" ":" "compiler_version_internal[" COMPILER_VERSION_INTERNAL_STR "]"; +#endif + +/* Construct a string literal encoding the version number components. */ +#ifdef SIMULATE_VERSION_MAJOR +char const info_simulate_version[] = { + 'I', 'N', 'F', 'O', ':', + 's','i','m','u','l','a','t','e','_','v','e','r','s','i','o','n','[', + SIMULATE_VERSION_MAJOR, +# ifdef SIMULATE_VERSION_MINOR + '.', SIMULATE_VERSION_MINOR, +# ifdef SIMULATE_VERSION_PATCH + '.', SIMULATE_VERSION_PATCH, +# ifdef SIMULATE_VERSION_TWEAK + '.', SIMULATE_VERSION_TWEAK, +# endif +# endif +# endif + ']','\0'}; +#endif + +/* Construct the string literal in pieces to prevent the source from + getting matched. Store it in a pointer rather than an array + because some compilers will just produce instructions to fill the + array rather than assigning a pointer to a static array. */ +char const* info_platform = "INFO" ":" "platform[" PLATFORM_ID "]"; +char const* info_arch = "INFO" ":" "arch[" ARCHITECTURE_ID "]"; + + + +#if defined(__INTEL_COMPILER) && defined(_MSVC_LANG) && _MSVC_LANG < 201403L +# if defined(__INTEL_CXX11_MODE__) +# if defined(__cpp_aggregate_nsdmi) +# define CXX_STD 201402L +# else +# define CXX_STD 201103L +# endif +# else +# define CXX_STD 199711L +# endif +#elif defined(_MSC_VER) && defined(_MSVC_LANG) +# define CXX_STD _MSVC_LANG +#else +# define CXX_STD __cplusplus +#endif + +const char* info_language_standard_default = "INFO" ":" "standard_default[" +#if CXX_STD > 202002L + "23" +#elif CXX_STD > 201703L + "20" +#elif CXX_STD >= 201703L + "17" +#elif CXX_STD >= 201402L + "14" +#elif CXX_STD >= 201103L + "11" +#else + "98" +#endif +"]"; + +const char* info_language_extensions_default = "INFO" ":" "extensions_default[" +#if (defined(__clang__) || defined(__GNUC__) || defined(__xlC__) || \ + defined(__TI_COMPILER_VERSION__)) && \ + !defined(__STRICT_ANSI__) + "ON" +#else + "OFF" +#endif +"]"; + +/*--------------------------------------------------------------------------*/ + +int main(int argc, char* argv[]) +{ + int require = 0; + require += info_compiler[argc]; + require += info_platform[argc]; + require += info_arch[argc]; +#ifdef COMPILER_VERSION_MAJOR + require += info_version[argc]; +#endif +#ifdef COMPILER_VERSION_INTERNAL + require += info_version_internal[argc]; +#endif +#ifdef SIMULATE_ID + require += info_simulate[argc]; +#endif +#ifdef SIMULATE_VERSION_MAJOR + require += info_simulate_version[argc]; +#endif +#if defined(__CRAYXT_COMPUTE_LINUX_TARGET) + require += info_cray[argc]; +#endif + require += info_language_standard_default[argc]; + require += info_language_extensions_default[argc]; + (void)argv; + return require; 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(find_package): + By not providing "FindSparta.cmake" in CMAKE_MODULE_PATH this project has + asked CMake to find a package configuration file provided by "Sparta", but + CMake did not find one. + + Could not find a package configuration file provided by "Sparta" with any + of the following names: + + SpartaConfig.cmake + sparta-config.cmake + + Add the installation prefix of "Sparta" to CMAKE_PREFIX_PATH or set + "Sparta_DIR" to a directory containing one of the above files. If "Sparta" + provides a separate development package or SDK, be sure it has been + installed. + + +-- Configuring incomplete, errors occurred! diff --git a/cmake-build-debug/CMakeFiles/clion-environment.txt b/cmake-build-debug/CMakeFiles/clion-environment.txt new file mode 100644 index 0000000000000000000000000000000000000000..cd47557a2a4555afbb8639481d27d02a83eff8bc GIT binary patch literal 112 zcmWH^&(8@?EwNHC)H6`f$jMJm%+d5OD9OyvE4EVL;({@CU7UR#y=4.5=2_gnu - binutils_impl_linux-64>=2.39=he00db2b_1 - binutils_linux-64>=2.39=h5fc0e48_11 + - bison>=3.8 - boost>=1.76.0=py310h7c3ba0c_1 - boost-cpp>=1.76.0=h312852a_1 - bzip2>=1.0.8=h7f98852_4 @@ -19,6 +20,7 @@ dependencies: - curl>=7.87.0=h6312ad2_0 - doxygen>=1.8.20=had0d8f1_0 - expat>=2.5.0=h27087fc_0 + - flex>=2.6 - gcc>=10.4.0=hb92f740_13 - gcc_impl_linux-64>=10.4.0=h5231bdf_19 - gcc_linux-64>=10.4.0=h9215b83_11 diff --git a/core/BranchPredIF.hpp b/core/BranchPredIF.hpp new file mode 100644 index 00000000..775521a1 --- /dev/null +++ b/core/BranchPredIF.hpp @@ -0,0 +1,45 @@ +// -*- C++ -*- + +//! +//! \file BranchPred.hpp +//! \brief Definition of Branch Prediction API +//! + +/* + * This file defines the Branch Prediction API. + * The goal is to define an API that is generic and yet flexible enough to support various + * branch prediction microarchitecture. + * To the end, we envision a generic branch predictor as a black box with following inputs + * and outputs: + * * A generic Prediction output + * * A generic Prediction input + * * A generic Update input + * + * The generic branch predictor may have two operations: + * * getPrediction: produces Prediction output based on the Prediction input. + * * updatePredictor: updates Predictor with Update input. + * + * It is intended that an implementation of branch predictor must also specify + * implementations of Prediction output, Prediction input and Update input, along with + * implementations of getPrediction and updatePredictor operations. + * */ +#pragma once + +namespace olympia +{ +namespace BranchPredictor +{ + + template + class BranchPredictorIF + { + public: + // TODO: create constexpr for bytes per compressed and uncompressed inst + static constexpr uint8_t bytes_per_inst = 4; + virtual ~BranchPredictorIF() { }; + virtual PredictionT getPrediction(const InputT &) = 0; + virtual void updatePredictor(const UpdateT &) = 0; + }; + +} // namespace BranchPredictor +} // namespace olympia diff --git a/core/CMakeLists.txt b/core/CMakeLists.txt index fdf462b1..47657c75 100644 --- a/core/CMakeLists.txt +++ b/core/CMakeLists.txt @@ -1,9 +1,12 @@ project (core) add_library(core + FusionDecode.cpp Core.cpp + SimpleBranchPred.cpp ICache.cpp Fetch.cpp Decode.cpp + VectorUopGenerator.cpp Rename.cpp Dispatch.cpp Dispatcher.cpp diff --git a/core/CPUFactories.hpp b/core/CPUFactories.hpp index 28f90dae..2947ba89 100644 --- a/core/CPUFactories.hpp +++ b/core/CPUFactories.hpp @@ -8,6 +8,7 @@ #include "ICache.hpp" #include "Fetch.hpp" #include "Decode.hpp" +#include "VectorUopGenerator.hpp" #include "Rename.hpp" #include "Dispatch.hpp" #include "Execute.hpp" @@ -52,6 +53,10 @@ namespace olympia{ sparta::ResourceFactory decode_rf; + //! \brief Resource Factory to build a VectorUopGenerator + sparta::ResourceFactory vec_uop_gen_rf; + //! \brief Resource Factory to build a Rename Unit RenameFactory rename_rf; diff --git a/core/CPUTopology.cpp b/core/CPUTopology.cpp index 2f3f3b79..c2fc310a 100644 --- a/core/CPUTopology.cpp +++ b/core/CPUTopology.cpp @@ -51,6 +51,14 @@ olympia::CoreTopologySimple::CoreTopologySimple(){ sparta::TreeNode::GROUP_IDX_NONE, &factories->decode_rf }, + { + "vec_uop_gen", + "cpu.core*.decode", + "Vector Uop Generator", + sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, + &factories->vec_uop_gen_rf + }, { "rename", "cpu.core*", @@ -413,8 +421,15 @@ void olympia::CoreTopologySimple::bindTree(sparta::RootTreeNode* root_node) pipe_target_end = stoi(iq[1]); } pipe_target_end++; + const std::string vset_in_decode = + core_node + ".decode." + "ports.in_vset_inst"; for (int pipe_idx = pipe_target_start; pipe_idx < pipe_target_end; ++pipe_idx) { + // check to ensure no duplicate pipe definitions + std::set unique_pipe_def_check(pipelines[pipe_idx].begin(), pipelines[pipe_idx].end()); + sparta_assert(unique_pipe_def_check.size() == pipelines[pipe_idx].size(), + "Duplicate pipe definitions, double check yaml file") + std::string unit_name = "exe" + std::to_string(pipe_idx); if (exe_pipe_rename.size() > 0) { @@ -427,6 +442,16 @@ void olympia::CoreTopologySimple::bindTree(sparta::RootTreeNode* root_node) const std::string exe_pipe_out = core_node + ".execute." + unit_name + ".ports.out_execute_pipe"; bind_ports(exe_pipe_in, exe_pipe_out); + + for(uint32_t i = 0; i < pipelines[pipe_idx].size(); ++i){ + if(pipelines[pipe_idx][i] == "vset"){ + // only bind execute pipe -> decode port for an issue queue if it has a vset pipe + const std::string exe_vset_out = + core_node + ".execute." + unit_name + ".ports.out_vset"; + bind_ports(vset_in_decode, exe_vset_out); + break; // break after we find a vset in pipeline def + } + } } const std::string exe_flush_in = diff --git a/core/CacheFuncModel.hpp b/core/CacheFuncModel.hpp index 61f8e2e8..749fa1b1 100644 --- a/core/CacheFuncModel.hpp +++ b/core/CacheFuncModel.hpp @@ -59,7 +59,9 @@ namespace olympia bool isValid() const { return valid_; } // Required by SimpleCache2 - void setModified(bool m) { (void) m; } + void setModified(bool m) { modified_ = m; } + + bool isModified() const { return modified_; } // Required by SimpleCache2 bool read(uint64_t offset, uint32_t size, uint32_t *buf) const @@ -84,6 +86,7 @@ namespace olympia private: uint64_t line_size_ = 0; bool valid_ = false; + bool modified_ = false; }; // class SimpleCacheLine diff --git a/core/CoreTypes.hpp b/core/CoreTypes.hpp index facd808f..4e37db57 100644 --- a/core/CoreTypes.hpp +++ b/core/CoreTypes.hpp @@ -9,29 +9,21 @@ namespace olympia::core_types using RegisterBitMask = sparta::Scoreboard::RegisterBitMask; //! Register file types - enum RegFile : uint8_t { + enum RegFile : uint8_t + { RF_INTEGER, RF_FLOAT, + RF_VECTOR, RF_INVALID, N_REGFILES = RF_INVALID }; - static inline const char * const regfile_names[] = { - "integer", - "float" - }; - - static inline const char * const issue_queue_types[] = { - "alu", - "fpu", - "br" - }; + static inline const char* const regfile_names[] = {"integer", "float", "vector"}; inline std::ostream & operator<<(std::ostream & os, const RegFile & rf) { - sparta_assert(rf < RegFile::RF_INVALID, - "RF index off into the weeds " << rf); + sparta_assert(rf < RegFile::RF_INVALID, "RF index off into the weeds " << rf); os << regfile_names[rf]; return os; } -} +} // namespace olympia::core_types diff --git a/core/CoreUtils.hpp b/core/CoreUtils.hpp index e4e0521b..00e33a90 100644 --- a/core/CoreUtils.hpp +++ b/core/CoreUtils.hpp @@ -28,7 +28,8 @@ namespace olympia::coreutils {mavis::InstMetaData::OperandTypes::DOUBLE, core_types::RegFile::RF_FLOAT}, {mavis::InstMetaData::OperandTypes::WORD, core_types::RegFile::RF_INTEGER}, {mavis::InstMetaData::OperandTypes::LONG, core_types::RegFile::RF_INTEGER}, - {mavis::InstMetaData::OperandTypes::QUAD, core_types::RegFile::RF_INTEGER}}; + {mavis::InstMetaData::OperandTypes::QUAD, core_types::RegFile::RF_INTEGER}, + {mavis::InstMetaData::OperandTypes::VECTOR, core_types::RegFile::RF_VECTOR}}; if (auto match = mavis_optype_to_regfile.find(reg.operand_type); match != mavis_optype_to_regfile.end()) { diff --git a/core/DCache.cpp b/core/DCache.cpp index 367bd60e..5c2331b3 100644 --- a/core/DCache.cpp +++ b/core/DCache.cpp @@ -1,29 +1,61 @@ #include "DCache.hpp" +#include "OlympiaAllocators.hpp" -namespace olympia { +namespace olympia +{ const char DCache::name[] = "cache"; - DCache::DCache(sparta::TreeNode *n, const CacheParameterSet *p) : - sparta::Unit(n), - l1_always_hit_(p->l1_always_hit), - cache_latency_(p->cache_latency) { + DCache::DCache(sparta::TreeNode* n, const CacheParameterSet* p) : + sparta::Unit(n), + l1_always_hit_(p->l1_always_hit), + cache_line_size_(p->l1_line_size), + num_mshr_entries_(p->mshr_entries), + mshr_file_("mshr_file", p->mshr_entries, getClock()), + mshr_entry_allocator_( + sparta::notNull(OlympiaAllocators::getOlympiaAllocators(n))->mshr_entry_allocator) + { + sparta_assert(num_mshr_entries_ > 0, "There must be atleast 1 MSHR entry"); + + in_lsu_lookup_req_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(DCache, receiveMemReqFromLSU_, MemoryAccessInfoPtr)); + + in_l2cache_resp_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(DCache, receiveRespFromL2Cache_, MemoryAccessInfoPtr)); + + in_l2cache_credits_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getCreditsFromL2Cache_, uint32_t)); + + in_lsu_lookup_req_.registerConsumerEvent(in_l2_cache_resp_receive_event_); + in_l2cache_resp_.registerConsumerEvent(in_l2_cache_resp_receive_event_); + setupL1Cache_(p); + + // Pipeline config + cache_pipeline_.enableCollection(n); + cache_pipeline_.performOwnUpdates(); + cache_pipeline_.setContinuing(true); + + // Pipeline Handlers + cache_pipeline_.registerHandlerAtStage(static_cast(PipelineStage::LOOKUP), + CREATE_SPARTA_HANDLER(DCache, handleLookup_)); - in_lsu_lookup_req_.registerConsumerHandler - (CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getInstsFromLSU_, MemoryAccessInfoPtr)); + cache_pipeline_.registerHandlerAtStage(static_cast(PipelineStage::DATA_READ), + CREATE_SPARTA_HANDLER(DCache, handleDataRead_)); - in_l2cache_credits_.registerConsumerHandler - (CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getCreditsFromL2Cache_, uint32_t)); + cache_pipeline_.registerHandlerAtStage(static_cast(PipelineStage::DEALLOCATE), + CREATE_SPARTA_HANDLER(DCache, handleDeallocate_)); - in_l2cache_resp_.registerConsumerHandler - (CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getRespFromL2Cache_, MemoryAccessInfoPtr)); + mshr_file_.enableCollection(n); + } - // DL1 cache config + void DCache::setupL1Cache_(const CacheParameterSet* p) + { // DL1 cache config const uint32_t l1_line_size = p->l1_line_size; const uint32_t l1_size_kb = p->l1_size_kb; const uint32_t l1_associativity = p->l1_associativity; - std::unique_ptr repl(new sparta::cache::TreePLRUReplacement - (l1_associativity)); + std::unique_ptr repl( + new sparta::cache::TreePLRUReplacement(l1_associativity)); l1_cache_.reset(new CacheFuncModel(getContainer(), l1_size_kb, l1_line_size, *repl)); + addr_decoder_ = l1_cache_->getAddrDecoder(); } // Reload cache line @@ -35,7 +67,7 @@ namespace olympia { ILOG("DCache reload complete!"); } - // Access DCache + // Access L1Cache bool DCache::dataLookup_(const MemoryAccessInfoPtr & mem_access_info_ptr) { const InstPtr & inst_ptr = mem_access_info_ptr->getInstPtr(); @@ -43,28 +75,34 @@ namespace olympia { bool cache_hit = false; - if (l1_always_hit_) { + if (l1_always_hit_) + { cache_hit = true; } - else { + else + { auto cache_line = l1_cache_->peekLine(phyAddr); cache_hit = (cache_line != nullptr) && cache_line->isValid(); // Update MRU replacement state if DCache HIT - if (cache_hit) { + if (cache_hit) + { l1_cache_->touchMRU(*cache_line); } } - if (l1_always_hit_) { + if (l1_always_hit_) + { ILOG("DL1 DCache HIT all the time: phyAddr=0x" << std::hex << phyAddr); dl1_cache_hits_++; } - else if (cache_hit) { + else if (cache_hit) + { ILOG("DL1 DCache HIT: phyAddr=0x" << std::hex << phyAddr); dl1_cache_hits_++; } - else { + else + { ILOG("DL1 DCache MISS: phyAddr=0x" << std::hex << phyAddr); dl1_cache_misses_++; } @@ -72,37 +110,202 @@ namespace olympia { return cache_hit; } - void DCache::getInstsFromLSU_(const MemoryAccessInfoPtr &memory_access_info_ptr){ - const bool hit = dataLookup_(memory_access_info_ptr); - if(hit){ - memory_access_info_ptr->setCacheState(MemoryAccessInfo::CacheState::HIT); - }else{ - memory_access_info_ptr->setCacheState(MemoryAccessInfo::CacheState::MISS); - // DCache is blocking for now. Busy is set on miss, until the miss is - // resolved by the L2. - // For NB behaviour: Poll on dcache_l2cache_credits_ > 0 which means - // that L2Cache can accept requests from DCache. - // Provide a corresponsing backpressure mechanism up the pipeline. - if(!busy_) { - busy_ = true; - cache_pending_inst_ = memory_access_info_ptr; - out_l2cache_req_.send(cache_pending_inst_); - - // Set the --dcache_l2cache_credits_ here. + // The lookup stage + void DCache::handleLookup_() + { + ILOG("Lookup stage"); + const auto stage_id = static_cast(PipelineStage::LOOKUP); + const MemoryAccessInfoPtr & mem_access_info_ptr = cache_pipeline_[stage_id]; + ILOG(mem_access_info_ptr << " in Lookup stage"); + // If the mem request is a refill we dont do anything in the lookup stage + if (mem_access_info_ptr->isRefill()) + { + ILOG("Incoming cache refill " << mem_access_info_ptr); + return; + } + + const bool hit = dataLookup_(mem_access_info_ptr); + ILOG(mem_access_info_ptr << " performing lookup " << hit); + if (hit) + { + mem_access_info_ptr->setCacheState(MemoryAccessInfo::CacheState::HIT); + out_lsu_lookup_ack_.send(mem_access_info_ptr); + return; + } + + // Check MSHR Entries for address match + const auto & mshr_itb = mem_access_info_ptr->getMSHRInfoIterator(); + + if (!mshr_itb.isValid() && mshr_file_.numFree() == 0) + { + // Should be Nack but miss should work for now + mem_access_info_ptr->setCacheState(MemoryAccessInfo::CacheState::MISS); + out_lsu_lookup_ack_.send(mem_access_info_ptr); + return; + } + + if (!mshr_itb.isValid()) + { + if (!mem_access_info_ptr->getMSHRInfoIterator().isValid()) + { + ILOG("Creating new MSHR Entry " << mem_access_info_ptr); + allocateMSHREntry_(mem_access_info_ptr); + } + } + + const auto & mshr_it = mem_access_info_ptr->getMSHRInfoIterator(); + const uint64_t block_addr = getBlockAddr(mem_access_info_ptr); + const bool data_arrived = (*mshr_it)->isDataArrived(); + const bool is_store_inst = mem_access_info_ptr->getInstPtr()->isStoreInst(); + + // All ST are considered Hit + if (is_store_inst) + { + // Update Line fill buffer only if ST + ILOG("Write to Line fill buffer (ST), block address:0x" << std::hex << block_addr); + (*mshr_it)->setModified(true); + (*mshr_it)->setMemRequest(mem_access_info_ptr); + mem_access_info_ptr->setCacheState(MemoryAccessInfo::CacheState::HIT); + } + else if (data_arrived) + { + ILOG("Hit on Line fill buffer (LD), block address:0x" << std::hex << block_addr); + mem_access_info_ptr->setCacheState(MemoryAccessInfo::CacheState::HIT); + } + else + { + // Enqueue Load in LMQ + ILOG("Load miss inst to LMQ; block address:0x" << std::hex << block_addr); + (*mshr_it)->setMemRequest(mem_access_info_ptr); + mem_access_info_ptr->setCacheState(MemoryAccessInfo::CacheState::MISS); + } + out_lsu_lookup_ack_.send(mem_access_info_ptr); + } + + uint64_t DCache::getBlockAddr(const MemoryAccessInfoPtr & mem_access_info_ptr) const + { + const InstPtr & inst_ptr = mem_access_info_ptr->getInstPtr(); + const auto & inst_target_addr = inst_ptr->getRAdr(); + return addr_decoder_->calcBlockAddr(inst_target_addr); + } + + // Data read stage + void DCache::handleDataRead_() + { + ILOG("Data Read stage"); + const auto stage_id = static_cast(PipelineStage::DATA_READ); + const MemoryAccessInfoPtr & mem_access_info_ptr = cache_pipeline_[stage_id]; + ILOG(mem_access_info_ptr << " in read stage"); + if (mem_access_info_ptr->isRefill()) + { + reloadCache_(mem_access_info_ptr->getPhyAddr()); + return; + } + + if (mem_access_info_ptr->isCacheHit()) + { + mem_access_info_ptr->setDataReady(true); + } + else + { + if (!l2cache_busy_) + { + out_l2cache_req_.send(mem_access_info_ptr); + l2cache_busy_ = true; + } + else + { + uev_mshr_request_.schedule(sparta::Clock::Cycle(1)); + } + } + out_lsu_lookup_ack_.send(mem_access_info_ptr); + } + + void DCache::mshrRequest_() + { + ILOG("Send mshr req"); + if (!l2cache_busy_) + { + auto iter = mshr_file_.begin(); + while (iter != mshr_file_.end()) + { + + if (iter.isValid()) + { + const auto & mshr_entry = *iter; + auto mem_info = mshr_entry->getMemRequest(); + if (mshr_entry->isValid() && !mshr_entry->isDataArrived() && mem_info) + { + ILOG("Sending mshr request when not busy " << mem_info); + out_l2cache_req_.send(mem_info); + l2cache_busy_ = true; + break; + } + } + ++iter; + } + } + } + + void DCache::handleDeallocate_() + { + ILOG("Data Dellocate stage"); + const auto stage_id = static_cast(PipelineStage::DEALLOCATE); + const MemoryAccessInfoPtr & mem_access_info_ptr = cache_pipeline_[stage_id]; + ILOG(mem_access_info_ptr << " in deallocate stage"); + if (mem_access_info_ptr->isRefill()) + { + const auto & mshr_it = mem_access_info_ptr->getMSHRInfoIterator(); + if (mshr_it.isValid()) + { + MemoryAccessInfoPtr dependant_load_inst = (*mshr_it)->getMemRequest(); + out_lsu_lookup_ack_.send(dependant_load_inst); + + ILOG("Removing mshr entry for " << mem_access_info_ptr); + mshr_file_.erase(mem_access_info_ptr->getMSHRInfoIterator()); } + return; } + ILOG("Deallocating pipeline for " << mem_access_info_ptr); + } + + void DCache::receiveMemReqFromLSU_(const MemoryAccessInfoPtr & memory_access_info_ptr) + { + ILOG("Received memory access request from LSU " << memory_access_info_ptr); out_lsu_lookup_ack_.send(memory_access_info_ptr); + in_l2_cache_resp_receive_event_.schedule(); + lsu_mem_access_info_ = memory_access_info_ptr; } - void DCache::getRespFromL2Cache_(const MemoryAccessInfoPtr &memory_access_info_ptr) { - out_lsu_lookup_req_.send(cache_pending_inst_); - reloadCache_(memory_access_info_ptr->getPhyAddr()); - cache_pending_inst_.reset(); - busy_ = false; + void DCache::receiveRespFromL2Cache_(const MemoryAccessInfoPtr & memory_access_info_ptr) + { + ILOG("Received cache refill " << memory_access_info_ptr); + // We mark the mem access to refill, this could be moved to the lower level caches later + memory_access_info_ptr->setIsRefill(true); + l2_mem_access_info_ = memory_access_info_ptr; + const auto & mshr_itb = memory_access_info_ptr->getMSHRInfoIterator(); + if(mshr_itb.isValid()){ + ILOG("Removing mshr entry for " << memory_access_info_ptr); + mshr_file_.erase(memory_access_info_ptr->getMSHRInfoIterator()); + } + l2cache_busy_ = false; + in_l2_cache_resp_receive_event_.schedule(); } void DCache::getCreditsFromL2Cache_(const uint32_t &ack) { dcache_l2cache_credits_ += ack; } -} + // MSHR Entry allocation in case of miss + void DCache::allocateMSHREntry_(const MemoryAccessInfoPtr & mem_access_info_ptr) + { + sparta_assert(mshr_file_.size() <= num_mshr_entries_, "Appending mshr causes overflows!"); + + MSHREntryInfoPtr mshr_entry = sparta::allocate_sparta_shared_pointer( + mshr_entry_allocator_, cache_line_size_, getClock()); + + const auto & it = mshr_file_.push_back(mshr_entry); + mem_access_info_ptr->setMSHREntryInfoIterator(it); + } + +} // namespace olympia diff --git a/core/DCache.hpp b/core/DCache.hpp index 269d9ce0..e3c3de8e 100644 --- a/core/DCache.hpp +++ b/core/DCache.hpp @@ -3,12 +3,15 @@ #include "sparta/simulation/Unit.hpp" #include "sparta/ports/DataPort.hpp" #include "sparta/ports/SignalPort.hpp" +#include "sparta/resources/Pipeline.hpp" #include "sparta/simulation/ParameterSet.hpp" +#include "sparta/simulation/Unit.hpp" #include "sparta/utils/LogUtils.hpp" #include "CacheFuncModel.hpp" #include "Inst.hpp" #include "cache/TreePLRUReplacement.hpp" #include "MemoryAccessInfo.hpp" +#include "MSHREntryInfo.hpp" namespace olympia { @@ -24,8 +27,8 @@ namespace olympia PARAMETER(uint32_t, l1_line_size, 64, "DL1 line size (power of 2)") PARAMETER(uint32_t, l1_size_kb, 32, "Size of DL1 in KB (power of 2)") PARAMETER(uint32_t, l1_associativity, 8, "DL1 associativity (power of 2)") - PARAMETER(uint32_t, cache_latency, 1, "Assumed latency of the memory system") PARAMETER(bool, l1_always_hit, false, "DL1 will always hit") + PARAMETER(uint32_t, mshr_entries, 8, "Number of MSHR Entries") }; static const char name[]; @@ -42,13 +45,57 @@ namespace olympia void getRespFromL2Cache_(const MemoryAccessInfoPtr & memory_access_info_ptr); + //////////////////////////////////////////////////////////////////////////////// + // L1 Data Cache Handling + //////////////////////////////////////////////////////////////////////////////// using L1Handle = CacheFuncModel::Handle; L1Handle l1_cache_; const bool l1_always_hit_; - bool busy_ = false; - uint32_t cache_latency_ = 0; + const uint64_t cache_line_size_; + const sparta::cache::AddrDecoderIF* addr_decoder_; // Keep track of the instruction that causes current outstanding cache miss - MemoryAccessInfoPtr cache_pending_inst_ = nullptr; + // MemoryAccessInfoPtr cache_pending_inst_ = nullptr; + + const uint32_t num_mshr_entries_; + + void setupL1Cache_(const CacheParameterSet* p); + + uint64_t getBlockAddr(const MemoryAccessInfoPtr & mem_access_info_ptr) const; + + using MSHREntryInfoPtr = sparta::SpartaSharedPointer; + using MSHREntryIterator = sparta::Buffer::const_iterator; + // Ongoing Refill request + MSHREntryIterator current_refill_mshr_entry_; + + // Cache Pipeline + enum class PipelineStage + { + LOOKUP = 0, + DATA_READ = 1, + DEALLOCATE = 2, + NUM_STAGES + }; + + sparta::Pipeline cache_pipeline_{ + "DCachePipeline", static_cast(PipelineStage::NUM_STAGES), getClock()}; + + void handleLookup_(); + void handleDataRead_(); + void handleDeallocate_(); + + //////////////////////////////////////////////////////////////////////////////// + // Handle requests + //////////////////////////////////////////////////////////////////////////////// + + void receiveMemReqFromLSU_(const MemoryAccessInfoPtr & memory_access_info_ptr); + + void receiveAckFromL2Cache_(const uint32_t & ack); + + void receiveRespFromL2Cache_(const MemoryAccessInfoPtr & memory_access_info_ptr); + + void mshrRequest_(); + + bool l2cache_busy_ = false; // Credit bool for sending miss request to L2Cache uint32_t dcache_l2cache_credits_ = 0; @@ -81,6 +128,40 @@ namespace olympia //////////////////////////////////////////////////////////////////////////////// // Events //////////////////////////////////////////////////////////////////////////////// + sparta::UniqueEvent<> uev_mshr_request_{&unit_event_set_, "mshr_request", + CREATE_SPARTA_HANDLER(DCache, mshrRequest_)}; + + sparta::utils::ValidValue l2_mem_access_info_; + sparta::utils::ValidValue lsu_mem_access_info_; + + void arbitrateL2LsuReq_() + { + if (l2_mem_access_info_.isValid()) + { + auto mem_access_info_ptr = l2_mem_access_info_.getValue(); + ILOG("Received Refill request " << mem_access_info_ptr); + cache_pipeline_.append(mem_access_info_ptr); + } + else + { + auto mem_access_info_ptr = lsu_mem_access_info_.getValue(); + ILOG("Received LSU request " << mem_access_info_ptr); + cache_pipeline_.append(mem_access_info_ptr); + } + if (l2_mem_access_info_.isValid()) + { + l2_mem_access_info_.clearValid(); + } + if (lsu_mem_access_info_.isValid()) + { + lsu_mem_access_info_.clearValid(); + } + uev_mshr_request_.schedule(1); + } + + sparta::UniqueEvent<> in_l2_cache_resp_receive_event_{ + &unit_event_set_, "in_l2_cache_resp_receive_event", + CREATE_SPARTA_HANDLER(DCache, arbitrateL2LsuReq_)}; //////////////////////////////////////////////////////////////////////////////// // Counters @@ -91,6 +172,14 @@ namespace olympia sparta::Counter dl1_cache_misses_{getStatisticSet(), "dl1_cache_misses", "Number of DL1 cache misses", sparta::Counter::COUNT_NORMAL}; + + sparta::StatisticDef dl1_hit_miss_ratio_{getStatisticSet(), "dl1_hit_miss_ratio", + "DL1 HIT/MISS Ratio", getStatisticSet(), + "dl1_cache_hits/dl1_cache_misses"}; + + sparta::Buffer mshr_file_; + MSHREntryInfoAllocator & mshr_entry_allocator_; + void allocateMSHREntry_(const MemoryAccessInfoPtr & mem_access_info_ptr); }; } // namespace olympia diff --git a/core/Decode.cpp b/core/Decode.cpp index 62752ce5..9a92fbcd 100644 --- a/core/Decode.cpp +++ b/core/Decode.cpp @@ -1,45 +1,109 @@ // -*- C++ -*- - -#include - #include "Decode.hpp" +#include "VectorUopGenerator.hpp" +#include "fsl_api/FusionTypes.h" #include "sparta/events/StartupEvent.hpp" #include "sparta/utils/LogUtils.hpp" +#include +#include + +using namespace std; namespace olympia { constexpr char Decode::name[]; - Decode::Decode(sparta::TreeNode * node, - const DecodeParameterSet * p) : + Decode::Decode(sparta::TreeNode* node, const DecodeParameterSet* p) : sparta::Unit(node), fetch_queue_("FetchQueue", p->fetch_queue_size, node->getClock(), &unit_stat_set_), - num_to_decode_(p->num_to_decode) + fusion_num_fuse_instructions_(&unit_stat_set_, "fusion_num_fuse_instructions", + "The number of custom instructions created by fusion", + sparta::Counter::COUNT_NORMAL), + + fusion_num_ghost_instructions_(&unit_stat_set_, "fusion_num_ghost_instructions", + "The number of instructions eliminated by fusion", + sparta::Counter::COUNT_NORMAL), + + fusion_num_groups_defined_(&unit_stat_set_, "fusion_num_groups_defined", + "Number of fusion groups compiled or read at run time", + sparta::Counter::COUNT_LATEST), + + fusion_num_groups_utilized_(&unit_stat_set_, "fusion_num_groups_utilized", + "Incremented on first use of a fusion group", + sparta::Counter::COUNT_LATEST), + + fusion_pred_cycles_saved_(&unit_stat_set_, "fusion_pred_cycles_saved", + "Optimistic prediction of the cycles saved by fusion", + sparta::Counter::COUNT_NORMAL), + + num_to_decode_(p->num_to_decode), + fusion_enable_(p->fusion_enable), + fusion_debug_(p->fusion_debug), + fusion_enable_register_(p->fusion_enable_register), + fusion_max_latency_(p->fusion_max_latency), + fusion_match_max_tries_(p->fusion_match_max_tries), + fusion_max_group_size_(p->fusion_max_group_size), + fusion_summary_report_(p->fusion_summary_report), + fusion_group_definitions_(p->fusion_group_definitions), + vector_enabled_(true), + vector_config_(new VectorConfig(p->init_vl, p->init_sew, p->init_lmul, p->init_vta)) { + initializeFusion_(); + fetch_queue_.enableCollection(node); - fetch_queue_write_in_. - registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(Decode, fetchBufferAppended_, InstGroupPtr)); - uop_queue_credits_in_. - registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(Decode, receiveUopQueueCredits_, uint32_t)); - in_reorder_flush_. - registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(Decode, handleFlush_, FlushManager::FlushingCriteria)); + fetch_queue_write_in_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(Decode, fetchBufferAppended_, InstGroupPtr)); + uop_queue_credits_in_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(Decode, receiveUopQueueCredits_, uint32_t)); + in_reorder_flush_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(Decode, handleFlush_, FlushManager::FlushingCriteria)); + in_vset_inst_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(Decode, processVset_, InstPtr)); sparta::StartupEvent(node, CREATE_SPARTA_HANDLER(Decode, sendInitialCredits_)); } + uint32_t Decode::getNumVecUopsRemaining() const + { + return vector_enabled_ ? vec_uop_gen_->getNumUopsRemaining() : 0; + } + // Send fetch the initial credit count void Decode::sendInitialCredits_() { fetch_queue_credits_outp_.send(fetch_queue_.capacity()); + + // Get pointer to the vector uop generator + sparta::TreeNode * root_node = getContainer()->getRoot(); + vec_uop_gen_ = \ + root_node->getChild("cpu.core0.decode.vec_uop_gen")->getResourceAs(); + } + + // ------------------------------------------------------------------- + // ------------------------------------------------------------------- + void Decode::initializeFusion_() + { + if (fusion_enable_) + { + fuser_ = std::make_unique(fusion_group_definitions_); + hcache_ = fusion::HCache(FusionGroupType::jenkins_1aat); + fusion_num_groups_defined_ = fuser_->getFusionGroupContainer().size(); + } + else + { + fuser_ = nullptr; + } } // Receive Uop credits from Dispatch - void Decode::receiveUopQueueCredits_(const uint32_t & credits) { + void Decode::receiveUopQueueCredits_(const uint32_t & credits) + { uop_queue_credits_ += credits; - if (fetch_queue_.size() > 0) { + if (fetch_queue_.size() > 0) + { ev_decode_insts_event_.schedule(sparta::Clock::Cycle(0)); } @@ -52,12 +116,45 @@ namespace olympia void Decode::fetchBufferAppended_(const InstGroupPtr & insts) { // Cache the instructions in the instruction queue if we can't decode this cycle - for(auto & i : *insts) + for (auto & i : *insts) { fetch_queue_.push(i); ILOG("Received: " << i); } - if (uop_queue_credits_ > 0) { + if (uop_queue_credits_ > 0) + { + ev_decode_insts_event_.schedule(sparta::Clock::Cycle(0)); + } + } + + void Decode::updateVectorConfig_(const InstPtr & inst) + { + vector_config_ = inst->getVectorConfig(); + + // If rs1 is x0 and rd is x0 then the vl is unchanged (assuming it is legal) + const uint64_t uid = inst->getOpCodeInfo()->getInstructionUniqueID(); + if ((uid == MAVIS_UID_VSETVLI) && inst->hasZeroRegSource()) + { + const uint32_t new_vl = \ + inst->hasZeroRegDest() ? std::min(vector_config_->getVL(), vector_config_->getVLMAX()) + : vector_config_->getVLMAX(); + vector_config_->setVL(new_vl); + } + + ILOG("Processing vset{i}vl{i} instruction: " << inst << " " << vector_config_); + } + + // process vset settings being forward from execution pipe + // for set instructions that depend on register + void Decode::processVset_(const InstPtr & inst) + { + updateVectorConfig_(inst); + + // if rs1 != 0, VL = x[rs1], so we assume there's an STF field for VL + if (waiting_on_vset_) + { + // schedule decode, because we've been stalled on vset + waiting_on_vset_ = false; ev_decode_insts_event_.schedule(sparta::Clock::Cycle(0)); } } @@ -68,43 +165,161 @@ namespace olympia ILOG("Got a flush call for " << criteria); fetch_queue_credits_outp_.send(fetch_queue_.size()); fetch_queue_.clear(); + + // Reset the vector uop generator + vec_uop_gen_->handleFlush(criteria); } // Decode instructions void Decode::decodeInsts_() { - uint32_t num_decode = std::min(uop_queue_credits_, fetch_queue_.size()); - num_decode = std::min(num_decode, num_to_decode_); + const uint32_t num_to_decode = std::min(uop_queue_credits_, num_to_decode_); + + // buffer to maximize the chances of a group match limited + // by max allowed latency, bounded by max group size + if (fusion_enable_) + { + if (num_to_decode < fusion_max_group_size_ && latency_count_ < fusion_max_latency_) + { + ++latency_count_; + return; + } + } + + latency_count_ = 0; - if(num_decode > 0) + // For fusion + InstUidListType uids; + + // Send instructions on their way to rename + InstGroupPtr insts = + sparta::allocate_sparta_shared_pointer(instgroup_allocator); + // if we have a waiting on vset followed by more instructions, we decode + // vset and stall anything else + while ((insts->size() < num_to_decode) && !waiting_on_vset_) { - InstGroupPtr insts = - sparta::allocate_sparta_shared_pointer(instgroup_allocator); - // Send instructions on their way to rename - for(uint32_t i = 0; i < num_decode; ++i) { - const auto & inst = fetch_queue_.read(0); - insts->emplace_back(inst); - inst->setStatus(Inst::Status::DECODED); + if (vec_uop_gen_->getNumUopsRemaining() > 0) + { + const InstPtr uop = vec_uop_gen_->generateUop(); + insts->emplace_back(uop); + uop->setStatus(Inst::Status::DECODED); + } + else if (fetch_queue_.size() > 0) + { + sparta_assert(fetch_queue_.size() > 0, + "Cannot read from the fetch queue because it is empty!"); + auto & inst = fetch_queue_.read(0); + + // for vector instructions, we block on vset and do not allow any other + // processing of instructions until the vset is resolved optimizations could be + // to allow scalar operations to move forward until a subsequent vector + // instruction is detected or do vset prediction + + // vsetvl always block + // vsetvli only blocks if rs1 is not x0 + // vsetivli never blocks + const uint64_t uid = inst->getOpCodeInfo()->getInstructionUniqueID(); + if ((uid == MAVIS_UID_VSETIVLI) || + ((uid == MAVIS_UID_VSETVLI) && inst->hasZeroRegSource())) + { + updateVectorConfig_(inst); + } + else if (uid == MAVIS_UID_VSETVLI || uid == MAVIS_UID_VSETVL) + { + // block for vsetvl or vsetvli when rs1 of vsetvli is NOT 0 + waiting_on_vset_ = true; + // need to indicate we want a signal sent back at execute + inst->setBlockingVSET(true); + ILOG("Decode stalled, Waiting on vset that has register dependency: " << inst) + } + else + { + if (!inst->isVset() && inst->isVector()) + { + // set LMUL, VSET, VL, VTA for any other vector instructions + inst->setVectorConfig(vector_config_); + } + } ILOG("Decoded: " << inst); + // Even if LMUL == 1, we need the vector uop generator to create a uop for us + // because some generators will add additional sources and destinations to the + // instruction (e.g. widening, multiply-add, slides). + if (inst->isVector() && !inst->isVset() && (inst->getUopGenType() != InstArchInfo::UopGenType::NONE)) + { + ILOG("Vector uop gen: " << inst); + vec_uop_gen_->setInst(inst); + + const InstPtr uop = vec_uop_gen_->generateUop(); + insts->emplace_back(uop); + uop->setStatus(Inst::Status::DECODED); + } + else + { + insts->emplace_back(inst); + inst->setStatus(Inst::Status::DECODED); + } + + if (fusion_enable_) + { + uids.push_back(inst->getMavisUid()); + } + + // Remove from Fetch Queue fetch_queue_.pop(); } + else + { + // Nothing left to decode + break; + } + } - // Send decoded instructions to rename - uop_queue_outp_.send(insts); + if (fusion_enable_) + { + MatchInfoListType matches; + uint32_t max_itrs = 0; + FusionGroupContainerType & container = fuser_->getFusionGroupContainer(); + do + { + matchFusionGroups_(matches, insts, uids, container); + processMatches_(matches, insts, uids); + // Future feature whereIsEgon(insts,numGhosts); + ++max_itrs; + } while (matches.size() > 0 && max_itrs < fusion_match_max_tries_); - // Decrement internal Uop Queue credits - uop_queue_credits_ -= insts->size(); + if (max_itrs >= fusion_match_max_tries_) + { + throw sparta::SpartaException("Fusion group match watch dog exceeded."); + } - // Send credits back to Fetch to get more instructions - fetch_queue_credits_outp_.send(insts->size()); + // Debug statement + if (fusion_debug_) + { + infoInsts_(cout, insts); + } } + // Send decoded instructions to rename + uop_queue_outp_.send(insts); + + // TODO: whereisegon() would remove the ghosts, + // Commented out for now, in practice insts + // would be smaller due to the fused ops + // uint32_t unfusedInstsSize = insts->size(); + + // Decrement internal Uop Queue credits + uop_queue_credits_ -= insts->size(); + + // Send credits back to Fetch to get more instructions + fetch_queue_credits_outp_.send(insts->size()); + // If we still have credits to send instructions as well as // instructions in the queue, schedule another decode session - if(uop_queue_credits_ > 0 && fetch_queue_.size() > 0) { + if (uop_queue_credits_ > 0 && (fetch_queue_.size() + getNumVecUopsRemaining()) > 0) + { ev_decode_insts_event_.schedule(1); } } -} +} // namespace olympia diff --git a/core/Decode.hpp b/core/Decode.hpp index 73b600bc..3d807daf 100644 --- a/core/Decode.hpp +++ b/core/Decode.hpp @@ -1,22 +1,34 @@ // -*- C++ -*- +//! \file Decode.hpp +#pragma once +#include "CoreTypes.hpp" +#include "FlushManager.hpp" +#include "InstGroup.hpp" +#include "MavisUnit.hpp" +#include "fsl_api/FieldExtractor.h" +#include "fsl_api/Fusion.h" +#include "fsl_api/FusionGroup.h" +#include "fsl_api/FusionTypes.h" +#include "fsl_api/HCache.h" +#include "fsl_api/MachineInfo.h" -#pragma once - -#include #include "sparta/ports/DataPort.hpp" #include "sparta/events/UniqueEvent.hpp" #include "sparta/simulation/Unit.hpp" #include "sparta/simulation/TreeNode.hpp" #include "sparta/simulation/ParameterSet.hpp" -#include "CoreTypes.hpp" -#include "FlushManager.hpp" -#include "InstGroup.hpp" + +#include +#include +#include +#include +#include namespace olympia { - + class VectorUopGenerator; /** * @file Decode.h * @brief Decode instructions from Fetch and send them on @@ -27,17 +39,99 @@ namespace olympia */ class Decode : public sparta::Unit { - public: + + //! \brief ... + using FusionGroupType = fusion::FusionGroup; + //! \brief ... + using FusionType = fusion::Fusion; + //! \brief ... + using FusionGroupListType = std::vector; + //! \brief ... + using FusionGroupContainerType = std::unordered_map; + //! \brief ... + using FusionGroupCfgType = fusion::FusionGroupCfg; + //! \brief ... + using FusionGroupCfgListType = std::vector; + //! \brief ... + using InstUidListType = fusion::InstUidListType; + //! \brief the is the return reference type for group matches + using MatchInfoListType = std::vector; + //! \brief ... + using HashPair = pair; + //! \brief ... + using HashPairListType = std::vector; + //! \brief ... + using FileNameListType = fusion::FileNameListType; + + public: //! \brief Parameters for Decode model class DecodeParameterSet : public sparta::ParameterSet { - public: - DecodeParameterSet(sparta::TreeNode* n) : - sparta::ParameterSet(n) - { } + public: + DecodeParameterSet(sparta::TreeNode* n) : sparta::ParameterSet(n) {} - PARAMETER(uint32_t, num_to_decode, 4, "Number of instructions to process") + //! \brief width of decoder + PARAMETER(uint32_t, num_to_decode, 4, "Decode group size") + + //! \brief depth of the input instruction buffer PARAMETER(uint32_t, fetch_queue_size, 10, "Size of the fetch queue") + + //! \brief enable fusion operations + //! + //! master enable, when false fusion_* parmeters have no effect + PARAMETER(bool, fusion_enable, false, "enable the fusion logic") + + //! \brief enable fusion specific debug statements + PARAMETER(bool, fusion_debug, false, "enable fusion debug logic") + + //! \brief fusion group enable register + //! + //! This is a bit mask that enables each fusion transform + //! Rather than a series of parameters for each fusion group + //! this uses one bit per fusion group. Default is all on. + //! + //! \see fusion_enable_register_ for the encoding + //! in the yaml to choose a transform my name + PARAMETER(uint32_t, fusion_enable_register, std::numeric_limits::max(), + "bit-wise fusion group enable") + + //! \brief max acceptable latency created by gathering uops + //! + //! Depending on the max fusion tuple size uops will be gathered, + //! when downstream is not busy this introduces some latency. + //! This knob allows studying the effects. fusion_enabled must + //! be true + PARAMETER(uint32_t, fusion_max_latency, 4, "max fusion latency") + + //! \brief fusion group match max iterations + PARAMETER(uint32_t, fusion_match_max_tries, 1023, "fusion group match attempts limit") + + //! \brief records the largest fusion group size + //! + //! Used with fusion_max_latency to gather instructions for + //! possible fusion. If number of decode is >= fusion group size + //! there is no need to continue to gather instructions. + PARAMETER(uint32_t, fusion_max_group_size, 4, "max fusion group size") + + //! \brief ... + PARAMETER(std::string, fusion_summary_report, "fusion_summary.txt", + "Path to fusion report file") + + //! \brief ... + PARAMETER(FileNameListType, fusion_group_definitions, {}, + "Lists of fusion group UID json files") + + //! LMUL + PARAMETER(uint32_t, init_lmul, 1, "effective length") + + //! Element width in bits + PARAMETER(uint32_t, init_sew, 8, "element width") + + //! Vector length, number of elements + PARAMETER(uint32_t, init_vl, 128, "vector length") + + //! Vector tail agnostic, default is undisturbed + PARAMETER(bool, init_vta, 0, "vector tail agnostic") }; /** @@ -46,41 +140,234 @@ namespace olympia * @param node The node that represents (has a pointer to) the Decode * @param p The Decode's parameter set */ - Decode(sparta::TreeNode * node, - const DecodeParameterSet * p); + Decode(sparta::TreeNode* node, const DecodeParameterSet* p); //! \brief Name of this resource. Required by sparta::UnitFactory static constexpr char name[] = "decode"; - private: - + private: // The internal instruction queue InstQueue fetch_queue_; + // Vector uop generator + VectorUopGenerator * vec_uop_gen_ = nullptr; + // Port listening to the fetch queue appends - Note the 1 cycle delay - sparta::DataInPort fetch_queue_write_in_ {&unit_port_set_, "in_fetch_queue_write", 1}; - sparta::DataOutPort fetch_queue_credits_outp_ {&unit_port_set_, "out_fetch_queue_credits"}; + sparta::DataInPort fetch_queue_write_in_{&unit_port_set_, + "in_fetch_queue_write", 1}; + sparta::DataInPort in_vset_inst_{&unit_port_set_, "in_vset_inst", 1}; + sparta::DataOutPort fetch_queue_credits_outp_{&unit_port_set_, + "out_fetch_queue_credits"}; // Port to the uop queue in dispatch (output and credits) - sparta::DataOutPort uop_queue_outp_ {&unit_port_set_, "out_uop_queue_write"}; - sparta::DataInPort uop_queue_credits_in_{&unit_port_set_, "in_uop_queue_credits", sparta::SchedulingPhase::Tick, 0}; + sparta::DataOutPort uop_queue_outp_{&unit_port_set_, "out_uop_queue_write"}; + sparta::DataInPort uop_queue_credits_in_{&unit_port_set_, "in_uop_queue_credits", + sparta::SchedulingPhase::Tick, 0}; // For flush - sparta::DataInPort in_reorder_flush_ - {&unit_port_set_, "in_reorder_flush", sparta::SchedulingPhase::Flush, 1}; + sparta::DataInPort in_reorder_flush_{ + &unit_port_set_, "in_reorder_flush", sparta::SchedulingPhase::Flush, 1}; + + //! \brief decode instruction event + sparta::UniqueEvent<> ev_decode_insts_event_{&unit_event_set_, "decode_insts_event", + CREATE_SPARTA_HANDLER(Decode, decodeInsts_)}; + + //! \brief initialize the fusion group configuration + void constructFusionGroups_(); + + //! \brief compare the dynamic uid vector to the predefined groups + //! + //! returns a sorted list of matches + //! Matches the fusionGroup sets against the input. There is a continuation + //! check invoked if the fusionGroup is larger than the input list. + //! FusionGroups must exactly match a segment of the input. + //! + //! During construction each fusion group has a pre-calculated Hash + //! created from the UIDs in the group. + //! + //! The group hash is matched against hashes formed from the input UIDs. + //! + //! In order to match the input to the group, hashes must be created of + //! the input. + //! + //! A 'cache' of the inputUids is created on entry. The cache is indexed + //! by group size. The cache data is a vector of pairs, pair.first is the + //! input position within inputUids, pair.second is the hash of the + //! inputUids in that segment. + void matchFusionGroups_(MatchInfoListType & matches, InstGroupPtr & insts, + InstUidListType & inputUIDS, FusionGroupContainerType &); - // The decode instruction event - sparta::UniqueEvent<> ev_decode_insts_event_ {&unit_event_set_, "decode_insts_event", CREATE_SPARTA_HANDLER(Decode, decodeInsts_)}; + //! \brief process the fusion matches + void processMatches_(MatchInfoListType &, InstGroupPtr & insts, + const InstUidListType & inputUIDS); + + //! \brief Remove the ghost ops + //! + //! The matching pass identifies the master fusion op (FUSED) + //! and the ops that will be eliminated (FUSION_GHOST). + //! This pass removes the ghosts. Future feature: not currently used. + void whereIsEgon_(InstGroupPtr &, uint32_t &); + + //! \brief ... + void infoInsts_(std::ostream & os, const InstGroupPtr & insts); + + //! \brief initialize the fusion api structures + //! + //! This can construct the FusionGroup lists using multiple + //! methods, as static objects, as objects read from files, etc. + //! + //! This called a small number of support methods. + void initializeFusion_(); + + //! \brief assign the current fusion group configs to a named context + //! + //! The Fusion API supports multiple contexts. There is a single + //! context in CAM at the moment. + //! + //! This method constructs the context and throws if there are + //! problems detected during construction + void setFusionContext_(FusionGroupListType &); + + //! \brief fusion groups are contructed statically or from DSL files + void constructGroups_(const FusionGroupCfgListType &, FusionGroupListType &); + + //! \brief record stats for fusionGroup name + void updateFusionGroupUtilization_(std::string name); + + //! \brief number of custom instructions created for fusion + sparta::Counter fusion_num_fuse_instructions_; + + //! \brief number of instructions eliminated by fusion + sparta::Counter fusion_num_ghost_instructions_; + + //! \brief the number of entries in the fusion group struct + //! + //! This is a run-time determined value extracted from parsing + //! the JSON files. Future feature: FSL file support + sparta::Counter fusion_num_groups_defined_; + + //! \brief the number of fusion groups utilizaed + //! + //! Some number of run-time or compile-time fusion groups + //! are defined. + //! + //! This is a measure of how many defined groups were + //! used during execution. A fusion group used 100 times + //! counts only once. + sparta::Counter fusion_num_groups_utilized_; + + //! \brief the predicted number of cycles saved by fusion + //! + //! For the simplist case a fusion group of N instructions + //! saves N-1 cycles. Modified for the cases where some + //! instructions and some fusion groups are multi-cycle. + //! + //! This is a prediction without concern for pipeline + //! behavior. This is compared against measured cycles + //! with fusion enabled vs. disabled to show effectiveness + //! of the defined fusion groups. + sparta::Counter fusion_pred_cycles_saved_; + + //! \brief temporary for number of instructions to decode this time + const uint32_t num_to_decode_; + + //! \brief master fusion enable data member + //! + //! This is the model's fusion enable parameter. When not enabled + //! the fusion methods have no impact on function or performance + //! of the model. \see fusion_enable_register_; + const bool fusion_enable_{false}; + + //! \brief fusion debug switch setting + //! + //! There are infrequent debug related statements that are gated + //! with this parameter. + const bool fusion_debug_{false}; + + //! \brief represents the FER in h/w + //! + //! The register holds an encoded value. Each fusion group + //! has an associated page, and an enable. The upper 4 bits + //! represent a page, the lower 28 bits are the enables. + //! PAGE=0xF all enabled, PAGE=0x0 all disabled. This is preferred + //! over a separate page register and enable register. + //! + //! Currently defined but not used + const uint32_t fusion_enable_register_{0}; + + //! \brief maximum allowed latency induced by fusion + //! + //! This typically zero, a parameter is provided to allow + //! experimenting with instruction gathering + const uint32_t fusion_max_latency_{0}; + + //! \brief max attempts to match UIDs of instrs in the XIQ + const uint32_t fusion_match_max_tries_{0}; + + //! \brief the longest chain of UIDs across all groups + //! + //! \see FusionGroup + uint32_t fusion_max_group_size_{0}; + + //! \brief running count of fusion latency + uint32_t latency_count_{0}; + + //! \brief the Fusion API instance + //! + //! \see Fusion.hpp + std::unique_ptr fuser_{nullptr}; + + //! \brief fusion group matching hash + fusion::HCache hcache_; + + //! \brief fusion function object callback proxies + struct cbProxy_; + //! \brief this counts the number of times a group is used + std::map matchedFusionGroups_; + //! \brief fusion specific report file name + const std::string fusion_summary_report_; + //! \brief the fusion group definition files, JSON or (future) FSL + const std::vector fusion_group_definitions_; + + ////////////////////////////////////////////////////////////////////// + // Vector + const bool vector_enabled_; + VectorConfigPtr vector_config_; + + bool waiting_on_vset_; + + // Helper method to get the current vector config + void updateVectorConfig_(const InstPtr &); + + uint32_t getNumVecUopsRemaining() const; ////////////////////////////////////////////////////////////////////// // Decoder callbacks void sendInitialCredits_(); - void fetchBufferAppended_ (const InstGroupPtr &); + void fetchBufferAppended_(const InstGroupPtr &); void receiveUopQueueCredits_(const uint32_t &); + void processVset_(const InstPtr &); void decodeInsts_(); void handleFlush_(const FlushManager::FlushingCriteria & criteria); uint32_t uop_queue_credits_ = 0; - const uint32_t num_to_decode_; + friend class DecodeTester; + }; + class DecodeTester; + + //! \brief the fusion functor/function objects + //! + //! there is one function object assigned to each group, + //! the objects can be shared across groups + struct Decode::cbProxy_ + { + //! \brief this is the default 'no fusion' operation + //! + //! false indicates no transform was performed + static bool dfltXform_(FusionGroupType &, fusion::InstPtrListType &, + fusion::InstPtrListType &) + { + return false; + } }; -} +} // namespace olympia diff --git a/core/Dispatch.cpp b/core/Dispatch.cpp index 18fec2b7..74ce4a14 100644 --- a/core/Dispatch.cpp +++ b/core/Dispatch.cpp @@ -211,7 +211,7 @@ namespace olympia InstGroupPtr insts_dispatched = sparta::allocate_sparta_shared_pointer(instgroup_allocator); - ; + bool keep_dispatching = true; for (uint32_t i = 0; (i < num_dispatch) && keep_dispatching; ++i) { @@ -223,89 +223,79 @@ namespace olympia sparta_assert(target_pipe != InstArchInfo::TargetPipe::UNKNOWN, "Have an instruction that doesn't know where to go: " << ex_inst); - if (SPARTA_EXPECT_FALSE(target_pipe == InstArchInfo::TargetPipe::SYS)) + // Get the dispatchers used to dispatch the target. + // Find a ready-to-go dispatcher + sparta_assert(static_cast(target_pipe) < InstArchInfo::N_TARGET_PIPES, + "Target pipe: " << target_pipe + << " not found in dispatchers, make sure pipe is " + "defined and has an assigned dispatcher"); + auto & dispatchers = dispatchers_[static_cast(target_pipe)]; + sparta_assert(dispatchers.size() > 0, + "Pipe Target: " + << target_pipe + << " doesn't have any execution unit that can handle that target " + "pipe. Did you define it in the yaml properly?"); + // so we have a map here that checks for which valid dispatchers for that + // instruction target pipe map needs to be: "int": [exe0, exe1, exe2] + if (target_pipe != InstArchInfo::TargetPipe::LSU) { - ex_inst.setStatus(Inst::Status::COMPLETED); - // Indicate that this instruction was dispatched - // -- it goes right to the ROB - dispatched = true; + uint32_t max_credits = 0; + olympia::Dispatcher* best_dispatcher = nullptr; + // find the dispatcher with the most amount of credits, i.e the issue queue with + // the least amount of entries + for (auto & dispatcher_iq : dispatchers) + { + if (dispatcher_iq->canAccept() && dispatcher_iq->getCredits() > max_credits) + { + best_dispatcher = dispatcher_iq.get(); + max_credits = dispatcher_iq->getCredits(); + } + } + if (best_dispatcher != nullptr) + { + best_dispatcher->acceptInst(ex_inst_ptr); + ++unit_distribution_[target_pipe]; + ++unit_distribution_context_.context(target_pipe); + ++weighted_unit_distribution_context_.context(target_pipe); + + ex_inst_ptr->setStatus(Inst::Status::DISPATCHED); + ILOG("Sending instruction: " << ex_inst_ptr << " to " + << best_dispatcher->getName() + << " of target type: " << target_pipe); + dispatched = true; + } } else { - // Get the dispatchers used to dispatch the target. - // Find a ready-to-go dispatcher - sparta_assert(static_cast(target_pipe) < InstArchInfo::N_TARGET_PIPES, - "Target pipe: " << target_pipe - << " not found in dispatchers, make sure pipe is " - "defined and has an assigned dispatcher"); - auto & dispatchers = dispatchers_[static_cast(target_pipe)]; - sparta_assert(dispatchers.size() > 0, - "Pipe Target: " - << target_pipe - << " doesn't have any execution unit that can handle that target " - "pipe. Did you define it in the yaml properly?"); - // so we have a map here that checks for which valid dispatchers for that - // instruction target pipe map needs to be: "int": [exe0, exe1, exe2] - if (target_pipe != InstArchInfo::TargetPipe::LSU) + for (auto & disp : dispatchers) { - uint32_t max_credits = 0; - olympia::Dispatcher* best_dispatcher = nullptr; - // find the dispatcher with the most amount of credits, i.e the issue queue with - // the least amount of entries - for (auto & dispatcher_iq : dispatchers) - { - if (dispatcher_iq->canAccept() && dispatcher_iq->getCredits() > max_credits) - { - best_dispatcher = dispatcher_iq.get(); - max_credits = dispatcher_iq->getCredits(); - } - } - if (best_dispatcher != nullptr) + if (disp->canAccept()) { - best_dispatcher->acceptInst(ex_inst_ptr); + disp->acceptInst(ex_inst_ptr); ++unit_distribution_[target_pipe]; - ++unit_distribution_context_.context(target_pipe); - ++weighted_unit_distribution_context_.context(target_pipe); + ++(unit_distribution_context_.context(target_pipe)); + ++(weighted_unit_distribution_context_.context(target_pipe)); ex_inst_ptr->setStatus(Inst::Status::DISPATCHED); ILOG("Sending instruction: " << ex_inst_ptr << " to " - << best_dispatcher->getName() - << " of target type: " << target_pipe); + << disp->getName()); dispatched = true; + + break; } - } - else - { - for (auto & disp : dispatchers) + else { - if (disp->canAccept()) - { - disp->acceptInst(ex_inst_ptr); - ++unit_distribution_[target_pipe]; - ++(unit_distribution_context_.context(target_pipe)); - ++(weighted_unit_distribution_context_.context(target_pipe)); - - ex_inst_ptr->setStatus(Inst::Status::DISPATCHED); - ILOG("Sending instruction: " << ex_inst_ptr << " to " - << disp->getName()); - dispatched = true; - - break; - } - else - { - ILOG(disp->getName() << " cannot accept inst: " << ex_inst_ptr); - blocking_dispatcher_ = target_pipe; - } + ILOG(disp->getName() << " cannot accept inst: " << ex_inst_ptr); + blocking_dispatcher_ = target_pipe; } } - if (false == dispatched) - { - current_stall_ = static_cast(target_pipe); - keep_dispatching = false; - } } - + if (false == dispatched) + { + current_stall_ = static_cast(target_pipe); + keep_dispatching = false; + } + if (dispatched) { insts_dispatched->emplace_back(ex_inst_ptr); diff --git a/core/Dispatch.hpp b/core/Dispatch.hpp index 78ff2fa1..1f94c0f9 100644 --- a/core/Dispatch.hpp +++ b/core/Dispatch.hpp @@ -123,30 +123,24 @@ namespace olympia /////////////////////////////////////////////////////////////////////// // Stall counters - enum StallReason + enum StallReason : uint16_t { - CMOV_BUSY = InstArchInfo::TargetPipe::CMOV, // Could not send any or all instructions -- - // CMOV busy - DIV_BUSY = - InstArchInfo::TargetPipe::DIV, // Could not send any or all instructions -- DIV busy - FADDSUB_BUSY = InstArchInfo::TargetPipe::FADDSUB, // Could not send any or all - // instructions -- FADDSUB busy - FLOAT_BUSY = InstArchInfo::TargetPipe::FLOAT, // Could not send any or all instructions - // -- FLOAT busy - FMAC_BUSY = InstArchInfo::TargetPipe::FMAC, // Could not send any or all instructions -- - // FMAC busy - I2F_BUSY = - InstArchInfo::TargetPipe::I2F, // Could not send any or all instructions -- I2F busy - F2I_BUSY = - InstArchInfo::TargetPipe::F2I, // Could not send any or all instructions -- F2I busy - INT_BUSY = - InstArchInfo::TargetPipe::INT, // Could not send any or all instructions -- INT busy - LSU_BUSY = - InstArchInfo::TargetPipe::LSU, // Could not send any or all instructions -- LSU busy - MUL_BUSY = - InstArchInfo::TargetPipe::MUL, // Could not send any or all instructions -- MUL busy - BR_BUSY = - InstArchInfo::TargetPipe::BR, // Could not send any or all instructions -- MUL busy + BR_BUSY = InstArchInfo::TargetPipe::BR, + CMOV_BUSY = InstArchInfo::TargetPipe::CMOV, + DIV_BUSY = InstArchInfo::TargetPipe::DIV, + FADDSUB_BUSY = InstArchInfo::TargetPipe::FADDSUB, + FLOAT_BUSY = InstArchInfo::TargetPipe::FLOAT, + FMAC_BUSY = InstArchInfo::TargetPipe::FMAC, + I2F_BUSY = InstArchInfo::TargetPipe::I2F, + F2I_BUSY = InstArchInfo::TargetPipe::F2I, + INT_BUSY = InstArchInfo::TargetPipe::INT, + LSU_BUSY = InstArchInfo::TargetPipe::LSU, + MUL_BUSY = InstArchInfo::TargetPipe::MUL, + VINT_BUSY = InstArchInfo::TargetPipe::VINT, + VMASK_BUSY = InstArchInfo::TargetPipe::VMASK, + VMUL_BUSY = InstArchInfo::TargetPipe::VMUL, + VDIV_BUSY = InstArchInfo::TargetPipe::VDIV, + VSET_BUSY = InstArchInfo::TargetPipe::VSET, NO_ROB_CREDITS = InstArchInfo::TargetPipe::SYS, // No credits from the ROB NOT_STALLED, // Made forward progress (dispatched all instructions or no instructions) N_STALL_REASONS @@ -180,6 +174,16 @@ namespace olympia sparta::Counter::COUNT_NORMAL, getClock()), sparta::CycleCounter(getStatisticSet(), "stall_br_busy", "BR busy", sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_vint_busy", "VINT busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_vmask_busy", "VMASK busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_vmul_busy", "VMUL busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_vdiv_busy", "VDIV busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_vset_busy", "VSET busy", + sparta::Counter::COUNT_NORMAL, getClock()), sparta::CycleCounter(getStatisticSet(), "stall_sys_busy", "No credits from ROB", sparta::Counter::COUNT_NORMAL, getClock()), sparta::CycleCounter(getStatisticSet(), "stall_not_stalled", @@ -209,6 +213,16 @@ namespace olympia sparta::Counter::COUNT_NORMAL), sparta::Counter(getStatisticSet(), "count_br_insts", "Total BR insts", sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_vint_insts", "Total VINT insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_vmask_insts", "Total VMASK insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_vmul_insts", "Total VMUL insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_vdiv_insts", "Total VDIV insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_vset_insts", "Total VSET insts", + sparta::Counter::COUNT_NORMAL), sparta::Counter(getStatisticSet(), "count_sys_insts", "Total SYS insts", sparta::Counter::COUNT_NORMAL)}}; @@ -262,51 +276,23 @@ namespace olympia inline std::ostream & operator<<(std::ostream & os, const Dispatch::StallReason & stall) { - switch (stall) + if (stall == Dispatch::StallReason::NOT_STALLED) { - case Dispatch::StallReason::NOT_STALLED: os << "NOT_STALLED"; - break; - case Dispatch::StallReason::NO_ROB_CREDITS: + } + else if (stall == Dispatch::StallReason::NO_ROB_CREDITS) + { os << "NO_ROB_CREDITS"; - break; - case Dispatch::StallReason::LSU_BUSY: - os << "LSU_BUSY"; - break; - case Dispatch::StallReason::CMOV_BUSY: - os << "CMOV_BUSY"; - break; - case Dispatch::StallReason::DIV_BUSY: - os << "DIV_BUSY"; - break; - case Dispatch::StallReason::FADDSUB_BUSY: - os << "FADDSUB_BUSY"; - break; - case Dispatch::StallReason::FLOAT_BUSY: - os << "FLOAT_BUSY"; - break; - case Dispatch::StallReason::FMAC_BUSY: - os << "FMAC_BUSY"; - break; - case Dispatch::StallReason::I2F_BUSY: - os << "I2F_BUSY"; - break; - case Dispatch::StallReason::F2I_BUSY: - os << "F2I_BUSY"; - break; - case Dispatch::StallReason::INT_BUSY: - os << "INT_BUSY"; - break; - case Dispatch::StallReason::MUL_BUSY: - os << "MUL_BUSY"; - break; - case Dispatch::StallReason::BR_BUSY: - os << "BR_BUSY"; - break; - case Dispatch::StallReason::N_STALL_REASONS: + } + else if (stall != Dispatch::StallReason::N_STALL_REASONS) + { + os << InstArchInfo::execution_pipe_string_map.at((InstArchInfo::TargetPipe)stall) << "_BUSY"; + } + else + { sparta_assert(false, "How'd we get here?"); } return os; } -} // namespace olympia \ No newline at end of file +} // namespace olympia diff --git a/core/ExecutePipe.cpp b/core/ExecutePipe.cpp index 22d801eb..818634c4 100644 --- a/core/ExecutePipe.cpp +++ b/core/ExecutePipe.cpp @@ -15,6 +15,7 @@ namespace olympia execute_time_(p->execute_time), enable_random_misprediction_(p->enable_random_misprediction && p->contains_branch_unit), issue_queue_name_(p->iq_name), + valu_adder_num_(p->valu_adder_num), collected_inst_(node, node->getName()) { p->enable_random_misprediction.ignore(); @@ -30,7 +31,6 @@ namespace olympia void ExecutePipe::setupExecutePipe_() { // Setup scoreboard view upon register file - std::vector reg_files = {core_types::RF_INTEGER, core_types::RF_FLOAT}; // if we ever move to multicore, we only want to have resources look for // scoreboard in their cpu if we're running a test where we only have // top.rename or top.issue_queue, then we can just use the root @@ -41,7 +41,7 @@ namespace olympia { cpu_node = getContainer()->getRoot(); } - for (const auto rf : reg_files) + for (uint32_t rf = 0; rf < core_types::RegFile::N_REGFILES; ++rf) { // alu0, alu1 name is based on exe names, point to issue_queue name instead scoreboard_views_[rf].reset( @@ -53,12 +53,62 @@ namespace olympia // change to insertInst void ExecutePipe::insertInst(const InstPtr & ex_inst) { - sparta_assert_context( - unit_busy_ == false, - "ExecutePipe is receiving a new instruction when it's already busy!!"); - ex_inst->setStatus(Inst::Status::SCHEDULED); - const uint32_t exe_time = - ignore_inst_execute_time_ ? execute_time_ : ex_inst->getExecuteTime(); + if (num_passes_needed_ == 0) + { + ex_inst->setStatus(Inst::Status::SCHEDULED); + // we only need to check if unit_busy_ if instruction doesn't have multiple passes + // if it does need multiple passes, we need to keep unit_busy_ blocked so no instruction + // can get dispatched before the next pass begins + sparta_assert_context( + unit_busy_ == false, + "ExecutePipe is receiving a new instruction when it's already busy!!"); + } + + // Get instruction latency + uint32_t exe_time = ignore_inst_execute_time_ ? execute_time_ : ex_inst->getExecuteTime(); + + if (!ex_inst->isVset() && ex_inst->isVector()) + { + // have to factor in vlen, sew, valu length to calculate how many passes are needed + // i.e if VL = 256 and SEW = 8, but our VALU only has 8 64 bit adders, it will take 4 + // passes to execute the entire instruction if we have an 8 bit number, the 64 bit adder + // will truncate, but we have each adder support the largest SEW possible + if (ex_inst->getPipe() == InstArchInfo::TargetPipe::VINT) + { + // First time seeing this uop, determine number of passes needed + if (num_passes_needed_ == 0) + { + // The number of non-tail elements in the uop is used to determine how many + // passes are needed + const VectorConfigPtr & vector_config = ex_inst->getVectorConfig(); + const uint32_t num_elems_per_uop = vector_config->getVLMAX() / vector_config->getLMUL(); + const uint32_t num_elems_remaining = \ + vector_config->getVL() - (num_elems_per_uop * (ex_inst->getUOpID() - 1)); + const uint32_t vl = std::min(num_elems_per_uop, num_elems_remaining); + const uint32_t num_passes = std::ceil(vl / valu_adder_num_); + if (num_passes > 1) + { + // only care about cases with multiple passes + num_passes_needed_ = num_passes; + curr_num_pass_ = 1; + ILOG("Inst " << ex_inst << " needs " << num_passes_needed_ + << " before completing the instruction, beginning pass: " + << curr_num_pass_); + } + } + else + { + curr_num_pass_++; + sparta_assert(curr_num_pass_ <= num_passes_needed_, + "Instruction with multiple passes incremented for more than the " + "total number of passes needed for instruction: " + << ex_inst) + ILOG("Inst: " + << ex_inst << " beginning it's pass number: " << curr_num_pass_ + << " of the total required passes needed: " << num_passes_needed_); + } + } + } collected_inst_.collectWithDuration(ex_inst, exe_time); ILOG("Executing: " << ex_inst << " for " << exe_time + getClock()->currentCycle()); sparta_assert(exe_time != 0); @@ -70,31 +120,53 @@ namespace olympia // Called by the scheduler, scheduled by complete_inst_. void ExecutePipe::executeInst_(const InstPtr & ex_inst) { - ILOG("Executed inst: " << ex_inst); - auto reg_file = ex_inst->getRenameData().getDestination().rf; - if (reg_file != core_types::RegFile::RF_INVALID) + if (num_passes_needed_ != 0 && curr_num_pass_ < num_passes_needed_) { - const auto & dest_bits = ex_inst->getDestRegisterBitMask(reg_file); - scoreboard_views_[reg_file]->setReady(dest_bits); + issue_inst_.preparePayload(ex_inst)->schedule(sparta::Clock::Cycle(0)); } - - if (enable_random_misprediction_) + else { - if (ex_inst->isBranch() && (std::rand() % 20) == 0) + if (num_passes_needed_ != 0) { - ILOG("Randomly injecting a mispredicted branch: " << ex_inst); - ex_inst->setMispredicted(); + // reseting counters once vector instruction needing more than 1 pass + curr_num_pass_ = 0; + num_passes_needed_ = 0; + } + ILOG("Executed inst: " << ex_inst); + if (ex_inst->isVset() && ex_inst->isBlockingVSET()) + { + // sending back VSET CSRs + const VectorConfigPtr & vector_config = ex_inst->getVectorConfig(); + ILOG("Forwarding VSET CSRs back to decode, LMUL: " + << vector_config->getLMUL() << " SEW: " << vector_config->getSEW() + << " VTA: " << vector_config->getVTA() << " VL: " << vector_config->getVL()); + out_vset_.send(ex_inst); + } + auto reg_file = ex_inst->getRenameData().getDestination().rf; + if (reg_file != core_types::RegFile::RF_INVALID) + { + const auto & dest_bits = ex_inst->getDestRegisterBitMask(reg_file); + scoreboard_views_[reg_file]->setReady(dest_bits); } - } - // We're not busy anymore - unit_busy_ = false; + if (enable_random_misprediction_) + { + if (ex_inst->isBranch() && (std::rand() % 20) == 0) + { + ILOG("Randomly injecting a mispredicted branch: " << ex_inst); + ex_inst->setMispredicted(); + } + } + + // We're not busy anymore + unit_busy_ = false; - // Count the instruction as completely executed - ++total_insts_executed_; + // Count the instruction as completely executed + ++total_insts_executed_; - // Schedule completion - complete_inst_.preparePayload(ex_inst)->schedule(1); + // Schedule completion + complete_inst_.preparePayload(ex_inst)->schedule(1); + } } // Called by the scheduler, scheduled by complete_inst_. diff --git a/core/ExecutePipe.hpp b/core/ExecutePipe.hpp index 5a2b95a3..1a281454 100644 --- a/core/ExecutePipe.hpp +++ b/core/ExecutePipe.hpp @@ -50,6 +50,8 @@ namespace olympia PARAMETER(uint32_t, execute_time, 1, "Time for execution") PARAMETER(bool, enable_random_misprediction, false, "test mode to inject random branch mispredictions") + PARAMETER(uint32_t, valu_adder_num, 8, + "VALU Number of Adders") // # of 64 bit adders, so 8 64 bit adders = 512 bits HIDDEN_PARAMETER(bool, contains_branch_unit, false, "Does this exe pipe contain a branch unit") HIDDEN_PARAMETER(std::string, iq_name, "", "issue queue name for scoreboard view") @@ -82,6 +84,7 @@ namespace olympia sparta::DataOutPort out_scheduler_credits_{&unit_port_set_, "out_scheduler_credits"}; sparta::DataOutPort out_execute_pipe_{&unit_port_set_, "out_execute_pipe"}; + sparta::DataOutPort out_vset_{&unit_port_set_, "out_vset"}; sparta::DataInPort in_reorder_flush_{ &unit_port_set_, "in_reorder_flush", sparta::SchedulingPhase::Flush, 1}; @@ -97,9 +100,11 @@ namespace olympia const uint32_t execute_time_; const bool enable_random_misprediction_; const std::string issue_queue_name_; - + uint32_t valu_adder_num_; + uint32_t num_passes_needed_ = 0; + uint32_t curr_num_pass_ = 0; // Events used to issue, execute and complete the instruction - sparta::UniqueEvent<> issue_inst_{ + sparta::PayloadEvent issue_inst_{ &unit_event_set_, getName() + "_insert_inst", CREATE_SPARTA_HANDLER_WITH_DATA(ExecutePipe, insertInst, InstPtr)}; sparta::PayloadEvent execute_inst_{ diff --git a/core/Fetch.cpp b/core/Fetch.cpp index 26b81f77..fbd784f0 100644 --- a/core/Fetch.cpp +++ b/core/Fetch.cpp @@ -17,10 +17,9 @@ namespace olympia { - const char * Fetch::name = "fetch"; + const char* Fetch::name = "fetch"; - Fetch::Fetch(sparta::TreeNode * node, - const FetchParameterSet * p) : + Fetch::Fetch(sparta::TreeNode* node, const FetchParameterSet* p) : sparta::Unit(node), my_clk_(getClock()), num_insts_to_fetch_(p->num_to_fetch), @@ -31,11 +30,11 @@ namespace olympia memory_access_allocator_(sparta::notNull(OlympiaAllocators::getOlympiaAllocators(node)) ->memory_access_allocator) { - in_fetch_queue_credits_. - registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(Fetch, receiveFetchQueueCredits_, uint32_t)); + in_fetch_queue_credits_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(Fetch, receiveFetchQueueCredits_, uint32_t)); - in_fetch_flush_redirect_. - registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(Fetch, flushFetch_, FlushManager::FlushingCriteria)); + in_fetch_flush_redirect_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(Fetch, flushFetch_, FlushManager::FlushingCriteria)); in_icache_fetch_resp_. registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(Fetch, receiveCacheResponse_, MemoryAccessInfoPtr)); @@ -221,7 +220,8 @@ namespace olympia } // Called when decode has room - void Fetch::receiveFetchQueueCredits_(const uint32_t & dat) { + void Fetch::receiveFetchQueueCredits_(const uint32_t & dat) + { credits_inst_queue_ += dat; ILOG("Fetch: receive num_decode_credits=" << dat diff --git a/core/FusionDecode.cpp b/core/FusionDecode.cpp new file mode 100644 index 00000000..ef1f3f3c --- /dev/null +++ b/core/FusionDecode.cpp @@ -0,0 +1,229 @@ +// Support methods for the fusion decoder +// 2024.07.25 Jeff Nye + +#include "fsl_api/FusionTypes.h" +#include "Decode.hpp" + +#include "sparta/events/StartupEvent.hpp" +#include "sparta/utils/LogUtils.hpp" + +#include +#include +#include +#include +#include + +using namespace std; +using namespace fusion; + +namespace olympia +{ + // ------------------------------------------------------------------- + // Remove the ghost fusion ops + // Kept, but currently not called + // ------------------------------------------------------------------- + void Decode::whereIsEgon_(InstGroupPtr & insts, uint32_t & numGhosts) + { + if (insts == nullptr) + { + // DLOG("whereIsEgon() called with insts null"); + return; + } + + // DLOG("BEFORE # --------------------------------------"); + // infoInsts(cout,insts); + + for (auto it = insts->begin(); it != insts->end();) + { + if ((*it)->getExtendedStatus() == olympia::Inst::Status::FUSION_GHOST) + { + ++numGhosts; + it = insts->erase(it); + } + else + { + ++it; + } + } + // DLOG("AFTER # --------------------------------------"); + // infoInsts(cout,insts); + // DLOG("DONE # --------------------------------------"); + } + + // ------------------------------------------------------------------- + // ------------------------------------------------------------------- + void Decode::processMatches_(MatchInfoListType & matches, InstGroupPtr & insts, + const InstUidListType & inputUids) + { + if (matches.size() == 0) + return; + + // Kept for upcoming additional work on reducing ROB entry requirements + // DLOG("PROCESS MATCHES "<infoUids(cout,inputUids,"before "); cout<info(cout,matches,inputUids); cout<begin(); + std::advance(itr, thisMatch.startIdx); + if ((*itr)->getExtendedStatus() == Inst::Status::UNMOD) + { + (*itr)->setExtendedStatus(Inst::Status::FUSED); + ++fusion_num_fuse_instructions_; + // Kept for upcoming additional work on reducing ROB + // entry requirements. This manages the sequential expectations + // of the ROB for program ID. + //(*itr)->setProgramIDIncrement(thisMatch.size()); + + for (size_t i = 1; i < thisMatch.size(); ++i) + { + ++itr; + sparta_assert(itr != insts->end(), + "processMatches inst iterator exceeded range"); + (*itr)->setExtendedStatus(Inst::Status::FUSION_GHOST); + ++fusion_num_ghost_instructions_; + ++fusion_pred_cycles_saved_; + } + updateFusionGroupUtilization_(thisMatch.name); + } + } + + matches.clear(); + } + + // ---------------------------------------------------------------------- + // TODO: this performs well for the FusionGroup set sizes tested, ~256. + // More testing is intended for 2048 (10x any practical size). + // Further improvement is deferred until a decsion on uop/trace cache + // implementations. Regardless, if warranted for model performance, + // an abstracted uop$ can be built using what is below adding the more + // conventional address indexing but retaining the UIDs as abstractions + // to fully decoded instrs. + // ---------------------------------------------------------------------- + void Decode::matchFusionGroups_(MatchInfoListType & matches, InstGroupPtr & insts, + InstUidListType & inputUids, + FusionGroupContainerType & fusionGroups) + { + matches.clear(); // Clear any existing matches + + // The cache is a map of cachelines, indexed by size, + // + // + // 3 1:hash 2:hash 3:hash ... modulo size, inputUids.size() % 3 + hcache_.clear(); + + for (auto & fgPair : fusionGroups) + { + auto & fGrp = fgPair.second; + size_t grpSize = fGrp.uids().size(); + hcache_.buildHashCacheEntry(inputUids, grpSize); + } + + for (auto & fgPair : fusionGroups) + { + + HashType grpHash = fgPair.first; + auto & fGrp = fgPair.second; + size_t grpSize = fGrp.uids().size(); + + // No match possible if the fg is bigger than the input + if (grpSize > inputUids.size()) + { + /*++filtered;*/ continue; + } + + // If the grpSize is not in the hash cache we need to calculate it + if (hcache_.find(grpSize) == hcache_.end()) + { + hcache_.buildHashCacheEntry(inputUids, grpSize); + } + + // If this fires something unexplained happened, the entry hit + // in the first place or it was constructed on a miss, + // either way this should never fire. + sparta_assert(hcache_.find(grpSize) != hcache_.end()) + + // pairs is from the cache entries with the same size as fGrp. + // a pair is , index is the position in the input + HashPairListType pairs = hcache_[grpSize]; + + // For each of the pairs that have the same size as fGrp. + for (auto & ep : pairs) + { + // if the pair.hash matches the group's hash + if (ep.second == grpHash) + { + + // DLOG("HASH HIT, index "< rhs.size(); + }); + } + + // ------------------------------------------------------------------------ + // If we get here we know name has been matched, update the stats + // ------------------------------------------------------------------------ + void Decode::updateFusionGroupUtilization_(std::string name) + { + // update the map containing per group utilization counts + // rely on the default behavior of map[] for new entries + matchedFusionGroups_[name]++; + // groups used more than once still only count as one in this stat + fusion_num_groups_utilized_ = matchedFusionGroups_.size(); + } + + // ------------------------------------------------------------------------ + // ------------------------------------------------------------------------ + void Decode::infoInsts_(std::ostream & os, const InstGroupPtr & insts) + { + InstGroup::iterator instItr; + os << "INSTS: "; + for (instItr = insts->begin(); instItr != insts->end(); ++instItr) + { + os << (*instItr)->info() << endl; + } + } + +} // namespace olympia diff --git a/core/Inst.cpp b/core/Inst.cpp index 59182a65..229fd4c4 100644 --- a/core/Inst.cpp +++ b/core/Inst.cpp @@ -1,9 +1,24 @@ // -*- C++ -*- #include "Inst.hpp" +#include namespace olympia { + const std::unordered_map Inst::status2String = { + { Inst::Status::BEFORE_FETCH,"BEFORE_FETCH" }, + { Inst::Status::FETCHED, "FETCHED" }, + { Inst::Status::DECODED, "DECODED" }, + { Inst::Status::RENAMED, "RENAMED" }, + { Inst::Status::DISPATCHED, "DISPATCHED" }, + { Inst::Status::SCHEDULED, "SCHEDULED" }, + { Inst::Status::COMPLETED, "COMPLETED" }, + { Inst::Status::RETIRED, "RETIRED" }, + { Inst::Status::FLUSHED, "FLUSHED" }, + { Inst::Status::UNMOD, "UNMOD" }, + { Inst::Status::FUSED, "FUSED" }, + { Inst::Status::FUSION_GHOST,"FUSION_GHOST" } + }; bool isCallInstruction(const mavis::OpcodeInfo::PtrType & opcode_info) { @@ -53,11 +68,20 @@ namespace olympia is_branch_(opcode_info_->isInstType(mavis::OpcodeInfo::InstructionTypes::BRANCH)), is_condbranch_(opcode_info_->isInstType(mavis::OpcodeInfo::InstructionTypes::CONDITIONAL)), is_call_(isCallInstruction(opcode_info)), + is_csr_(opcode_info->isInstType(mavis::OpcodeInfo::InstructionTypes::CSR)), + is_vector_(opcode_info->isInstType(mavis::OpcodeInfo::InstructionTypes::VECTOR)), is_return_(isReturnInstruction(opcode_info)), + has_immediate_(opcode_info_->hasImmediate()), status_state_(Status::BEFORE_FETCH) { sparta_assert(inst_arch_info_ != nullptr, "Mavis decoded the instruction, but Olympia has no uarch data for it: " << getDisasm() << " " << std::hex << " opc: 0x" << getOpCode()); + + // Check that instruction is supported + sparta_assert(getPipe() != InstArchInfo::TargetPipe::UNKNOWN, + "Unknown target pipe (execution) for " << getMnemonic()); + sparta_assert(getExecuteTime() != 0, + "Unknown execution time (latency) for " << getMnemonic()); } } // namespace olympia diff --git a/core/Inst.hpp b/core/Inst.hpp index 3aa32fee..a04ff925 100644 --- a/core/Inst.hpp +++ b/core/Inst.hpp @@ -15,12 +15,14 @@ #include "InstArchInfo.hpp" #include "CoreTypes.hpp" +#include "VectorConfig.hpp" #include "MiscUtils.hpp" #include #include -#include +#include #include +#include namespace olympia { @@ -93,6 +95,9 @@ namespace olympia COMPLETED, RETIRED, FLUSHED, + UNMOD, // no extended status + FUSED, + FUSION_GHOST, __LAST }; @@ -135,6 +140,18 @@ namespace olympia } } + const Status & getExtendedStatus() const { return extended_status_state_; } + + void setExtendedStatus(Status status) + { + sparta_assert(extended_status_state_ == Inst::Status::UNMOD + || extended_status_state_ == Inst::Status::FUSED + || extended_status_state_ == Inst::Status::FUSION_GHOST, + "Attempt to set unknown extended status : " << status << " " << *this); + + extended_status_state_ = status; + } + InstArchInfo::TargetPipe getPipe() const { return inst_arch_info_->getTargetPipe(); } // ROB handling -- mark this instruction as the oldest in the machine @@ -158,14 +175,36 @@ namespace olympia uint64_t getUniqueID() const { return unique_id_; } + // Set the instruction's UOp ID. This ID is incremented based + // off of number of Uops. The UOp instructions will all have the same + // UID, but different UOp IDs. + void setUOpID(uint64_t uopid) { uopid_ = uopid; } + + // Set the instruction's UOp ID. This ID is incremented based + // off of number of Uops. The UOp instructions will all have the same + // UID, but different UOp IDs. + uint64_t getUOpID() const { return uopid_.isValid() ? uopid_.getValue() : 0; } + + void setBlockingVSET(bool is_blocking_vset) { is_blocking_vset_ = is_blocking_vset; } + + bool isBlockingVSET() const { return is_blocking_vset_; } + // Set the instruction's Program ID. This ID is specific to // an instruction's retire pointer. The same instruction in a // trace will have the same program ID (as compared to - // UniqueID). + // UniqueID). Fusion changes this a bit see below void setProgramID(uint64_t prog_id) { program_id_ = prog_id; } uint64_t getProgramID() const { return program_id_; } + // A fused operation will modify the program_id_increment_ based on + // the number of instructions fused. A-B-C-D -> fA incr becomes 4 + // This is planned, but not currently used. + void setProgramIDIncrement(uint64_t incr) { program_id_increment_ = incr; } + + // This is planned, but not currently used. + uint64_t getProgramIDIncrement() const { return program_id_increment_; } + // Set the instruction's PC void setPC(sparta::memory::addr_t inst_pc) { inst_pc_ = inst_pc; } @@ -176,6 +215,23 @@ namespace olympia sparta::memory::addr_t getTargetVAddr() const { return target_vaddr_; } + void setVectorConfig(const VectorConfigPtr input_vector_config) + { + vector_config_ = input_vector_config; + } + + const VectorConfigPtr getVectorConfig() const { return vector_config_; } + VectorConfigPtr getVectorConfig() { return vector_config_; } + + void setTail(bool has_tail) { has_tail_ = has_tail; } + bool hasTail() const { return has_tail_; } + + void setUOpParent(sparta::SpartaWeakPointer & parent_uop) + { + parent_uop_ = parent_uop; + } + sparta::SpartaWeakPointer getUOpParent() { return parent_uop_; } + // Branch instruction was taken (always set for JAL/JALR) void setTakenBranch(bool taken) { is_taken_branch_ = taken; } @@ -197,6 +253,11 @@ namespace olympia uint32_t getOpCode() const { return static_cast(opcode_info_->getOpcode()); } + mavis::InstructionUniqueID getMavisUid() const + { + return opcode_info_->getInstructionUniqueID(); + } + // Operand information using OpInfoList = mavis::DecodedInstructionInfo::OpInfoList; @@ -207,6 +268,49 @@ namespace olympia const OpInfoList & getDestOpInfoList() const { return opcode_info_->getDestOpInfoList(); } + bool hasZeroRegSource() const + { + return std::any_of(getSourceOpInfoList().begin(), getSourceOpInfoList().end(), + [](const mavis::OperandInfo::Element & elem) + { + return elem.field_value == 0; + }); + } + + bool hasZeroRegDest() const + { + return std::any_of(getDestOpInfoList().begin(), getDestOpInfoList().end(), + [](const mavis::OperandInfo::Element & elem) + { + return elem.field_value == 0; + }); + } + + uint64_t getImmediate() const + { + sparta_assert(has_immediate_, + "Instruction does not have an immediate!"); + return opcode_info_->getImmediate(); + } + + bool getVectorMaskEnabled() const + { + try + { + // If vm bit is 0, masking is enabled + const uint64_t vm_bit = opcode_info_->getSpecialField(mavis::OpcodeInfo::SpecialField::VM); + return vm_bit == 0; + } + catch (const mavis::UnsupportedExtractorSpecialFieldID & mavis_exception) + { + return false; + } + catch (const mavis::InvalidExtractorSpecialFieldID & mavis_exception) + { + return false; + } + } + // Static instruction information bool isStoreInst() const { return is_store_; } @@ -214,6 +318,8 @@ namespace olympia uint32_t getExecuteTime() const { return inst_arch_info_->getExecutionTime(); } + InstArchInfo::UopGenType getUopGenType() const { return inst_arch_info_->getUopGenType(); } + uint64_t getRAdr() const { return target_vaddr_ | 0x8000000; } // faked bool isSpeculative() const { return is_speculative_; } @@ -228,8 +334,16 @@ namespace olympia bool isCall() const { return is_call_; } + bool isCSR() const { return is_csr_; } + bool isReturn() const { return is_return_; } + bool hasImmediate() const { return has_immediate_; } + + bool isVset() const { return inst_arch_info_->isVset(); } + + bool isVector() const { return is_vector_; } + void setCoF(const bool &cof) { is_cof_ = cof; } bool isCoF() const { return is_cof_; } @@ -271,6 +385,40 @@ namespace olympia const RenameData & getRenameData() const { return rename_data; } + mavis::OpcodeInfo::PtrType getOpCodeInfo() { return opcode_info_; } + + // Duplicates stream operator but does not change EXPECT logs + std::string info() + { + std::string rStatus = "DONTCARE"; + std::string eStatus = "UNKNOWN"; + + if (getExtendedStatus() == Inst::Status::UNMOD) + { + eStatus = "UNMOD"; + } + else if (getExtendedStatus() == Inst::Status::FUSED) + { + eStatus = "FUSED"; + } + else if (getExtendedStatus() == Inst::Status::FUSION_GHOST) + { + eStatus = "GHOST"; + } + + std::stringstream ss; + + ss << "uid: " << std::dec //<< std::hex << std::setfill('0') + << getUniqueID() << " pid: " << std::dec //<< std::hex << std::setfill('0') + << getProgramID() << " mav: 0x" << std::hex << std::setw(2) << std::setfill('0') + << getMavisUid() << " inc: " << std::dec << getProgramIDIncrement() << " pc: 0x" + << std::hex << std::setw(8) << std::setfill('0') << getPC() << " " << std::setw(10) + << std::setfill(' ') << rStatus << " " << std::setw(12) << std::setfill(' ') + << eStatus << " '" << getDisasm() << "'"; + + return ss.str(); + } + private: mavis::OpcodeInfo::PtrType opcode_info_; InstArchInfo::PtrType inst_arch_info_; @@ -279,23 +427,39 @@ namespace olympia sparta::memory::addr_t target_vaddr_ = 0; // Instruction's Target PC (for branches, loads/stores) bool is_oldest_ = false; - uint64_t unique_id_ = 0; // Supplied by Fetch - uint64_t program_id_ = 0; // Supplied by a trace Reader or execution backend + uint64_t unique_id_ = 0; // Supplied by Fetch + uint64_t program_id_ = 0; // Supplied by a trace Reader or execution backend + sparta::utils::ValidValue uopid_; // Set in decode + uint64_t program_id_increment_ = 1; bool is_speculative_ = false; // Is this instruction soon to be flushed? const bool is_store_; const bool is_transfer_; // Is this a transfer instruction (F2I/I2F) const bool is_branch_; const bool is_condbranch_; const bool is_call_; + const bool is_csr_; + const bool is_vector_; const bool is_return_; // Is this instruction a change of flow? bool is_cof_ = false; + const bool has_immediate_; + + VectorConfigPtr vector_config_{new VectorConfig}; + bool has_tail_ = false; // Does this vector uop have a tail? + + // blocking vset is a vset that needs to read a value from a register value. A blocking vset + // can't be resolved until after execution, so we need to block on it due to UOp fracturing + bool is_blocking_vset_ = false; + + sparta::SpartaWeakPointer parent_uop_; + // Did this instruction mispredict? bool is_mispredicted_ = false; bool is_taken_branch_ = false; bool last_in_fetch_block_ = false; // This is the last instruction in the fetch block sparta::Scheduleable* ev_retire_ = nullptr; Status status_state_; + Status extended_status_state_{Inst::Status::UNMOD}; using JSONIterator = uint64_t; using RewindIterator = std::variant; @@ -308,6 +472,7 @@ namespace olympia RegisterBitMaskArray dest_reg_bit_masks_; RegisterBitMaskArray store_data_mask_; RenameData rename_data; + static const std::unordered_map status2String; }; using InstPtr = Inst::PtrType; @@ -344,23 +509,44 @@ namespace olympia case Inst::Status::FLUSHED: os << "FLUSHED"; break; + // Used in extended_status_state as default case + case Inst::Status::UNMOD: + os << "UNMOD"; + break; + // The new opcode/instruction as a result of fusion + case Inst::Status::FUSED: + os << "FUSED"; + break; + // The opcodes/instruction no longer present due to fusion + case Inst::Status::FUSION_GHOST: + os << "FUSION_GHOST"; + break; case Inst::Status::__LAST: throw sparta::SpartaException("__LAST cannot be a valid enum state."); } return os; } + // Expect log info system uses simple diff + // - any changes here will break EXPECT inline std::ostream & operator<<(std::ostream & os, const Inst & inst) { os << "uid: " << inst.getUniqueID() << " " << std::setw(10) << inst.getStatus() << " " - << std::hex << inst.getPC() << std::dec << " pid: " << inst.getProgramID() << " '" - << inst.getDisasm() << "' "; + << std::hex << inst.getPC() << std::dec << " pid: " << inst.getProgramID() + << " uopid: " << inst.getUOpID() << " '" << inst.getDisasm() << "' "; return os; } inline std::ostream & operator<<(std::ostream & os, const InstPtr & inst) { - os << *inst; + if (inst) + { + os << *inst; + } + else + { + os << "nullptr"; + } return os; } diff --git a/core/InstArchInfo.cpp b/core/InstArchInfo.cpp index 8ceb3d9a..dca1a980 100644 --- a/core/InstArchInfo.cpp +++ b/core/InstArchInfo.cpp @@ -6,12 +6,55 @@ namespace olympia { const InstArchInfo::TargetPipeMap InstArchInfo::execution_pipe_map = { - {"br", InstArchInfo::TargetPipe::BR}, {"cmov", InstArchInfo::TargetPipe::CMOV}, - {"div", InstArchInfo::TargetPipe::DIV}, {"faddsub", InstArchInfo::TargetPipe::FADDSUB}, - {"float", InstArchInfo::TargetPipe::FLOAT}, {"fmac", InstArchInfo::TargetPipe::FMAC}, - {"i2f", InstArchInfo::TargetPipe::I2F}, {"f2i", InstArchInfo::TargetPipe::F2I}, - {"int", InstArchInfo::TargetPipe::INT}, {"lsu", InstArchInfo::TargetPipe::LSU}, - {"mul", InstArchInfo::TargetPipe::MUL}, {"sys", InstArchInfo::TargetPipe::SYS}}; + {"br", InstArchInfo::TargetPipe::BR}, + {"cmov", InstArchInfo::TargetPipe::CMOV}, + {"div", InstArchInfo::TargetPipe::DIV}, + {"faddsub", InstArchInfo::TargetPipe::FADDSUB}, + {"float", InstArchInfo::TargetPipe::FLOAT}, + {"fmac", InstArchInfo::TargetPipe::FMAC}, + {"i2f", InstArchInfo::TargetPipe::I2F}, + {"f2i", InstArchInfo::TargetPipe::F2I}, + {"int", InstArchInfo::TargetPipe::INT}, + {"lsu", InstArchInfo::TargetPipe::LSU}, + {"mul", InstArchInfo::TargetPipe::MUL}, + {"vint", InstArchInfo::TargetPipe::VINT}, + {"vmask", InstArchInfo::TargetPipe::VMASK}, + {"vset", InstArchInfo::TargetPipe::VSET}, + {"vmul", InstArchInfo::TargetPipe::VMUL}, + {"vdiv", InstArchInfo::TargetPipe::VDIV}, + {"sys", InstArchInfo::TargetPipe::SYS}, + {"?", InstArchInfo::TargetPipe::UNKNOWN} + }; + + const InstArchInfo::TargetPipeStringMap InstArchInfo::execution_pipe_string_map = { + {InstArchInfo::TargetPipe::BR, "BR"}, + {InstArchInfo::TargetPipe::CMOV, "CMOV"}, + {InstArchInfo::TargetPipe::DIV, "DIV"}, + {InstArchInfo::TargetPipe::FADDSUB, "FADDSUB"}, + {InstArchInfo::TargetPipe::FLOAT, "FLOAT"}, + {InstArchInfo::TargetPipe::FMAC, "FMAC"}, + {InstArchInfo::TargetPipe::I2F, "I2F"}, + {InstArchInfo::TargetPipe::F2I, "F2I"}, + {InstArchInfo::TargetPipe::INT, "INT"}, + {InstArchInfo::TargetPipe::LSU, "LSU"}, + {InstArchInfo::TargetPipe::MUL, "MUL"}, + {InstArchInfo::TargetPipe::VINT, "VINT"}, + {InstArchInfo::TargetPipe::VMASK, "VMASK"}, + {InstArchInfo::TargetPipe::VSET, "VSET"}, + {InstArchInfo::TargetPipe::VMUL, "VMUL"}, + {InstArchInfo::TargetPipe::VDIV, "VDIV"}, + {InstArchInfo::TargetPipe::SYS, "SYS"}, + {InstArchInfo::TargetPipe::UNKNOWN, "?"} + }; + + const InstArchInfo::UopGenMap InstArchInfo::uop_gen_type_map = { + {"ARITH", InstArchInfo::UopGenType::ARITH}, + {"ARITH_SINGLE_DEST", InstArchInfo::UopGenType::ARITH_SINGLE_DEST}, + {"ARITH_WIDE_DEST", InstArchInfo::UopGenType::ARITH_WIDE_DEST}, + {"ARITH_MAC", InstArchInfo::UopGenType::ARITH_MAC}, + {"ARITH_MAC_WIDE_DEST", InstArchInfo::UopGenType::ARITH_MAC_WIDE_DEST}, + {"NONE", InstArchInfo::UopGenType::NONE} + }; void InstArchInfo::update(const nlohmann::json & jobj) { @@ -24,17 +67,24 @@ namespace olympia << jobj["mnemonic"].get()); tgt_pipe_ = itr->second; } - sparta_assert(tgt_pipe_ != TargetPipe::UNKNOWN, "Unknown target pipe (execution) for " - << jobj["mnemonic"].get()); if (jobj.find("latency") != jobj.end()) { execute_time_ = jobj["latency"].get(); } - sparta_assert(execute_time_ != 0, "Unknown execution time (latency) for " - << jobj["mnemonic"].get()); + + if (jobj.find("uop_gen") != jobj.end()) + { + auto uop_gen_name = jobj["uop_gen"].get(); + const auto itr = uop_gen_type_map.find(uop_gen_name); + sparta_assert(itr != uop_gen_type_map.end(), + "Unknown uop gen: " << uop_gen_name << " for inst: " + << jobj["mnemonic"].get()); + uop_gen_ = itr->second; + } is_load_store_ = (tgt_pipe_ == TargetPipe::LSU); + is_vset_ = {tgt_pipe_ == TargetPipe::VSET}; } } // namespace olympia diff --git a/core/InstArchInfo.hpp b/core/InstArchInfo.hpp index 7f2b57ed..8ad855a5 100644 --- a/core/InstArchInfo.hpp +++ b/core/InstArchInfo.hpp @@ -35,7 +35,7 @@ namespace olympia public: using PtrType = sparta::SpartaSharedPointer; - enum TargetPipe : std::uint16_t + enum TargetPipe : uint16_t { BR, CMOV, @@ -48,6 +48,11 @@ namespace olympia INT, LSU, MUL, + VINT, + VMASK, + VMUL, + VDIV, + VSET, SYS, UNKNOWN }; @@ -57,6 +62,25 @@ namespace olympia using TargetPipeMap = std::map; static const TargetPipeMap execution_pipe_map; + using TargetPipeStringMap = std::map; + static const TargetPipeStringMap execution_pipe_string_map; + + enum class UopGenType + { + ARITH, + ARITH_SINGLE_DEST, + ARITH_WIDE_DEST, + ARITH_MAC, + ARITH_MAC_WIDE_DEST, + NONE, + UNKNOWN + }; + + static constexpr uint32_t N_UOP_GEN_TYPES = static_cast(UopGenType::NONE); + + using UopGenMap = std::map; + static const UopGenMap uop_gen_type_map; + // Called by Mavis during its initialization explicit InstArchInfo(const nlohmann::json & jobj) { update(jobj); } @@ -70,57 +94,31 @@ namespace olympia //! Return the execution time (latency) of the instruction uint32_t getExecutionTime() const { return execute_time_; } + //! Return the vector uop generator type + UopGenType getUopGenType() const { return uop_gen_; } + //! Is this instruction a load/store type? bool isLoadStore() const { return is_load_store_; } + //! Is this instruction a vset instruction type + bool isVset() const { return is_vset_; } + private: TargetPipe tgt_pipe_ = TargetPipe::UNKNOWN; uint32_t execute_time_ = 0; + UopGenType uop_gen_ = UopGenType::UNKNOWN; bool is_load_store_ = false; + bool is_vset_ = false; }; inline std::ostream & operator<<(std::ostream & os, const InstArchInfo::TargetPipe & pipe) { - switch (pipe) + if (pipe != InstArchInfo::TargetPipe::UNKNOWN) + { + os << InstArchInfo::execution_pipe_string_map.at(pipe); + } + else { - case InstArchInfo::TargetPipe::BR: - os << "BR"; - break; - case InstArchInfo::TargetPipe::CMOV: - os << "CMOV"; - break; - case InstArchInfo::TargetPipe::DIV: - os << "DIV"; - break; - case InstArchInfo::TargetPipe::FADDSUB: - os << "FADDSUB"; - break; - case InstArchInfo::TargetPipe::FLOAT: - os << "FLOAT"; - break; - case InstArchInfo::TargetPipe::FMAC: - os << "FMAC"; - break; - case InstArchInfo::TargetPipe::I2F: - os << "I2F"; - break; - case InstArchInfo::TargetPipe::F2I: - os << "F2I"; - break; - case InstArchInfo::TargetPipe::INT: - os << "INT"; - break; - case InstArchInfo::TargetPipe::LSU: - os << "LSU"; - break; - case InstArchInfo::TargetPipe::MUL: - os << "MUL"; - break; - case InstArchInfo::TargetPipe::SYS: - os << "SYS"; - break; - - case InstArchInfo::TargetPipe::UNKNOWN: throw sparta::SpartaException("Got UNKNOWN/NONE target pipe."); } return os; diff --git a/core/InstGenerator.cpp b/core/InstGenerator.cpp index ed8dd068..385b66f8 100644 --- a/core/InstGenerator.cpp +++ b/core/InstGenerator.cpp @@ -1,45 +1,52 @@ #include "InstGenerator.hpp" -#include "json.hpp" // From Mavis +#include "json.hpp" // From Mavis #include "mavis/Mavis.h" namespace olympia { - std::unique_ptr InstGenerator::createGenerator(MavisType * mavis_facade, + std::unique_ptr InstGenerator::createGenerator(MavisType* mavis_facade, const std::string & filename, const bool skip_nonuser_mode) { const std::string json_ext = "json"; - if((filename.size() > json_ext.size()) && filename.substr(filename.size()-json_ext.size()) == json_ext) { + if ((filename.size() > json_ext.size()) + && filename.substr(filename.size() - json_ext.size()) == json_ext) + { std::cout << "olympia: JSON file input detected" << std::endl; return std::unique_ptr(new JSONInstGenerator(mavis_facade, filename)); } - const std::string stf_ext = "stf"; // Should cover both zstf and stf - if((filename.size() > stf_ext.size()) && filename.substr(filename.size()-stf_ext.size()) == stf_ext) { + const std::string stf_ext = "stf"; // Should cover both zstf and stf + if ((filename.size() > stf_ext.size()) + && filename.substr(filename.size() - stf_ext.size()) == stf_ext) + { std::cout << "olympia: STF file input detected" << std::endl; - return std::unique_ptr(new TraceInstGenerator(mavis_facade, filename, skip_nonuser_mode)); + return std::unique_ptr( + new TraceInstGenerator(mavis_facade, filename, skip_nonuser_mode)); } // Dunno what it is... sparta_assert(false, "Unknown file extension for '" << filename - << "'. Expected .json or .[z]stf"); + << "'. Expected .json or .[z]stf"); return nullptr; } //////////////////////////////////////////////////////////////////////////////// // JSON Inst Generator - JSONInstGenerator::JSONInstGenerator(MavisType * mavis_facade, - const std::string & filename) : + JSONInstGenerator::JSONInstGenerator(MavisType* mavis_facade, const std::string & filename) : InstGenerator(mavis_facade) { std::ifstream fs; std::ios_base::iostate exceptionMask = fs.exceptions() | std::ios::failbit; fs.exceptions(exceptionMask); - try { + try + { fs.open(filename); - } catch (const std::ifstream::failure &e) { + } + catch (const std::ifstream::failure & e) + { throw sparta::SpartaException("ERROR: Issues opening ") << filename << ": " << e.what(); } @@ -48,9 +55,7 @@ namespace olympia n_insts_ = jobj_->size(); } - bool JSONInstGenerator::isDone() const { - return (curr_inst_index_ >= n_insts_); - } + bool JSONInstGenerator::isDone() const { return (curr_inst_index_ >= n_insts_); } void JSONInstGenerator::reset(const InstPtr & inst_ptr, const bool skip = false) { @@ -63,60 +68,108 @@ namespace olympia } } - InstPtr JSONInstGenerator::getNextInst(const sparta::Clock * clk) + InstPtr JSONInstGenerator::getNextInst(const sparta::Clock* clk) { - if(SPARTA_EXPECT_FALSE(isDone())) { + if (SPARTA_EXPECT_FALSE(isDone())) + { return nullptr; } // Get the JSON record at the current index nlohmann::json jinst = jobj_->at(curr_inst_index_); - - if (jinst.find("mnemonic") == jinst.end()) { - throw sparta::SpartaException() << "Missing mnemonic at " << curr_inst_index_; - } - const std::string mnemonic = jinst["mnemonic"]; - - auto addElement = [&jinst] (mavis::OperandInfo & operands, - const std::string & key, - const mavis::InstMetaData::OperandFieldID operand_field_id, - const mavis::InstMetaData::OperandTypes operand_type) { - if(jinst.find(key) != jinst.end()) { - operands.addElement(operand_field_id, - operand_type, - jinst[key].get()); - } - }; - - mavis::OperandInfo srcs; - addElement(srcs, "rs1", mavis::InstMetaData::OperandFieldID::RS1, mavis::InstMetaData::OperandTypes::LONG); - addElement(srcs, "fs1", mavis::InstMetaData::OperandFieldID::RS1, mavis::InstMetaData::OperandTypes::DOUBLE); - addElement(srcs, "rs2", mavis::InstMetaData::OperandFieldID::RS2, mavis::InstMetaData::OperandTypes::LONG); - addElement(srcs, "fs2", mavis::InstMetaData::OperandFieldID::RS2, mavis::InstMetaData::OperandTypes::DOUBLE); - - mavis::OperandInfo dests; - addElement(dests, "rd", mavis::InstMetaData::OperandFieldID::RD, mavis::InstMetaData::OperandTypes::LONG); - addElement(dests, "fd", mavis::InstMetaData::OperandFieldID::RD, mavis::InstMetaData::OperandTypes::DOUBLE); - InstPtr inst; - if(jinst.find("imm") != jinst.end()) { - const uint64_t imm = jinst["imm"].get(); - mavis::ExtractorDirectOpInfoList ex_info(mnemonic, srcs, dests, imm); - inst = mavis_facade_->makeInstDirectly(ex_info, clk); - } - else { - mavis::ExtractorDirectOpInfoList ex_info(mnemonic, srcs, dests); - inst = mavis_facade_->makeInstDirectly(ex_info, clk); + if (jinst.find("opcode") != jinst.end()) + { + uint64_t opcode = std::strtoull(jinst["opcode"].get().c_str(), nullptr, 0); + inst = mavis_facade_->makeInst(opcode, clk); } + else + { + if (jinst.find("mnemonic") == jinst.end()) + { + throw sparta::SpartaException() << "Missing mnemonic at " << curr_inst_index_; + } + const std::string mnemonic = jinst["mnemonic"]; - if (jinst.find("vaddr") != jinst.end()) { - uint64_t vaddr = std::strtoull(jinst["vaddr"].get().c_str(), nullptr, 0); - inst->setTargetVAddr(vaddr); - } + auto addElement = [&jinst](mavis::OperandInfo & operands, const std::string & key, + const mavis::InstMetaData::OperandFieldID operand_field_id, + const mavis::InstMetaData::OperandTypes operand_type) + { + if (jinst.find(key) != jinst.end()) + { + operands.addElement(operand_field_id, operand_type, jinst[key].get()); + } + }; + + mavis::OperandInfo srcs; + addElement(srcs, "rs1", mavis::InstMetaData::OperandFieldID::RS1, + mavis::InstMetaData::OperandTypes::LONG); + addElement(srcs, "fs1", mavis::InstMetaData::OperandFieldID::RS1, + mavis::InstMetaData::OperandTypes::DOUBLE); + addElement(srcs, "rs2", mavis::InstMetaData::OperandFieldID::RS2, + mavis::InstMetaData::OperandTypes::LONG); + addElement(srcs, "fs2", mavis::InstMetaData::OperandFieldID::RS2, + mavis::InstMetaData::OperandTypes::DOUBLE); + addElement(srcs, "vs1", mavis::InstMetaData::OperandFieldID::RS1, + mavis::InstMetaData::OperandTypes::VECTOR); + addElement(srcs, "vs2", mavis::InstMetaData::OperandFieldID::RS2, + mavis::InstMetaData::OperandTypes::VECTOR); + + mavis::OperandInfo dests; + addElement(dests, "rd", mavis::InstMetaData::OperandFieldID::RD, + mavis::InstMetaData::OperandTypes::LONG); + addElement(dests, "fd", mavis::InstMetaData::OperandFieldID::RD, + mavis::InstMetaData::OperandTypes::DOUBLE); + addElement(dests, "vd", mavis::InstMetaData::OperandFieldID::RD, + mavis::InstMetaData::OperandTypes::VECTOR); + + if (jinst.find("imm") != jinst.end()) + { + const uint64_t imm = jinst["imm"].get(); + mavis::ExtractorDirectOpInfoList ex_info(mnemonic, srcs, dests, imm); + inst = mavis_facade_->makeInstDirectly(ex_info, clk); + } + else + { + mavis::ExtractorDirectOpInfoList ex_info(mnemonic, srcs, dests); + inst = mavis_facade_->makeInstDirectly(ex_info, clk); + } + + if (jinst.find("vaddr") != jinst.end()) + { + uint64_t vaddr = std::strtoull(jinst["vaddr"].get().c_str(), nullptr, 0); + inst->setTargetVAddr(vaddr); + } + + VectorConfigPtr vector_config = inst->getVectorConfig(); + if (jinst.find("vtype") != jinst.end()) + { + // immediate, so decode from hex + uint64_t vtype = std::strtoull(jinst["vtype"].get().c_str(), nullptr, 0); + std::string binaryString = std::bitset<32>(vtype).to_string(); + uint32_t sew = std::pow(2, std::stoi(binaryString.substr(26, 3), nullptr, 2)) * 8; + uint32_t lmul = std::pow(2, std::stoi(binaryString.substr(29, 3), nullptr, 2)); + vector_config->setLMUL(lmul); + vector_config->setSEW(sew); + } + + if (jinst.find("vta") != jinst.end()) + { + const bool vta = jinst["vta"].get() > 0 ? true: false; + vector_config->setVTA(vta); + } - if (jinst.find("taken") != jinst.end()) { - const bool taken = jinst["taken"].get(); - inst->setTakenBranch(taken); + if (jinst.find("vl") != jinst.end()) + { + const uint64_t vl = jinst["vl"].get(); + vector_config->setVL(vl); + } + + if (jinst.find("taken") != jinst.end()) + { + const bool taken = jinst["taken"].get(); + inst->setTakenBranch(taken); + } } inst->setRewindIterator(curr_inst_index_); @@ -124,13 +177,11 @@ namespace olympia inst->setProgramID(program_id_++); ++curr_inst_index_; return inst; - } //////////////////////////////////////////////////////////////////////////////// // STF Inst Generator - TraceInstGenerator::TraceInstGenerator(MavisType * mavis_facade, - const std::string & filename, + TraceInstGenerator::TraceInstGenerator(MavisType* mavis_facade, const std::string & filename, const bool skip_nonuser_mode) : InstGenerator(mavis_facade) { @@ -138,9 +189,12 @@ namespace olympia std::ios_base::iostate exceptionMask = fs.exceptions() | std::ios::failbit; fs.exceptions(exceptionMask); - try { + try + { fs.open(filename); - } catch (const std::ifstream::failure &e) { + } + catch (const std::ifstream::failure & e) + { throw sparta::SpartaException("ERROR: Issues opening ") << filename << ": " << e.what(); } @@ -151,19 +205,14 @@ namespace olympia // value. Required for traces that stay in machine mode the entire // time constexpr bool FILTER_MODE_CHANGE_EVENTS = true; - constexpr size_t BUFFER_SIZE = 4096; - reader_.reset(new stf::STFInstReader(filename, - skip_nonuser_mode, - CHECK_FOR_STF_PTE, - FILTER_MODE_CHANGE_EVENTS, - BUFFER_SIZE)); + constexpr size_t BUFFER_SIZE = 4096; + reader_.reset(new stf::STFInstReader(filename, skip_nonuser_mode, CHECK_FOR_STF_PTE, + FILTER_MODE_CHANGE_EVENTS, BUFFER_SIZE)); next_it_ = reader_->begin(); } - bool TraceInstGenerator::isDone() const { - return next_it_ == reader_->end(); - } + bool TraceInstGenerator::isDone() const { return next_it_ == reader_->end(); } void TraceInstGenerator::reset(const InstPtr & inst_ptr, const bool skip = false) { @@ -176,32 +225,32 @@ namespace olympia } } - InstPtr TraceInstGenerator::getNextInst(const sparta::Clock * clk) + InstPtr TraceInstGenerator::getNextInst(const sparta::Clock* clk) { - if(SPARTA_EXPECT_FALSE(isDone())) { + if (SPARTA_EXPECT_FALSE(isDone())) + { return nullptr; } mavis::Opcode opcode = next_it_->opcode(); - try { + try + { InstPtr inst = mavis_facade_->makeInst(opcode, clk); inst->setPC(next_it_->pc()); inst->setUniqueID(++unique_id_); inst->setProgramID(program_id_++); inst->setRewindIterator(next_it_); - if (const auto& mem_accesses = next_it_->getMemoryAccesses(); !mem_accesses.empty()) + if (const auto & mem_accesses = next_it_->getMemoryAccesses(); !mem_accesses.empty()) { using VectorAddrType = std::vector; VectorAddrType addrs; std::for_each(next_it_->getMemoryAccesses().begin(), next_it_->getMemoryAccesses().end(), - [&addrs] (const auto & ma) { - addrs.emplace_back(ma.getAddress()); - }); + [&addrs](const auto & ma) { addrs.emplace_back(ma.getAddress()); }); inst->setTargetVAddr(addrs.front()); - //For misaligns, more than 1 address is provided - //inst->setVAddrVector(std::move(addrs)); + // For misaligns, more than 1 address is provided + // inst->setVAddrVector(std::move(addrs)); } inst->setCoF(next_it_->isCoF()); if (next_it_->isBranch()) @@ -212,15 +261,14 @@ namespace olympia ++next_it_; return inst; } - catch(std::exception & excpt) { - std::cerr << "ERROR: Mavis failed decoding: 0x" - << std::hex << opcode << " for STF It PC: 0x" - << next_it_->pc() << " STFID: " << std::dec - << next_it_->index() << " err: " - << excpt.what() << std::endl; + catch (std::exception & excpt) + { + std::cerr << "ERROR: Mavis failed decoding: 0x" << std::hex << opcode + << " for STF It PC: 0x" << next_it_->pc() << " STFID: " << std::dec + << next_it_->index() << " err: " << excpt.what() << std::endl; throw; } return nullptr; } -} +} // namespace olympia diff --git a/core/InstGroup.hpp b/core/InstGroup.hpp index a387f3e0..51a2e717 100644 --- a/core/InstGroup.hpp +++ b/core/InstGroup.hpp @@ -29,6 +29,14 @@ namespace olympia insts_.emplace_back(inst); } + iterator erase(iterator first, iterator last) { + return insts_.erase(first, last); + } + + iterator erase(iterator pos) { + return insts_.erase(pos); + } + iterator begin() { return insts_.begin(); } iterator end() { return insts_.end(); } diff --git a/core/IssueQueue.cpp b/core/IssueQueue.cpp index cbc817ad..afcabcd1 100644 --- a/core/IssueQueue.cpp +++ b/core/IssueQueue.cpp @@ -35,8 +35,7 @@ namespace olympia { cpu_node = getContainer()->getRoot(); } - std::vector reg_files = {core_types::RF_INTEGER, core_types::RF_FLOAT}; - for (const auto rf : reg_files) + for (uint32_t rf = 0; rf < core_types::RegFile::N_REGFILES; ++rf) { scoreboard_views_[rf].reset(new sparta::ScoreboardView( getContainer()->getName(), core_types::regfile_names[rf], cpu_node)); @@ -98,33 +97,61 @@ namespace olympia void IssueQueue::handleOperandIssueCheck_(const InstPtr & ex_inst) { - // FIXME: Now every source operand should be ready - auto reg_file = core_types::RegFile::RF_INTEGER; const auto srcs = ex_inst->getRenameData().getSourceList(); - if (srcs.size() > 0) + + // Lambda function to check if a source is ready. + // Returns true if source is ready. + // Returns false and registers a callback if source is not ready. + auto check_src_ready = [this, ex_inst](const Inst::RenameData::Reg & src) + { + // vector-scalar operations have 1 vector src and 1 scalar src that + // need to be checked, so can't assume the register files are the + // same for every source + auto reg_file = src.rf; + const auto & src_bits = ex_inst->getSrcRegisterBitMask(reg_file); + if (scoreboard_views_[reg_file]->isSet(src_bits)) + { + return true; + } + else + { + // temporary fix for clearCallbacks not working + scoreboard_views_[reg_file]->registerReadyCallback(src_bits, ex_inst->getUniqueID(), + [this, ex_inst](const sparta::Scoreboard::RegisterBitMask &) + { + this->handleOperandIssueCheck_(ex_inst); + } + ); + return false; + } + }; + + bool all_srcs_ready = true; + for (const auto & src : srcs) { - reg_file = srcs[0].rf; + const bool src_ready = check_src_ready(src); + + if (!src_ready) + { + ILOG("Instruction NOT ready: " << ex_inst << + " Bits needed:" << sparta::printBitSet(ex_inst->getSrcRegisterBitMask(src.rf)) << + " rf: " << src.rf); + all_srcs_ready = false; + // we break to prevent multiple callbacks from being sent out + break; + } } - const auto & src_bits = ex_inst->getSrcRegisterBitMask(reg_file); - if (scoreboard_views_[reg_file]->isSet(src_bits)) + + // we wait till the final callback comes back and checks in the case where both RF are ready at the same time + if (all_srcs_ready) { - // Insert at the end if we are doing in order issue or if the scheduler is - // empty + // all register file types are ready ILOG("Sending to issue queue " << ex_inst); // will insert based on if in_order_issue_ is set // if it is, will be first in first out, if not it'll be by age, so by UniqueID (UID) ready_queue_.insert(ex_inst); ev_issue_ready_inst_.schedule(sparta::Clock::Cycle(0)); } - else - { - scoreboard_views_[reg_file]->registerReadyCallback( - src_bits, ex_inst->getUniqueID(), - [this, ex_inst](const sparta::Scoreboard::RegisterBitMask &) - { this->handleOperandIssueCheck_(ex_inst); }); - ILOG("Instruction NOT ready: " << ex_inst - << " Bits needed:" << sparta::printBitSet(src_bits)); - } } void IssueQueue::readyExeUnit_(const uint32_t & readyExe) @@ -243,4 +270,4 @@ namespace olympia } sparta_assert(false, "Attempt to complete instruction no longer exiting in issue queue!"); } -} // namespace olympia \ No newline at end of file +} // namespace olympia diff --git a/core/LSU.cpp b/core/LSU.cpp index 31735c04..2324cddd 100644 --- a/core/LSU.cpp +++ b/core/LSU.cpp @@ -150,14 +150,16 @@ namespace olympia void LSU::setupScoreboard_() { // Setup scoreboard view upon register file - std::vector reg_files = {core_types::RF_INTEGER, core_types::RF_FLOAT}; - // if we ever move to multicore, we only want to have resources look for scoreboard in their cpu - // if we're running a test where we only have top.rename or top.issue_queue, then we can just use the root + // if we ever move to multicore, we only want to have resources look for scoreboard in their + // cpu if we're running a test where we only have top.rename or top.issue_queue, then we can + // just use the root auto cpu_node = getContainer()->findAncestorByName("core.*"); - if(cpu_node == nullptr){ + if (cpu_node == nullptr) + { cpu_node = getContainer()->getRoot(); } - for (const auto rf : reg_files) + for (uint32_t rf = 0; rf < core_types::RegFile::N_REGFILES; + ++rf) // for (const auto rf : reg_files) { scoreboard_views_[rf].reset(new sparta::ScoreboardView( getContainer()->getName(), core_types::regfile_names[rf], cpu_node)); @@ -516,7 +518,34 @@ namespace olympia out_cache_lookup_req_.send(mem_access_info_ptr); } - void LSU::getAckFromCache_(const MemoryAccessInfoPtr & updated_memory_access_info_ptr) {} + void LSU::getAckFromCache_(const MemoryAccessInfoPtr & mem_access_info_ptr) + { + const LoadStoreInstIterator & iter = mem_access_info_ptr->getIssueQueueIterator(); + if (!iter.isValid()) + { + return; + } + + // Is its a cache miss we dont need to rechedule the instruction + if (!mem_access_info_ptr->isCacheHit()) + { + return; + } + + const LoadStoreInstInfoPtr & inst_info_ptr = *(iter); + + // Update issue priority for this outstanding cache miss + if (inst_info_ptr->getState() != LoadStoreInstInfo::IssueState::ISSUED) + { + inst_info_ptr->setState(LoadStoreInstInfo::IssueState::READY); + } + + inst_info_ptr->setPriority(LoadStoreInstInfo::IssuePriority::CACHE_RELOAD); + if (!inst_info_ptr->isInReadyQueue()) + { + uev_append_ready_.preparePayload(inst_info_ptr)->schedule(sparta::Clock::Cycle(0)); + } + } void LSU::handleCacheReadyReq_(const MemoryAccessInfoPtr & memory_access_info_ptr) { @@ -756,9 +785,8 @@ namespace olympia flushReadyQueue_(criteria); // Cancel replay events - auto flush = [&criteria](const LoadStoreInstInfoPtr & ldst_info_ptr) -> bool { - return criteria.includedInFlush(ldst_info_ptr->getInstPtr()); - }; + auto flush = [&criteria](const LoadStoreInstInfoPtr & ldst_info_ptr) -> bool + { return criteria.includedInFlush(ldst_info_ptr->getInstPtr()); }; uev_append_ready_.cancelIf(flush); uev_replay_ready_.cancelIf(flush); @@ -1175,9 +1203,8 @@ namespace olympia { const InstPtr & inst_ptr = mem_access_info_ptr->getInstPtr(); - sparta_assert( - inst_ptr->getFlushedStatus() == false, - "Attempt to rehandle cache lookup for flushed instruction!"); + sparta_assert(inst_ptr->getFlushedStatus() == false, + "Attempt to rehandle cache lookup for flushed instruction!"); const LoadStoreInstIterator & iter = mem_access_info_ptr->getIssueQueueIterator(); sparta_assert( @@ -1242,17 +1269,20 @@ namespace olympia uint32_t credits_to_send = 0; auto iter = ldst_inst_queue_.begin(); - while (iter != ldst_inst_queue_.end()) { + while (iter != ldst_inst_queue_.end()) + { auto inst_ptr = (*iter)->getInstPtr(); auto delete_iter = iter++; - if (criteria.includedInFlush(inst_ptr)) { + if (criteria.includedInFlush(inst_ptr)) + { ldst_inst_queue_.erase(delete_iter); // Clear any scoreboard callback - std::vector reg_files = {core_types::RF_INTEGER, core_types::RF_FLOAT}; - for(const auto rf : reg_files) + std::vector reg_files = {core_types::RF_INTEGER, + core_types::RF_FLOAT}; + for (const auto rf : reg_files) { scoreboard_views_[rf]->clearCallbacks(inst_ptr->getUniqueID()); } @@ -1278,18 +1308,21 @@ namespace olympia void LSU::flushLSPipeline_(const FlushCriteria & criteria) { uint32_t stage_id = 0; - for (auto iter = ldst_pipeline_.begin(); iter != ldst_pipeline_.end(); iter++, stage_id++) { + for (auto iter = ldst_pipeline_.begin(); iter != ldst_pipeline_.end(); iter++, stage_id++) + { // If the pipe stage is already invalid, no need to criteria - if (!iter.isValid()) { + if (!iter.isValid()) + { continue; } auto inst_ptr = (*iter)->getInstPtr(); - if (criteria.includedInFlush(inst_ptr)) { + if (criteria.includedInFlush(inst_ptr)) + { ldst_pipeline_.flushStage(iter); ILOG("Flush Pipeline Stage[" << stage_id - << "], Instruction ID: " << inst_ptr->getUniqueID()); + << "], Instruction ID: " << inst_ptr->getUniqueID()); } } } @@ -1297,12 +1330,14 @@ namespace olympia void LSU::flushReadyQueue_(const FlushCriteria & criteria) { auto iter = ready_queue_.begin(); - while (iter != ready_queue_.end()) { + while (iter != ready_queue_.end()) + { auto inst_ptr = (*iter)->getInstPtr(); auto delete_iter = iter++; - if (criteria.includedInFlush(inst_ptr)) { + if (criteria.includedInFlush(inst_ptr)) + { ready_queue_.erase(delete_iter); ILOG("Flushing from ready queue - Instruction ID: " << inst_ptr->getUniqueID()); } @@ -1312,12 +1347,14 @@ namespace olympia void LSU::flushReplayBuffer_(const FlushCriteria & criteria) { auto iter = replay_buffer_.begin(); - while (iter != replay_buffer_.end()) { + while (iter != replay_buffer_.end()) + { auto inst_ptr = (*iter)->getInstPtr(); auto delete_iter = iter++; - if (criteria.includedInFlush(inst_ptr)) { + if (criteria.includedInFlush(inst_ptr)) + { replay_buffer_.erase(delete_iter); ILOG("Flushing from replay buffer - Instruction ID: " << inst_ptr->getUniqueID()); } diff --git a/core/MSHREntryInfo.hpp b/core/MSHREntryInfo.hpp new file mode 100644 index 00000000..f2e37845 --- /dev/null +++ b/core/MSHREntryInfo.hpp @@ -0,0 +1,44 @@ +#pragma once + +#include "CacheFuncModel.hpp" + +namespace olympia +{ + class MSHREntryInfo + { + public: + MSHREntryInfo(const uint64_t & line_size, const sparta::Clock* clock) : + line_fill_buffer_(line_size) + { + line_fill_buffer_.setValid(true); + } + + ~MSHREntryInfo() {} + + SimpleCacheLine & getLineFillBuffer() { return line_fill_buffer_; } + + bool isValid() const { return line_fill_buffer_.isValid(); } + + void setValid(bool v) { line_fill_buffer_.setValid(v); } + + bool isModified() const { return line_fill_buffer_.isModified(); } + + void setModified(bool m) { line_fill_buffer_.setModified(m); } + + void setDataArrived(bool v) { data_arrived_ = v; } + + bool isDataArrived() { return data_arrived_; } + + void setMemRequest(const MemoryAccessInfoPtr & new_memory_access_info) + { + memory_access_info_ = new_memory_access_info; + } + + MemoryAccessInfoPtr & getMemRequest() { return memory_access_info_; } + + private: + SimpleCacheLine line_fill_buffer_; + MemoryAccessInfoPtr memory_access_info_; + bool data_arrived_ = false; + }; +} // namespace olympia \ No newline at end of file diff --git a/core/MavisUnit.cpp b/core/MavisUnit.cpp index 44ee0d6e..90ef92e5 100644 --- a/core/MavisUnit.cpp +++ b/core/MavisUnit.cpp @@ -16,13 +16,20 @@ namespace olympia std::vector getISAFiles(sparta::TreeNode *n, const std::string & isa_file_path, const std::string& pseudo_file_path) { - std::vector isa_files = {isa_file_path + "/isa_rv64g.json", + std::vector isa_files = {isa_file_path + "/isa_rv64i.json", + isa_file_path + "/isa_rv64m.json", + isa_file_path + "/isa_rv64a.json", + isa_file_path + "/isa_rv64f.json", + isa_file_path + "/isa_rv64d.json", isa_file_path + "/isa_rv64zba.json", isa_file_path + "/isa_rv64zbb.json", isa_file_path + "/isa_rv64zbs.json", + isa_file_path + "/isa_rv64zicsr.json", isa_file_path + "/isa_rv64c.json", isa_file_path + "/isa_rv64cf.json", - isa_file_path + "/isa_rv64cd.json"}; + isa_file_path + "/isa_rv64cd.json", + isa_file_path + "/isa_rv64v.json", + isa_file_path + "/isa_rv64vf.json"}; return isa_files; } @@ -31,7 +38,8 @@ namespace olympia { std::vector uarch_files = {uarch_file_path + "/olympia_uarch_rv64g.json", uarch_file_path + "/olympia_uarch_rv64c.json", - uarch_file_path + "/olympia_uarch_rv64b.json"}; + uarch_file_path + "/olympia_uarch_rv64b.json", + uarch_file_path + "/olympia_uarch_rv64v.json"}; if(false == std::string(p->uarch_overrides_json).empty()) { uarch_files.emplace_back(p->uarch_overrides_json); diff --git a/core/MavisUnit.hpp b/core/MavisUnit.hpp index 618f296b..6e063c41 100644 --- a/core/MavisUnit.hpp +++ b/core/MavisUnit.hpp @@ -38,6 +38,9 @@ namespace olympia // Handy UIDs that the modeler can assign to an instruction for // compare constexpr mavis::InstructionUniqueID MAVIS_UID_NOP = 1; + constexpr mavis::InstructionUniqueID MAVIS_UID_VSETIVLI = 4; + constexpr mavis::InstructionUniqueID MAVIS_UID_VSETVLI = 3; + constexpr mavis::InstructionUniqueID MAVIS_UID_VSETVL = 2; // This is a sparta tree node wrapper around the Mavis facade object // Used to provide global access to the facade @@ -86,7 +89,10 @@ namespace olympia //! Mavis Instruction ID's that we want to use in Olympia static inline mavis::InstUIDList mavis_uid_list_ { { "nop", MAVIS_UID_NOP }, - }; + { "vsetivli", MAVIS_UID_VSETIVLI }, + { "vsetvli", MAVIS_UID_VSETVLI }, + { "vsetvl", MAVIS_UID_VSETVL }, + }; const std::string pseudo_file_path_; ///< Path to olympia pseudo ISA/uArch JSON files std::unique_ptr mavis_facade_; ///< Mavis facade object diff --git a/core/MemoryAccessInfo.hpp b/core/MemoryAccessInfo.hpp index 133f3afa..0c92c434 100644 --- a/core/MemoryAccessInfo.hpp +++ b/core/MemoryAccessInfo.hpp @@ -18,10 +18,15 @@ namespace olympia class MemoryAccessInfoPairDef; class MemoryAccessInfo; + class MSHREntryInfo; using MemoryAccessInfoPtr = sparta::SpartaSharedPointer; using MemoryAccessInfoAllocator = sparta::SpartaSharedPointerAllocator; + using MSHREntryInfoPtr = sparta::SpartaSharedPointer; + using MSHREntryInfoIterator = sparta::Buffer::const_iterator; + using MSHREntryInfoAllocator = sparta::SpartaSharedPointerAllocator; + class MemoryAccessInfo { public: @@ -89,6 +94,7 @@ namespace olympia // Construct the State object here cache_access_state_(CacheState::NO_ACCESS), cache_data_ready_(false), + is_refill_(false), src_(ArchUnit::NO_ACCESS), dest_(ArchUnit::NO_ACCESS), vaddr_(inst_ptr->getTargetVAddr()), @@ -155,6 +161,10 @@ namespace olympia const LoadStoreInstIterator getIssueQueueIterator() const { return issue_queue_iterator_; } + bool isRefill() const { return is_refill_; } + + void setIsRefill(bool is_refill) { is_refill_ = is_refill; } + void setIssueQueueIterator(const LoadStoreInstIterator & iter) { issue_queue_iterator_ = iter; @@ -170,6 +180,16 @@ namespace olympia replay_queue_iterator_ = iter; } + const MSHREntryInfoIterator & getMSHRInfoIterator() const + { + return mshr_entry_info_iterator_; + } + + void setMSHREntryInfoIterator(const MSHREntryInfoIterator & iter) + { + mshr_entry_info_iterator_ = iter; + } + private: // load/store instruction pointer const InstPtr ldst_inst_ptr_; @@ -184,6 +204,8 @@ namespace olympia CacheState cache_access_state_; bool cache_data_ready_; + + bool is_refill_; // Src and destination unit name for the packet ArchUnit src_ = ArchUnit::NO_ACCESS; ArchUnit dest_ = ArchUnit::NO_ACCESS; @@ -205,6 +227,7 @@ namespace olympia LoadStoreInstIterator issue_queue_iterator_; LoadStoreInstIterator replay_queue_iterator_; + MSHREntryInfoIterator mshr_entry_info_iterator_; }; using MemoryAccessInfoPtr = sparta::SpartaSharedPointer; diff --git a/core/ROB.cpp b/core/ROB.cpp index a757dbcc..a262b136 100644 --- a/core/ROB.cpp +++ b/core/ROB.cpp @@ -1,30 +1,27 @@ // -*- C++ -*- - #include #include "ROB.hpp" #include "sparta/utils/LogUtils.hpp" #include "sparta/events/StartupEvent.hpp" +#include "CoreUtils.hpp" namespace olympia { const char ROB::name[] = "rob"; - ROB::ROB(sparta::TreeNode * node, - const ROBParameterSet * p) : + ROB::ROB(sparta::TreeNode* node, const ROBParameterSet* p) : sparta::Unit(node), - stat_ipc_(&unit_stat_set_, - "ipc", - "Instructions retired per cycle", - &unit_stat_set_, + stat_ipc_(&unit_stat_set_, "ipc", "Instructions retired per cycle", &unit_stat_set_, "total_number_retired/cycles"), - num_retired_(&unit_stat_set_, - "total_number_retired", + num_retired_(&unit_stat_set_, "total_number_retired", "The total number of instructions retired by this core", sparta::Counter::COUNT_NORMAL), - num_flushes_(&unit_stat_set_, - "total_number_of_flushes", + num_uops_retired_(&unit_stat_set_, "total_uops_retired", + "The total number of uops retired by this core", + sparta::Counter::COUNT_NORMAL), + num_flushes_(&unit_stat_set_, "total_number_of_flushes", "The total number of flushes performed by the ROB", sparta::Counter::COUNT_NORMAL), overall_ipc_si_(&stat_ipc_), @@ -33,8 +30,7 @@ namespace olympia num_to_retire_(p->num_to_retire), num_insts_to_retire_(p->num_insts_to_retire), retire_heartbeat_(p->retire_heartbeat), - reorder_buffer_("ReorderBuffer", p->retire_queue_depth, - node->getClock(), &unit_stat_set_) + reorder_buffer_("ReorderBuffer", p->retire_queue_depth, node->getClock(), &unit_stat_set_) { // Set a cycle delay on the retire, just for kicks ev_retire_.setDelay(1); @@ -42,30 +38,27 @@ namespace olympia // Set up the reorder buffer to support pipeline collection. reorder_buffer_.enableCollection(node); - in_reorder_buffer_write_. - registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(ROB, robAppended_, InstGroup)); + in_reorder_buffer_write_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(ROB, robAppended_, InstGroup)); - in_reorder_flush_. - registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(ROB, handleFlush_, - FlushManager::FlushingCriteria)); + in_reorder_flush_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(ROB, handleFlush_, FlushManager::FlushingCriteria)); // Do not allow this event to keep simulation alive ev_ensure_forward_progress_.setContinuing(false); // Notify other components when ROB stops the simulation rob_stopped_notif_source_.reset(new sparta::NotificationSource( - this->getContainer(), - "rob_stopped_notif_channel", - "ROB terminated simulation channel", - "rob_stopped_notif_channel" - )); + this->getContainer(), "rob_stopped_notif_channel", "ROB terminated simulation channel", + "rob_stopped_notif_channel")); // Send initial credits to anyone that cares. Probably Dispatch. sparta::StartupEvent(node, CREATE_SPARTA_HANDLER(ROB, sendInitialCredits_)); } /// Destroy! - ROB::~ROB() { + ROB::~ROB() + { // Logging can be done from destructors in the correct simulator setup ILOG("ROB is destructing now, but you can still see this message"); } @@ -79,8 +72,10 @@ namespace olympia // An illustration of the use of the callback -- instead of // getting a reference, you can pull the data from the port // directly, albeit inefficient and superfluous here... - void ROB::robAppended_(const InstGroup &) { - for(auto & i : *in_reorder_buffer_write_.pullData()) { + void ROB::robAppended_(const InstGroup &) + { + for (auto & i : *in_reorder_buffer_write_.pullData()) + { reorder_buffer_.push(i); ILOG("retire appended: " << i); } @@ -118,7 +113,8 @@ namespace olympia void ROB::retireInstructions_() { // ROB is expecting a flush (back to itself) - if(expect_flush_) { + if (expect_flush_) + { return; } @@ -127,49 +123,64 @@ namespace olympia ILOG("num to retire: " << num_to_retire); uint32_t retired_this_cycle = 0; - for(uint32_t i = 0; i < num_to_retire; ++i) + for (uint32_t i = 0; i < num_to_retire; ++i) { auto ex_inst_ptr = reorder_buffer_.access(0); sparta_assert(nullptr != ex_inst_ptr); auto & ex_inst = *ex_inst_ptr; sparta_assert(ex_inst.isSpeculative() == false, "Uh, oh! A speculative instruction is being retired: " << ex_inst); - if(ex_inst.getStatus() == Inst::Status::COMPLETED) + + if (ex_inst.getStatus() == Inst::Status::COMPLETED) { // UPDATE: ex_inst.setStatus(Inst::Status::RETIRED); - if (ex_inst.isStoreInst()) { + if (ex_inst.isStoreInst()) + { out_rob_retire_ack_.send(ex_inst_ptr); } // sending retired instruction to rename out_rob_retire_ack_rename_.send(ex_inst_ptr); - ++num_retired_; - ++retired_this_cycle; - reorder_buffer_.pop(); + // All instructions count as 1 uop + ++num_uops_retired_; + if (ex_inst_ptr->getUOpID() == 0) + { + ++num_retired_; + ++retired_this_cycle; + + // Use the program ID to verify that the program order has been maintained. + sparta_assert(ex_inst.getProgramID() == expected_program_id_, + "\nUnexpected program ID when retiring instruction" << + "\n(suggests wrong program order)" << + "\n expected: " << expected_program_id_ << + "\n received: " << ex_inst.getProgramID() << + "\n UID: " << ex_inst_ptr->getMavisUid() << + "\n incr: " << ex_inst_ptr->getProgramIDIncrement() << + "\n inst " << ex_inst); + + // The fused op records the number of insts that + // were eliminated and adjusts the progID as needed + expected_program_id_ += ex_inst.getProgramIDIncrement(); + } + reorder_buffer_.pop(); ILOG("retiring " << ex_inst); retire_event_.collect(*ex_inst_ptr); + last_inst_retired_ = ex_inst_ptr; - // Use the program ID to verify that the program order has been maintained. - sparta_assert(ex_inst.getProgramID() == expected_program_id_, - "Unexpected program ID when retiring instruction" - << "(suggests wrong program order)" - << " expected: " << expected_program_id_ - << " received: " << ex_inst.getProgramID()); - ++expected_program_id_; - - if(SPARTA_EXPECT_FALSE((num_retired_ % retire_heartbeat_) == 0)) { - std::cout << "olympia: Retired " << num_retired_.get() - << " instructions in " << getClock()->currentCycle() + if (SPARTA_EXPECT_FALSE((num_retired_ % retire_heartbeat_) == 0)) + { + std::cout << "olympia: Retired " << num_retired_.get() << " instructions in " + << getClock()->currentCycle() << " cycles. Period IPC: " << period_ipc_si_.getValue() - << " overall IPC: " << overall_ipc_si_.getValue() - << std::endl; + << " overall IPC: " << overall_ipc_si_.getValue() << std::endl; period_ipc_si_.start(); } // Will be true if the user provides a -i option - if (SPARTA_EXPECT_FALSE((num_retired_ == num_insts_to_retire_))) { + if (SPARTA_EXPECT_FALSE((num_retired_ == num_insts_to_retire_))) + { rob_stopped_simulation_ = true; rob_stopped_notif_source_->postNotification(true); getScheduler()->stopRunning(); @@ -177,53 +188,54 @@ namespace olympia } // Is this a misprdicted branch requiring a refetch? - if(ex_inst.isMispredicted()) { - FlushManager::FlushingCriteria criteria - (FlushManager::FlushCause::MISPREDICTION, ex_inst_ptr); + if (ex_inst.isMispredicted()) + { + FlushManager::FlushingCriteria criteria(FlushManager::FlushCause::MISPREDICTION, + ex_inst_ptr); out_retire_flush_.send(criteria); expect_flush_ = true; break; } // This is rare for the example - if(SPARTA_EXPECT_FALSE(ex_inst.getPipe() == InstArchInfo::TargetPipe::SYS)) + if (SPARTA_EXPECT_FALSE(ex_inst.getPipe() == InstArchInfo::TargetPipe::SYS)) { - ILOG("Instigating flush... " << ex_inst); - - FlushManager::FlushingCriteria criteria(FlushManager::FlushCause::POST_SYNC, ex_inst_ptr); - out_retire_flush_.send(criteria); - - ++num_flushes_; - break; + retireSysInst_(ex_inst_ptr); } } - else { + else + { break; } } - if(false == reorder_buffer_.empty()) { + if (false == reorder_buffer_.empty()) + { const auto & oldest_inst = reorder_buffer_.front(); - if(oldest_inst->getStatus() == Inst::Status::COMPLETED) { + if (oldest_inst->getStatus() == Inst::Status::COMPLETED) + { ILOG("oldest is marked completed: " << oldest_inst); ev_retire_.schedule(); } - else if(false == oldest_inst->isMarkedOldest()) { + else if (false == oldest_inst->isMarkedOldest()) + { ILOG("set oldest: " << oldest_inst); oldest_inst->setOldest(true, &ev_retire_); } } - if(retired_this_cycle != 0) { + if (retired_this_cycle != 0) + { out_reorder_buffer_credits_.send(retired_this_cycle); last_retirement_ = getClock()->currentCycle(); } } - void ROB::dumpDebugContent_(std::ostream& output) const + void ROB::dumpDebugContent_(std::ostream & output) const { output << "ROB Contents" << std::endl; - for(const auto & entry : reorder_buffer_) { + for (const auto & entry : reorder_buffer_) + { output << '\t' << entry << std::endl; } } @@ -231,21 +243,47 @@ namespace olympia // Make sure the pipeline is making forward progress void ROB::checkForwardProgress_() { - if(getClock()->currentCycle() - last_retirement_ >= retire_timeout_interval_) + if (getClock()->currentCycle() - last_retirement_ >= retire_timeout_interval_) { sparta::SpartaException e; - e << "Been a while since we've retired an instruction. Is the pipe stalled indefinitely?"; - e << " currentCycle: " << getClock()->currentCycle(); + e << "Been a while since we've retired an instruction. Is the pipe stalled " + "indefinitely?"; + e << " currentCycle: " << getClock()->currentCycle(); throw e; } ev_ensure_forward_progress_.schedule(retire_timeout_interval_); } - void ROB::onStartingTeardown_() { - if ((reorder_buffer_.size() > 0) && (false == rob_stopped_simulation_)) { - std::cerr << "WARNING! Simulation is ending, but the ROB didn't stop it. Lock up situation?" << std::endl; + void ROB::onStartingTeardown_() + { + if ((reorder_buffer_.size() > 0) && (false == rob_stopped_simulation_)) + { + std::cerr + << "WARNING! Simulation is ending, but the ROB didn't stop it. Lock up situation?" + << std::endl; dumpDebugContent_(std::cerr); } } + // sys gets flushed unless it is csr rd + void ROB::retireSysInst_(InstPtr &ex_inst) + { + auto srclist = ex_inst->getRenameData().getSourceList(); + // if SYS instr is not a csr instruction flush + // if SYS instr is a csr but src1 is not x0, flush + // otherwise it is a csr read, therefore don't flush + if (ex_inst->isCSR()) + { // this is the case if csr instr with src != x0 + DLOG("retiring SYS wr instr with src reg " << ex_inst->getMnemonic() ); + + FlushManager::FlushingCriteria criteria(FlushManager::FlushCause::POST_SYNC, ex_inst); + out_retire_flush_.send(criteria); + expect_flush_ = true; + ++num_flushes_; + ILOG("Instigating flush due to SYS instruction... " << *ex_inst); + + } + + } + } diff --git a/core/ROB.hpp b/core/ROB.hpp index a024410f..23ab29ec 100644 --- a/core/ROB.hpp +++ b/core/ROB.hpp @@ -72,11 +72,12 @@ namespace olympia private: // Stats and counters - sparta::StatisticDef stat_ipc_; // A simple expression to calculate IPC - sparta::Counter num_retired_; // Running counter of number instructions retired - sparta::Counter num_flushes_; // Number of flushes - sparta::StatisticInstance overall_ipc_si_; // An overall IPC statistic instance starting at time == 0 - sparta::StatisticInstance period_ipc_si_; // An IPC counter for the period between retirement heartbeats + sparta::StatisticDef stat_ipc_; // A simple expression to calculate IPC + sparta::Counter num_retired_; // Running counter of number of instructions retired + sparta::Counter num_uops_retired_; // Running counter of the number of uops retired + sparta::Counter num_flushes_; // Number of flushes + sparta::StatisticInstance overall_ipc_si_; // An overall IPC statistic instance starting at time == 0 + sparta::StatisticInstance period_ipc_si_; // An IPC counter for the period between retirement heartbeats // Parameter constants const sparta::Clock::Cycle retire_timeout_interval_; @@ -118,6 +119,9 @@ namespace olympia // For correlation activities sparta::pevents::PeventCollector retire_event_{"RETIRE", getContainer(), getClock()}; + // Last inst retired for testing + InstPtr last_inst_retired_ = nullptr; + // A nice checker to make sure forward progress is being made // Note that in the ROB constructor, this event is set as non-continuing sparta::Clock::Cycle last_retirement_ = 0; // Last retirement cycle for checking stalled retire @@ -134,5 +138,11 @@ namespace olympia void dumpDebugContent_(std::ostream& output) const override final; void onStartingTeardown_() override final; + void retireSysInst_(InstPtr & ); + + // Friend class used in retire testing + friend class ROBTester; }; + + class ROBTester; } diff --git a/core/Rename.cpp b/core/Rename.cpp index 4dcc2c8d..5080b60e 100644 --- a/core/Rename.cpp +++ b/core/Rename.cpp @@ -16,76 +16,84 @@ namespace olympia { const char Rename::name[] = "rename"; - Rename::Rename(sparta::TreeNode * node, - const RenameParameterSet * p) : + Rename::Rename(sparta::TreeNode* node, const RenameParameterSet* p) : sparta::Unit(node), - uop_queue_("rename_uop_queue", p->rename_queue_depth, - node->getClock(), getStatisticSet()), + uop_queue_("rename_uop_queue", p->rename_queue_depth, node->getClock(), getStatisticSet()), num_to_rename_per_cycle_(p->num_to_rename), rename_histogram_(*getStatisticSet(), "rename_histogram", "Rename Stage Histogram", - [&p]() { std::vector v(p->num_to_rename+1); std::iota(v.begin(), v.end(), 0); return v; }()) + [&p]() + { + std::vector v(p->num_to_rename + 1); + std::iota(v.begin(), v.end(), 0); + return v; + }()) { uop_queue_.enableCollection(node); // The path into the Rename block // - Instructions are received on the Uop Queue Append port // - Credits arrive on the dispatch queue credits port - in_uop_queue_append_. - registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(Rename, decodedInstructions_, InstGroupPtr)); - in_dispatch_queue_credits_. - registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(Rename, creditsDispatchQueue_, uint32_t)); - in_reorder_flush_. - registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(Rename, handleFlush_, FlushManager::FlushingCriteria)); - in_rename_retire_ack_.registerConsumerHandler - (CREATE_SPARTA_HANDLER_WITH_DATA(Rename, getAckFromROB_, InstPtr)); + in_uop_queue_append_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(Rename, decodedInstructions_, InstGroupPtr)); + in_dispatch_queue_credits_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(Rename, creditsDispatchQueue_, uint32_t)); + in_reorder_flush_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(Rename, handleFlush_, FlushManager::FlushingCriteria)); + in_rename_retire_ack_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(Rename, getAckFromROB_, InstPtr)); sparta::StartupEvent(node, CREATE_SPARTA_HANDLER(Rename, setupRename_)); - auto setup_map = [this] (core_types::RegFile reg_file, const uint32_t num_renames) { - const uint32_t num_regs = 32; // default risc-v ARF count - sparta_assert(num_regs < num_renames); // ensure we have more renames than 32 because first 32 renames are allocated at the beginning - // initialize the first 32 Float (31 for INT) regs, i.e x1 -> PRF1 - - // for x0 for RF_INTEGER, we don't want to set a PRF for it because x0 is hardwired to 0 - uint32_t i = 0; - if (reg_file == core_types::RegFile::RF_INTEGER){ - reference_counter_[reg_file].push_back(0); - freelist_[reg_file].push(0); - i = 1; - } - for(; i < num_regs; i++){ - map_table_[reg_file][i] = i; - // for the first 32 Float (31 INT) registers, we mark their reference_counters 1, as they are the - // current "valid" PRF for that ARF - reference_counter_[reg_file].push_back(1); - } - for(uint32_t j = num_regs; j < num_renames; ++j) { - freelist_[reg_file].push(j); - reference_counter_[reg_file].push_back(0); - } - }; + auto setup_map = [this](core_types::RegFile reg_file, const uint32_t num_renames) + { + const uint32_t num_regs = 32; // default risc-v ARF count + sparta_assert(num_regs + < num_renames); // ensure we have more renames than 32 because first 32 + // renames are allocated at the beginning + // initialize the first 32 Float (31 for INT) regs, i.e x1 -> PRF1 + + // for x0 for RF_INTEGER, we don't want to set a PRF for it because x0 is hardwired to 0 + uint32_t i = 0; + if (reg_file == core_types::RegFile::RF_INTEGER) + { + reference_counter_[reg_file].push_back(0); + freelist_[reg_file].push(0); + i = 1; + } + for (; i < num_regs; i++) + { + map_table_[reg_file][i] = i; + // for the first 32 Float (31 INT) registers, we mark their reference_counters 1, as + // they are the current "valid" PRF for that ARF + reference_counter_[reg_file].push_back(1); + } + for (uint32_t j = num_regs; j < num_renames; ++j) + { + freelist_[reg_file].push(j); + reference_counter_[reg_file].push_back(0); + } + }; setup_map(core_types::RegFile::RF_INTEGER, p->num_integer_renames); - setup_map(core_types::RegFile::RF_FLOAT, p->num_float_renames); + setup_map(core_types::RegFile::RF_FLOAT, p->num_float_renames); + setup_map(core_types::RegFile::RF_VECTOR, p->num_vector_renames); - static_assert(core_types::RegFile::N_REGFILES == 2, "New RF type added, but Rename not updated"); + static_assert(core_types::RegFile::N_REGFILES == 3, + "New RF type added, but Rename not updated"); } // Using the Rename factory, create the Scoreboards void RenameFactory::onConfiguring(sparta::ResourceTreeNode* node) { - sparta::TreeNode * sb_tn = nullptr; - sb_tns_.emplace_back(sb_tn = - new sparta::TreeNode(node, "scoreboards", "Scoreboards used by Rename")); + sparta::TreeNode* sb_tn = nullptr; + sb_tns_.emplace_back( + sb_tn = new sparta::TreeNode(node, "scoreboards", "Scoreboards used by Rename")); // Set up the Scoreboard resources - for(uint32_t rf = 0; rf < core_types::RegFile::N_REGFILES; ++rf) + for (uint32_t rf = 0; rf < core_types::RegFile::N_REGFILES; ++rf) { const auto rf_name = core_types::regfile_names[rf]; - sb_tns_.emplace_back(new sparta::ResourceTreeNode(sb_tn, - rf_name, - sparta::TreeNode::GROUP_NAME_NONE, - sparta::TreeNode::GROUP_IDX_NONE, - rf_name + std::string(" Scoreboard"), - &sb_facts_[rf])); + sb_tns_.emplace_back(new sparta::ResourceTreeNode( + sb_tn, rf_name, sparta::TreeNode::GROUP_NAME_NONE, sparta::TreeNode::GROUP_IDX_NONE, + rf_name + std::string(" Scoreboard"), &sb_facts_[rf])); } } @@ -94,7 +102,8 @@ namespace olympia // Set up scoreboards auto sbs_tn = getContainer()->getChild("scoreboards"); sparta_assert(sbs_tn != nullptr, "Expected to find 'scoreboards' node in Rename, got none"); - for(uint32_t rf = 0; rf < core_types::RegFile::N_REGFILES; ++rf) { + for (uint32_t rf = 0; rf < core_types::RegFile::N_REGFILES; ++rf) + { // Get scoreboard resources auto sb_tn = sbs_tn->getChild(core_types::regfile_names[rf]); scoreboards_[rf] = sb_tn->getResourceAs(); @@ -102,12 +111,14 @@ namespace olympia // Initialize 32 scoreboard resources, // all ready. uint32_t reg = 0; - if(rf == core_types::RegFile::RF_INTEGER){ + if (rf == core_types::RegFile::RF_INTEGER) + { reg = 1; } constexpr uint32_t num_regs = 32; core_types::RegisterBitMask bits; - for(; reg < num_regs; ++reg) { + for (; reg < num_regs; ++reg) + { bits.set(reg); } scoreboards_[rf]->set(bits); @@ -122,29 +133,33 @@ namespace olympia sparta_assert(in_dispatch_queue_credits_.dataReceived()); credits_dispatch_ += credits; - if (uop_queue_.size() > 0) { + if (uop_queue_.size() > 0) + { ev_schedule_rename_.schedule(); } } + void Rename::getAckFromROB_(const InstPtr & inst_ptr) { sparta_assert(inst_ptr->getStatus() == Inst::Status::RETIRED, - "Get ROB Ack, but the inst hasn't retired yet!"); + "Get ROB Ack, but the inst hasn't retired yet!"); auto const & dests = inst_ptr->getDestOpInfoList(); - if(dests.size() > 0) + if (dests.size() > 0) { sparta_assert(dests.size() == 1); // we should only have one destination const auto dest = dests[0]; - const auto rf = olympia::coreutils::determineRegisterFile(dest); + const auto rf = olympia::coreutils::determineRegisterFile(dest); const auto num = dest.field_value; const bool is_x0 = (num == 0 && rf == core_types::RF_INTEGER); if (!is_x0) { auto const & original_dest = inst_ptr->getRenameData().getOriginalDestination(); --reference_counter_[original_dest.rf][original_dest.val]; - // free previous PRF mapping if no references from srcs, there should be a new dest mapping for the ARF -> PRF - // so we know it's free to be pushed to freelist if it has no other src references - if(reference_counter_[original_dest.rf][original_dest.val] <= 0){ + // free previous PRF mapping if no references from srcs, there should be a new dest + // mapping for the ARF -> PRF so we know it's free to be pushed to freelist if it + // has no other src references + if (reference_counter_[original_dest.rf][original_dest.val] <= 0) + { freelist_[original_dest.rf].push(original_dest.val); } } @@ -152,24 +167,31 @@ namespace olympia const auto & srcs = inst_ptr->getRenameData().getSourceList(); // decrement reference to data register - if(inst_ptr->isLoadStoreInst()){ + if (inst_ptr->isLoadStoreInst()) + { const auto & data_reg = inst_ptr->getRenameData().getDataReg(); - if(data_reg.field_id == mavis::InstMetaData::OperandFieldID::RS2 && data_reg.is_x0 != true){ + if (data_reg.field_id == mavis::InstMetaData::OperandFieldID::RS2 + && data_reg.is_x0 != true) + { --reference_counter_[data_reg.rf][data_reg.val]; - if(reference_counter_[data_reg.rf][data_reg.val] <= 0){ - // freeing data register value, because it's not in the source list, so won't get caught below + if (reference_counter_[data_reg.rf][data_reg.val] <= 0) + { + // freeing data register value, because it's not in the source list, so won't + // get caught below freelist_[data_reg.rf].push(data_reg.val); } } } // freeing references to PRF - for(const auto & src: srcs){ + for (const auto & src : srcs) + { --reference_counter_[src.rf][src.val]; - if(reference_counter_[src.rf][src.val] <= 0){ - // freeing a register in the case where it still has references and has already been retired - // we wait until the last reference is retired to then free the prf - // any "valid" PRF that is the true mapping of an ARF will have a reference_counter of at least 1, - // and thus shouldn't be retired + if (reference_counter_[src.rf][src.val] <= 0) + { + // freeing a register in the case where it still has references and has already been + // retired we wait until the last reference is retired to then free the prf any + // "valid" PRF that is the true mapping of an ARF will have a reference_counter of + // at least 1, and thus shouldn't be retired freelist_[src.rf].push(src.val); } } @@ -177,20 +199,25 @@ namespace olympia if (SPARTA_EXPECT_TRUE(!inst_queue_.empty())) { const auto & oldest_inst = inst_queue_.front(); - sparta_assert(oldest_inst->getUniqueID() == inst_ptr->getUniqueID(), "ROB and rename inst_queue out of sync"); + if (oldest_inst->getUOpID() == 0) + { + sparta_assert(oldest_inst->getUniqueID() == inst_ptr->getUniqueID(), + "ROB and rename inst_queue out of sync"); + } + inst_queue_.pop_front(); } else { sparta_assert(false, "ROB and rename inst_queue out of sync"); } - if(credits_dispatch_ > 0 && (uop_queue_.size() > 0)){ + if (credits_dispatch_ > 0 && (uop_queue_.size() > 0)) + { ev_schedule_rename_.schedule(); } ILOG("Retired instruction: " << inst_ptr); } - // Handle incoming flush void Rename::handleFlush_(const FlushManager::FlushingCriteria & criteria) { @@ -209,18 +236,20 @@ namespace olympia for (const auto & dest : dests) { // restore rename table following a flush - const auto rf = olympia::coreutils::determineRegisterFile(dest); + const auto rf = olympia::coreutils::determineRegisterFile(dest); const auto num = dest.field_value; const bool is_x0 = (num == 0 && rf == core_types::RF_INTEGER); if (!is_x0) { - auto const & original_dest = inst_ptr->getRenameData().getOriginalDestination(); + auto const & original_dest = + inst_ptr->getRenameData().getOriginalDestination(); map_table_[rf][num] = original_dest.val; // free renamed PRF mapping when reference counter reaches zero auto const & renamed_dest = inst_ptr->getRenameData().getDestination(); --reference_counter_[renamed_dest.rf][renamed_dest.val]; - if(reference_counter_[renamed_dest.rf][renamed_dest.val] <= 0){ + if (reference_counter_[renamed_dest.rf][renamed_dest.val] <= 0) + { freelist_[renamed_dest.rf].push(renamed_dest.val); } } @@ -228,24 +257,31 @@ namespace olympia const auto & srcs = inst_ptr->getRenameData().getSourceList(); // decrement reference to data register - if(inst_ptr->isLoadStoreInst()){ + if (inst_ptr->isLoadStoreInst()) + { const auto & data_reg = inst_ptr->getRenameData().getDataReg(); - if(data_reg.field_id == mavis::InstMetaData::OperandFieldID::RS2 && data_reg.is_x0 != true){ + if (data_reg.field_id == mavis::InstMetaData::OperandFieldID::RS2 + && data_reg.is_x0 != true) + { --reference_counter_[data_reg.rf][data_reg.val]; - if(reference_counter_[data_reg.rf][data_reg.val] <= 0){ - // freeing data register value, because it's not in the source list, so won't get caught below + if (reference_counter_[data_reg.rf][data_reg.val] <= 0) + { + // freeing data register value, because it's not in the source list, so + // won't get caught below freelist_[data_reg.rf].push(data_reg.val); } } } // freeing references to PRF - for(const auto & src: srcs){ + for (const auto & src : srcs) + { --reference_counter_[src.rf][src.val]; - if(reference_counter_[src.rf][src.val] <= 0){ - // freeing a register in the case where it still has references and has already been retired - // we wait until the last reference is retired to then free the prf - // any "valid" PRF that is the true mapping of an ARF will have a reference_counter of at least 1, - // and thus shouldn't be retired + if (reference_counter_[src.rf][src.val] <= 0) + { + // freeing a register in the case where it still has references and has + // already been retired we wait until the last reference is retired to then + // free the prf any "valid" PRF that is the true mapping of an ARF will have + // a reference_counter of at least 1, and thus shouldn't be retired freelist_[src.rf].push(src.val); } } @@ -266,20 +302,24 @@ namespace olympia sparta_assert(in_uop_queue_append_.dataReceived()); RegCountData current_counts; - if(!uop_queue_regcount_data_.empty()){ + if (!uop_queue_regcount_data_.empty()) + { // if we have entries, use the most recent entered instruction counts current_counts = uop_queue_regcount_data_.back(); } - for(auto & i : *insts) { + for (auto & i : *insts) + { // create an index count for each instruction entered const auto & dests = i->getDestOpInfoList(); - if(dests.size() > 0){ + if (dests.size() > 0) + { sparta_assert(dests.size() == 1); // we should only have one destination const auto rf = olympia::coreutils::determineRegisterFile(dests[0]); const auto num = dests[0].field_value; const bool is_x0 = (num == 0 && rf == core_types::RF_INTEGER); // if dest is x0, we don't need to count it towards cumulative register count - if(!is_x0){ + if (!is_x0) + { current_counts.cumulative_reg_counts[rf]++; } } @@ -287,10 +327,12 @@ namespace olympia uop_queue_regcount_data_.push_back(current_counts); } - if(credits_dispatch_ > 0) { + if (credits_dispatch_ > 0) + { ev_schedule_rename_.schedule(); } } + void Rename::scheduleRenaming_() { current_stall_ = StallReason::NOT_STALLED; @@ -298,25 +340,31 @@ namespace olympia // If we have credits from dispatch, schedule a rename session this cycle uint32_t num_rename = std::min(uop_queue_.size(), num_to_rename_per_cycle_); num_rename = std::min(credits_dispatch_, num_rename); - if(credits_dispatch_ > 0) + if (credits_dispatch_ > 0) { RegCountData count_subtract; bool enough_rename = false; - for(uint32_t i = num_rename; i > 0 ; --i) + for (uint32_t i = num_rename; i > 0; --i) { - if(enough_rename){ + if (enough_rename) + { // once we know the number we can rename // pop everything below it uop_queue_regcount_data_.pop_front(); } - else{ + else + { uint32_t enough_freelists = 0; - for(int j = 0; j < core_types::RegFile::N_REGFILES; ++j){ - if(uop_queue_regcount_data_[i-1].cumulative_reg_counts[j] <= freelist_[j].size()){ + for (int j = 0; j < core_types::RegFile::N_REGFILES; ++j) + { + if (uop_queue_regcount_data_[i - 1].cumulative_reg_counts[j] + <= freelist_[j].size()) + { enough_freelists++; } } - if(enough_freelists == core_types::RegFile::N_REGFILES){ + if (enough_freelists == core_types::RegFile::N_REGFILES) + { // we are good to process all instructions from this index num_to_rename_ = i; enough_rename = true; @@ -324,12 +372,13 @@ namespace olympia } } // decrement the rest of the entries in the uop_queue_reg_count_data_ accordingly - if(enough_rename) + if (enough_rename) { count_subtract = uop_queue_regcount_data_.front(); uop_queue_regcount_data_.pop_front(); - for(uint32_t i = 0; i < uop_queue_regcount_data_.size(); ++i){ - for(uint32_t j = 0; j < core_types::RegFile::N_REGFILES; ++j) + for (uint32_t i = 0; i < uop_queue_regcount_data_.size(); ++i) + { + for (uint32_t j = 0; j < core_types::RegFile::N_REGFILES; ++j) { uop_queue_regcount_data_[i].cumulative_reg_counts[j] -= count_subtract.cumulative_reg_counts[j]; @@ -337,27 +386,31 @@ namespace olympia } ev_rename_insts_.schedule(); } - else{ + else + { current_stall_ = StallReason::NO_RENAMES; num_to_rename_ = 0; } } - else{ + else + { current_stall_ = StallReason::NO_DISPATCH_CREDITS; num_to_rename_ = 0; } ILOG("current stall: " << current_stall_); - rename_histogram_.addValue((int) num_to_rename_); + rename_histogram_.addValue((int)num_to_rename_); } + void Rename::renameInstructions_() { - if(num_to_rename_ > 0) + if (num_to_rename_ > 0) { // Pick instructions from uop queue to rename - InstGroupPtr insts = sparta::allocate_sparta_shared_pointer(instgroup_allocator); + InstGroupPtr insts = + sparta::allocate_sparta_shared_pointer(instgroup_allocator); - for(uint32_t i = 0; i < num_to_rename_; ++i) + for (uint32_t i = 0; i < num_to_rename_; ++i) { // Pick the oldest const auto & renaming_inst = uop_queue_.read(0); @@ -366,51 +419,58 @@ namespace olympia const auto & srcs = renaming_inst->getSourceOpInfoList(); const auto & dests = renaming_inst->getDestOpInfoList(); - for(const auto & src : srcs) + for (const auto & src : srcs) { - const auto rf = olympia::coreutils::determineRegisterFile(src); + const auto rf = olympia::coreutils::determineRegisterFile(src); const auto num = src.field_value; // we check if src is RF_INTEGER x0, if so, we skip rename const bool is_x0 = (num == 0 && rf == core_types::RF_INTEGER); - if (is_x0) { - // if x0 is a data operand for LSU op, we need to set it in DataReg when we check in LSU - // so we can still check the scoreboard, which will always return back ready for x0 - if(src.field_id == mavis::InstMetaData::OperandFieldID::RS2){ - renaming_inst->getRenameData().setDataReg({num, rf, src.field_id, is_x0}); + if (is_x0) + { + // if x0 is a data operand for LSU op, we need to set it in DataReg when we + // check in LSU so we can still check the scoreboard, which will always + // return back ready for x0 + if (src.field_id == mavis::InstMetaData::OperandFieldID::RS2) + { + renaming_inst->getRenameData().setDataReg( + {num, rf, src.field_id, is_x0}); } continue; } // we check for load/store separately because address operand // is always integer - else if(renaming_inst->isLoadStoreInst()) { + else if (renaming_inst->isLoadStoreInst()) + { // check for data operand existing based on RS2 existence // store data register info separately - if(src.field_id == mavis::InstMetaData::OperandFieldID::RS2) { + if (src.field_id == mavis::InstMetaData::OperandFieldID::RS2) + { auto & bitmask = renaming_inst->getDataRegisterBitMask(rf); const uint32_t prf = map_table_[rf][num]; reference_counter_[rf][prf]++; - renaming_inst->getRenameData().setDataReg({prf, rf, src.field_id, is_x0}); + renaming_inst->getRenameData().setDataReg( + {prf, rf, src.field_id, is_x0}); bitmask.set(prf); - ILOG("\tsetup store data register bit mask " - << sparta::printBitSet(bitmask) - << " for '" << rf << "' scoreboard"); + ILOG("\tsetup store data register bit mask " << sparta::printBitSet( + bitmask) << " for '" << rf << "' scoreboard"); } - else { + else + { // address is always INTEGER - const auto addr_rf = core_types::RF_INTEGER; + const auto addr_rf = core_types::RF_INTEGER; auto & bitmask = renaming_inst->getSrcRegisterBitMask(addr_rf); const uint32_t prf = map_table_[addr_rf][num]; reference_counter_[addr_rf][prf]++; renaming_inst->getRenameData().setSource({prf, addr_rf, src.field_id}); bitmask.set(prf); - ILOG("\tsetup source register bit mask " - << sparta::printBitSet(bitmask) - << " for '" << addr_rf << "' scoreboard"); + ILOG("\tsetup source register bit mask " << sparta::printBitSet( + bitmask) << " for '" << addr_rf << "' scoreboard"); } } - else { + else + { auto & bitmask = renaming_inst->getSrcRegisterBitMask(rf); const uint32_t prf = map_table_[rf][num]; reference_counter_[rf][prf]++; @@ -418,37 +478,38 @@ namespace olympia bitmask.set(prf); ILOG("\tsetup source register bit mask " - << sparta::printBitSet(bitmask) - << " for '" << rf << "' scoreboard"); + << sparta::printBitSet(bitmask) << " for '" << rf << "' scoreboard"); } } - for(const auto & dest : dests) + for (const auto & dest : dests) { - const auto rf = olympia::coreutils::determineRegisterFile(dest); + const auto rf = olympia::coreutils::determineRegisterFile(dest); const auto num = dest.field_value; - if (num == 0 && rf == core_types::RF_INTEGER) { + if (num == 0 && rf == core_types::RF_INTEGER) + { continue; } - else{ + else + { auto & bitmask = renaming_inst->getDestRegisterBitMask(rf); const uint32_t prf = freelist_[rf].front(); freelist_[rf].pop(); - renaming_inst->getRenameData().setOriginalDestination({map_table_[rf][num], rf, dest.field_id}); + renaming_inst->getRenameData().setOriginalDestination( + {map_table_[rf][num], rf, dest.field_id}); renaming_inst->getRenameData().setDestination({prf, rf, dest.field_id}); map_table_[rf][num] = prf; // we increase reference_counter_ for destinations to mark them as "valid", // so the PRF in the reference_counter_ should have a value of 1 - // once a PRF reference_counter goes to 0, we know that the PRF isn't the "valid" - // PRF for that ARF anymore and there are no sources referring to it + // once a PRF reference_counter goes to 0, we know that the PRF isn't the + // "valid" PRF for that ARF anymore and there are no sources referring to it // so we can push it to freelist reference_counter_[rf][prf]++; bitmask.set(prf); // clear scoreboard for the PRF we are allocating scoreboards_[rf]->clearBits(bitmask); ILOG("\tsetup destination register bit mask " - << sparta::printBitSet(bitmask) - << " for '" << rf << "' scoreboard"); + << sparta::printBitSet(bitmask) << " for '" << rf << "' scoreboard"); } } // Remove it from uop queue @@ -465,8 +526,9 @@ namespace olympia out_uop_queue_credits_.send(num_to_rename_); num_to_rename_ = 0; } - if (credits_dispatch_ > 0 && (uop_queue_.size() > 0)) { + if (credits_dispatch_ > 0 && (uop_queue_.size() > 0)) + { ev_schedule_rename_.schedule(1); } } -} \ No newline at end of file +} // namespace olympia diff --git a/core/Rename.hpp b/core/Rename.hpp index 5f31eed3..c5e7165d 100644 --- a/core/Rename.hpp +++ b/core/Rename.hpp @@ -1,6 +1,5 @@ // -*- C++ -*- - #pragma once #include @@ -16,7 +15,6 @@ #include "sparta/statistics/Histogram.hpp" #include "sparta/statistics/BasicHistogram.hpp" - #include "CoreTypes.hpp" #include "FlushManager.hpp" #include "InstGroup.hpp" @@ -35,19 +33,18 @@ namespace olympia */ class Rename : public sparta::Unit { - public: + public: //! \brief Parameters for Rename model class RenameParameterSet : public sparta::ParameterSet { - public: - RenameParameterSet(sparta::TreeNode* n) : - sparta::ParameterSet(n) - { } + public: + RenameParameterSet(sparta::TreeNode* n) : sparta::ParameterSet(n) {} - PARAMETER(uint32_t, num_to_rename, 4, "Number of instructions to rename") + PARAMETER(uint32_t, num_to_rename, 4, "Number of instructions to rename") PARAMETER(uint32_t, rename_queue_depth, 10, "Number of instructions queued for rename") PARAMETER(uint32_t, num_integer_renames, 128, "Number of integer renames") - PARAMETER(uint32_t, num_float_renames, 128, "Number of float renames") + PARAMETER(uint32_t, num_float_renames, 128, "Number of float renames") + PARAMETER(uint32_t, num_vector_renames, 48, "Number of vector renames") }; /** @@ -56,29 +53,32 @@ namespace olympia * @param node The node that represents (has a pointer to) the Rename * @param p The Rename's parameter set */ - Rename(sparta::TreeNode * node, - const RenameParameterSet * p); + Rename(sparta::TreeNode* node, const RenameParameterSet* p); //! \brief Name of this resource. Required by sparta::UnitFactory static const char name[]; - private: - InstQueue uop_queue_; - sparta::DataInPort in_uop_queue_append_ {&unit_port_set_, "in_uop_queue_append", 1}; - sparta::DataOutPort out_uop_queue_credits_ {&unit_port_set_, "out_uop_queue_credits"}; - sparta::DataOutPort out_dispatch_queue_write_ {&unit_port_set_, "out_dispatch_queue_write"}; - sparta::DataInPort in_dispatch_queue_credits_ {&unit_port_set_, "in_dispatch_queue_credits", - sparta::SchedulingPhase::Tick, 0}; - sparta::DataInPort in_rename_retire_ack_ {&unit_port_set_, "in_rename_retire_ack", 1}; + private: + InstQueue uop_queue_; + sparta::DataInPort in_uop_queue_append_{&unit_port_set_, + "in_uop_queue_append", 1}; + sparta::DataOutPort out_uop_queue_credits_{&unit_port_set_, + "out_uop_queue_credits"}; + sparta::DataOutPort out_dispatch_queue_write_{&unit_port_set_, + "out_dispatch_queue_write"}; + sparta::DataInPort in_dispatch_queue_credits_{ + &unit_port_set_, "in_dispatch_queue_credits", sparta::SchedulingPhase::Tick, 0}; + sparta::DataInPort in_rename_retire_ack_{&unit_port_set_, "in_rename_retire_ack", + 1}; // For flush - sparta::DataInPort in_reorder_flush_ - {&unit_port_set_, "in_reorder_flush", sparta::SchedulingPhase::Flush, 1}; + sparta::DataInPort in_reorder_flush_{ + &unit_port_set_, "in_reorder_flush", sparta::SchedulingPhase::Flush, 1}; - sparta::UniqueEvent<> ev_rename_insts_ {&unit_event_set_, "rename_insts", - CREATE_SPARTA_HANDLER(Rename, renameInstructions_)}; - sparta::UniqueEvent<> ev_schedule_rename_ {&unit_event_set_, "schedule_rename", - CREATE_SPARTA_HANDLER(Rename, scheduleRenaming_)}; + sparta::UniqueEvent<> ev_rename_insts_{&unit_event_set_, "rename_insts", + CREATE_SPARTA_HANDLER(Rename, renameInstructions_)}; + sparta::UniqueEvent<> ev_schedule_rename_{&unit_event_set_, "schedule_rename", + CREATE_SPARTA_HANDLER(Rename, scheduleRenaming_)}; const uint32_t num_to_rename_per_cycle_; uint32_t num_to_rename_ = 0; @@ -96,21 +96,24 @@ namespace olympia std::array, core_types::N_REGFILES> reference_counter_; // list of free PRF that are available to map std::queue freelist_[core_types::N_REGFILES]; + // used to track current number of each type of RF instruction at each // given index in the uop_queue_ - struct RegCountData{ + struct RegCountData + { uint32_t cumulative_reg_counts[core_types::RegFile::N_REGFILES] = {0}; }; + std::deque uop_queue_regcount_data_; // Used to track inflight instructions for the purpose of recovering // the rename data structures std::deque inst_queue_; - /////////////////////////////////////////////////////////////////////// // Stall counters - enum StallReason { + enum StallReason + { NO_DECODE_INSTS, // No insts from Decode NO_DISPATCH_CREDITS, // No credits from Dispatch NO_RENAMES, // Out of renames @@ -121,24 +124,20 @@ namespace olympia }; StallReason current_stall_ = NO_DECODE_INSTS; - friend std::ostream&operator<<(std::ostream &, const StallReason &); + friend std::ostream & operator<<(std::ostream &, const StallReason &); // Counters -- this is only supported in C++11 -- uses // Counter's move semantics - std::array stall_counters_{{ - sparta::CycleCounter(getStatisticSet(), "stall_no_decode_insts", - "No Decode Insts", - sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_no_dispatch_credits", - "No Dispatch Credits", - sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_no_renames", - "No Renames", - sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_not_stalled", - "Rename not stalled, all instructions renamed", - sparta::Counter::COUNT_NORMAL, getClock()) - }}; + std::array stall_counters_{ + {sparta::CycleCounter(getStatisticSet(), "stall_no_decode_insts", "No Decode Insts", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_no_dispatch_credits", + "No Dispatch Credits", sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_no_renames", "No Renames", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_not_stalled", + "Rename not stalled, all instructions renamed", + sparta::Counter::COUNT_NORMAL, getClock())}}; //! Rename setup void setupRename_(); @@ -163,27 +162,26 @@ namespace olympia // Friend class used in rename testing friend class RenameTester; - }; - inline std::ostream&operator<<(std::ostream &os, const Rename::StallReason & stall) + inline std::ostream & operator<<(std::ostream & os, const Rename::StallReason & stall) { - switch(stall) + switch (stall) { - case Rename::StallReason::NO_DECODE_INSTS: - os << "NO_DECODE_INSTS"; - break; - case Rename::StallReason::NO_DISPATCH_CREDITS: - os << "NO_DISPATCH_CREDITS"; - break; - case Rename::StallReason::NO_RENAMES: - os << "NO_RENAMES"; - break; - case Rename::StallReason::NOT_STALLED: - os << "NOT_STALLED"; - break; - case Rename::StallReason::N_STALL_REASONS: - sparta_assert(false, "How'd we get here?"); + case Rename::StallReason::NO_DECODE_INSTS: + os << "NO_DECODE_INSTS"; + break; + case Rename::StallReason::NO_DISPATCH_CREDITS: + os << "NO_DISPATCH_CREDITS"; + break; + case Rename::StallReason::NO_RENAMES: + os << "NO_RENAMES"; + break; + case Rename::StallReason::NOT_STALLED: + os << "NOT_STALLED"; + break; + case Rename::StallReason::N_STALL_REASONS: + sparta_assert(false, "How'd we get here?"); } return os; } @@ -191,16 +189,16 @@ namespace olympia //! Rename's factory class. Don't create Rename without it class RenameFactory : public sparta::ResourceFactory { - public: + public: void onConfiguring(sparta::ResourceTreeNode* node) override; - private: + private: using ScoreboardTreeNodes = std::vector>; - using ScoreboardFactories = std::array , - core_types::RegFile::N_REGFILES>; + using ScoreboardFactories = std::array< + sparta::ResourceFactory, + core_types::RegFile::N_REGFILES>; ScoreboardFactories sb_facts_; ScoreboardTreeNodes sb_tns_; }; class RenameTester; -} +} // namespace olympia diff --git a/core/SimpleBranchPred.cpp b/core/SimpleBranchPred.cpp new file mode 100644 index 00000000..9c679ea5 --- /dev/null +++ b/core/SimpleBranchPred.cpp @@ -0,0 +1,79 @@ +#include "SimpleBranchPred.hpp" + +/* + * The algorithm used for prediction / update is as follows: + * Prediction: + * - look up BHT to determine if the branch is predicted taken or not + * using 2-bit saturated counter + * - value 3: strongly taken + * - value 2: weakly taken + * - value 1: weakly not taken + * - value 0: strongly not taken + * - look up BTB to see if an entry exists for the input fetch pc + * - if present in BTB and predicted taken, BTB entry is used to determine + * prediction branch idx and predicted_PC + * - if present in BTB but predicted not taken, BTB entry is used to determine + * prediction branch idx, while predicted_PC is the fall through addr + * - if not present in BTB entry, prediction branch idx is the last instr of + * the FetchPacket, while predicted PC is the fall through addr. Also, create + * a new BTB entry + * Update: + * - a valid BTB entry must be present for fetch PC + * - TBD + * + */ +namespace olympia +{ +namespace BranchPredictor +{ + + void SimpleBranchPredictor::updatePredictor(const DefaultUpdate & update) { + + sparta_assert(branch_target_buffer_.find(update.fetch_PC) != branch_target_buffer_.end()); + branch_target_buffer_[update.fetch_PC].branch_idx = update.branch_idx; + if (update.actually_taken) { + branch_history_table_[update.fetch_PC] = + (branch_history_table_[update.fetch_PC] == 3) ? 3 : + branch_history_table_[update.fetch_PC] + 1; + branch_target_buffer_[update.fetch_PC].predicted_PC = update.corrected_PC; + } else { + branch_history_table_[update.fetch_PC] = + (branch_history_table_[update.fetch_PC] == 0) ? 0 : + branch_history_table_[update.fetch_PC] - 1; + } + } + + DefaultPrediction SimpleBranchPredictor::getPrediction(const DefaultInput & input) { + bool predictTaken = false; + if (branch_history_table_.find(input.fetch_PC) != branch_history_table_.end()) { + predictTaken = (branch_history_table_[input.fetch_PC] > 1); + } else { + // add a new entry to BHT, biased towards not taken + branch_history_table_.insert(std::pair(input.fetch_PC, 1)); + } + + DefaultPrediction prediction; + if (branch_target_buffer_.find(input.fetch_PC) != branch_target_buffer_.end()) { + // BTB hit + const BTBEntry & btb_entry = branch_target_buffer_[input.fetch_PC]; + prediction.branch_idx = btb_entry.branch_idx; + if (predictTaken) { + prediction.predicted_PC = btb_entry.predicted_PC; + } else { + // fall through address + prediction.predicted_PC = input.fetch_PC + prediction.branch_idx + BranchPredictorIF::bytes_per_inst; + } + } else { + // BTB miss + prediction.branch_idx = max_fetch_insts_; + prediction.predicted_PC = input.fetch_PC + max_fetch_insts_ * bytes_per_inst; + // add new entry to BTB + branch_target_buffer_.insert(std::pair( + input.fetch_PC, BTBEntry(prediction.branch_idx, prediction.predicted_PC))); + } + + return prediction; + } + +} // namespace BranchPredictor +} // namespace olympia diff --git a/core/SimpleBranchPred.hpp b/core/SimpleBranchPred.hpp new file mode 100644 index 00000000..53f9bccc --- /dev/null +++ b/core/SimpleBranchPred.hpp @@ -0,0 +1,89 @@ +// -*- C++ -*- + +//! +//! \file SimpleBranchPred.hpp +//! \brief Class definition of a simple brranch prediction using branch prediction interface +//! + +/* + * This file defines the class SimpleBranchPredictor, as well as, a default Prediction + * output class, a default Prediction input class, a defeault Prediction input class + * as required by Olympia's Branch Prediction inteface + * */ +#pragma once + +#include +#include +#include +#include "sparta/utils/SpartaAssert.hpp" +#include "BranchPredIF.hpp" + +namespace olympia +{ +namespace BranchPredictor +{ + + // following class definitions are example inputs & outputs for a very simple branch + // predictor + class DefaultPrediction + { + public: + // index of branch instruction in the fetch packet + // branch_idx can vary from 0 to (FETCH_WIDTH - 1) + // initialized to default max to catch errors + uint32_t branch_idx = std::numeric_limits::max(); + // predicted target PC + uint64_t predicted_PC = std::numeric_limits::max(); + }; + + class DefaultUpdate + { + public: + uint64_t fetch_PC = std::numeric_limits::max(); + uint32_t branch_idx = std::numeric_limits::max(); + uint64_t corrected_PC = std::numeric_limits::max(); + bool actually_taken = false; + }; + + class DefaultInput + { + public: + // PC of first instruction of fetch packet + uint64_t fetch_PC = std::numeric_limits::max(); + }; + + class BTBEntry + { + public: + // use of BTBEntry in std:map operator [] requires default constructor + BTBEntry() = default; + BTBEntry(uint32_t bidx, uint64_t predPC) : + branch_idx(bidx), + predicted_PC(predPC) + {} + uint32_t branch_idx {std::numeric_limits::max()}; + uint64_t predicted_PC {std::numeric_limits::max()}; + }; + + // Currently SimpleBranchPredictor works only with uncompressed instructions + // TODO: generalize SimpleBranchPredictor for both compressed and uncompressed instructions + class SimpleBranchPredictor : public BranchPredictorIF + { + public: + SimpleBranchPredictor(uint32_t max_fetch_insts) : + max_fetch_insts_(max_fetch_insts) + {} + DefaultPrediction getPrediction(const DefaultInput &); + void updatePredictor(const DefaultUpdate &); + private: + // maximum number of instructions in a FetchPacket + const uint32_t max_fetch_insts_; + // BHT and BTB of SimpleBranchPredictor is unlimited in size + // a map of branch PC to 2 bit staurating counter tracking branch history + std::map branch_history_table_; // BHT + // a map of branch PC to target of the branch + std::map branch_target_buffer_; // BTB + }; + +} // namespace BranchPredictor +} // namespace olympia diff --git a/core/VectorConfig.hpp b/core/VectorConfig.hpp new file mode 100644 index 00000000..287707fb --- /dev/null +++ b/core/VectorConfig.hpp @@ -0,0 +1,101 @@ +// -*- C++ -*- + +#pragma once + +namespace olympia +{ + /*! + * \class Vector config + * \brief + */ + class VectorConfig + { + public: + + // Vector register length in bits + static const uint32_t VLEN = 1024; + + using PtrType = sparta::SpartaSharedPointer; + + VectorConfig(uint32_t vl, uint32_t sew, uint32_t lmul, uint32_t vta) : + sew_(sew), + lmul_(lmul), + vl_(vl), + vlmax_(vlmax_formula_()), + vta_(vta) + { + // Check validity of vector config + sparta_assert(lmul_ <= 8, + "LMUL (" << lmul_ << ") cannot be greater than " << 8); + sparta_assert(vl_ <= vlmax_, + "VL (" << vl_ << ") cannot be greater than VLMAX ("<< vlmax_ << ")"); + } + + VectorConfig() = default; + + uint32_t getSEW() const { return sew_; } + void setSEW(uint32_t sew) + { + sew_ = sew; + vlmax_ = vlmax_formula_(); + } + + uint32_t getLMUL() const { return lmul_; } + void setLMUL(uint32_t lmul) + { + lmul_ = lmul; + vlmax_ = vlmax_formula_(); + } + + uint32_t getVL() const { return vl_; } + void setVL(uint32_t vl) + { + vl_ = vl; + } + + uint32_t getVLMAX() const { return vlmax_; } + + uint32_t getVTA() const { return vta_; } + void setVTA(uint32_t vta) + { + vta_ = vta; + } + + private: + uint32_t sew_ = 8; // set element width + uint32_t lmul_ = 1; // effective length + uint32_t vl_ = 16; // vector length + uint32_t vlmax_ = vlmax_formula_(); + bool vta_ = false; // vector tail agnostic, false = undisturbed, true = agnostic + + uint32_t vlmax_formula_() + { + return (VLEN / sew_) * lmul_; + } + }; + + using VectorConfigPtr = VectorConfig::PtrType; + + inline std::ostream & operator<<(std::ostream & os, const VectorConfig & vector_config) + { + os << "e" << vector_config.getSEW() << + "m" << vector_config.getLMUL() << + (vector_config.getVTA() ? "ta" : "") << + " vl: " << vector_config.getVL() << + " vlmax: " << vector_config.getVLMAX(); + return os; + } + + inline std::ostream & operator<<(std::ostream & os, const VectorConfig * vector_config) + { + if (vector_config) + { + os << *vector_config; + } + else + { + os << "nullptr"; + } + return os; + } +} // namespace olympia diff --git a/core/VectorUopGenerator.cpp b/core/VectorUopGenerator.cpp new file mode 100644 index 00000000..a67458ef --- /dev/null +++ b/core/VectorUopGenerator.cpp @@ -0,0 +1,261 @@ +#include "VectorUopGenerator.hpp" +#include "mavis/Mavis.h" +#include "sparta/utils/LogUtils.hpp" + +namespace olympia +{ + constexpr char VectorUopGenerator::name[]; + + VectorUopGenerator::VectorUopGenerator(sparta::TreeNode* node, const VectorUopGeneratorParameterSet* p) : + sparta::Unit(node) + { + // Vector arithmetic uop generator, increment all src and dest register numbers + // For a "vadd.vv v12, v4,v8" with an LMUL of 4: + // Uop 1: vadd.vv v12, v4, v8 + // Uop 2: vadd.vv v13, v5, v9 + // Uop 3: vadd.vv v14, v6, v10 + // Uop 4: vadd.vv v15, v7, v11 + { + constexpr bool SINGLE_DEST = false; + constexpr bool WIDE_DEST = false; + constexpr bool ADD_DEST_AS_SRC = false; + uop_gen_function_map_.emplace(InstArchInfo::UopGenType::ARITH, + &VectorUopGenerator::generateArithUop); + } + + // Vector arithmetic single dest uop generator, only increment all src register numbers + // For a "vmseq.vv v12, v4,v8" with an LMUL of 4: + // Uop 1: vadd.vv v12, v4, v8 + // Uop 2: vadd.vv v12, v5, v9 + // Uop 3: vadd.vv v12, v6, v10 + // Uop 4: vadd.vv v12, v7, v11 + { + constexpr bool SINGLE_DEST = true; + constexpr bool WIDE_DEST = false; + constexpr bool ADD_DEST_AS_SRC = false; + uop_gen_function_map_.emplace(InstArchInfo::UopGenType::ARITH_SINGLE_DEST, + &VectorUopGenerator::generateArithUop); + } + + // Vector arithmetic wide dest uop generator, only increment src register numbers for even uops + // For a "vwmul.vv v12, v4, v8" with an LMUL of 4: + // Uop 1: vwmul.vv v12, v4, v8 + // Uop 2: vwmul.vv v13, v4, v8 + // Uop 3: vwmul.vv v14, v6, v10 + // Uop 4: vwmul.vv v15, v6, v10 + // Uop 5: vwmul.vv v16, v8, v12 + // Uop 6: vwmul.vv v17, v8, v12 + // Uop 7: vwmul.vv v18, v10, v14 + // Uop 8: vwmul.vv v19, v10, v14 + { + constexpr bool SINGLE_DEST = false; + constexpr bool WIDE_DEST = true; + constexpr bool ADD_DEST_AS_SRC = false; + uop_gen_function_map_.emplace(InstArchInfo::UopGenType::ARITH_WIDE_DEST, + &VectorUopGenerator::generateArithUop); + } + + // Vector arithmetic multiplay-add wide dest uop generator, add dest as source + // For a "vmacc.vv v12, v4, v8" with an LMUL of 4: + // Uop 1: vwmacc.vv v12, v4, v8, v12 + // Uop 2: vwmacc.vv v13, v4, v8, v13 + // Uop 3: vwmacc.vv v14, v5, v9, v14 + // Uop 4: vwmacc.vv v15, v5, v9, v15 + // Uop 5: vwmacc.vv v16, v6, v10, v16 + // Uop 6: vwmacc.vv v17, v6, v10, v17 + // Uop 7: vwmacc.vv v18, v7, v11, v18 + // Uop 8: vwmacc.vv v19, v7, v11, v19 + { + constexpr bool SINGLE_DEST = false; + constexpr bool WIDE_DEST = false; + constexpr bool ADD_DEST_AS_SRC = true; + uop_gen_function_map_.emplace(InstArchInfo::UopGenType::ARITH_MAC, + &VectorUopGenerator::generateArithUop); + } + + // Vector arithmetic multiplay-add uop generator, add dest as source + // For a "vmacc.vv v12, v4, v8" with an LMUL of 4: + // Uop 1: vmacc.vv v12, v4, v8, v12 + // Uop 2: vmacc.vv v13, v5, v9, v13 + // Uop 3: vmacc.vv v14, v6, v10, v14 + // Uop 4: vmacc.vv v15, v7, v11, v15 + { + constexpr bool SINGLE_DEST = false; + constexpr bool WIDE_DEST = true; + constexpr bool ADD_DEST_AS_SRC = true; + uop_gen_function_map_.emplace(InstArchInfo::UopGenType::ARITH_MAC_WIDE_DEST, + &VectorUopGenerator::generateArithUop); + } + } + + void VectorUopGenerator::onBindTreeLate_() + { + mavis_facade_ = getMavis(getContainer()); + } + + void VectorUopGenerator::setInst(const InstPtr & inst) + { + sparta_assert(current_inst_ == nullptr, + "Cannot start generating uops for a new vector instruction, " + "current instruction has not finished: " << current_inst_); + + const auto uop_gen_type = inst->getUopGenType(); + sparta_assert(uop_gen_type != InstArchInfo::UopGenType::UNKNOWN, + "Inst: " << current_inst_ << " uop gen type is unknown"); + sparta_assert(uop_gen_type != InstArchInfo::UopGenType::NONE, + "Inst: " << current_inst_ << " uop gen type is none"); + + // Number of vector elements processed by each uop + const VectorConfigPtr & vector_config = inst->getVectorConfig(); + const uint64_t num_elems_per_uop = VectorConfig::VLEN / vector_config->getSEW(); + // TODO: For now, generate uops for all elements even if there is a tail + num_uops_to_generate_ = std::ceil(vector_config->getVLMAX() / num_elems_per_uop); + + if((uop_gen_type == InstArchInfo::UopGenType::ARITH_WIDE_DEST) || + (uop_gen_type == InstArchInfo::UopGenType::ARITH_MAC_WIDE_DEST)) + { + // TODO: Add parameter to support dual dests + num_uops_to_generate_ *= 2; + } + + current_inst_ = inst; + ILOG("Inst: " << current_inst_ << + " is being split into " << num_uops_to_generate_ << " UOPs"); + } + + const InstPtr VectorUopGenerator::generateUop() + { + const auto uop_gen_type = current_inst_->getUopGenType(); + sparta_assert(uop_gen_type <= InstArchInfo::UopGenType::NONE, + "Inst: " << current_inst_ << " uop gen type is unknown"); + + // Generate uop + auto uop_gen_func = uop_gen_function_map_.at(uop_gen_type); + const InstPtr uop = uop_gen_func(this); + + // setting UOp instructions to have the same UID and PID as parent instruction + uop->setUniqueID(current_inst_->getUniqueID()); + uop->setProgramID(current_inst_->getProgramID()); + + const VectorConfigPtr & vector_config = current_inst_->getVectorConfig(); + uop->setVectorConfig(vector_config); + uop->setUOpID(num_uops_generated_); + ++num_uops_generated_; + + // Set weak pointer to parent vector instruction (first uop) + sparta::SpartaWeakPointer parent_weak_ptr = current_inst_; + uop->setUOpParent(parent_weak_ptr); + + // Does this uop contain tail elements? + const uint32_t num_elems_per_uop = vector_config->getVLMAX() / vector_config->getSEW(); + uop->setTail((num_elems_per_uop * num_uops_generated_) > vector_config->getVL()); + + // Handle last uop + if(num_uops_generated_ == num_uops_to_generate_) + { + reset_(); + } + + ILOG("Generated uop: " << uop); + + return uop; + } + + template + const InstPtr VectorUopGenerator::generateArithUop() + { + // Increment source and destination register values + auto srcs = current_inst_->getSourceOpInfoList(); + for (auto & src : srcs) + { + // Do not increment scalar sources for transfer instructions + if (src.operand_type != mavis::InstMetaData::OperandTypes::VECTOR) + { + continue; + } + + if constexpr (WIDE_DEST == true) + { + // Only increment source values for even uops + src.field_value += (num_uops_generated_ % 2) ? num_uops_generated_ - 1 + : num_uops_generated_; + } + else + { + src.field_value += num_uops_generated_; + } + } + + // Add a destination to the list of sources + auto add_dest_as_src = [](auto & srcs, auto & dest) + { + // OperandFieldID is an enum with RS1 = 0, RS2 = 1, etc. with a max RS of RS4 + using OperandFieldID = mavis::InstMetaData::OperandFieldID; + const OperandFieldID field_id = static_cast(srcs.size()); + sparta_assert(field_id <= OperandFieldID::RS_MAX, + "Mavis does not support instructions with more than " << std::dec << + static_cast>(OperandFieldID::RS_MAX) << + " sources"); + srcs.emplace_back(field_id, dest.operand_type, dest.field_value); + }; + + auto dests = current_inst_->getDestOpInfoList(); + if constexpr (SINGLE_DEST == false) + { + for (auto & dest : dests) + { + dest.field_value += num_uops_generated_; + + if constexpr (ADD_DEST_AS_SRC == true) + { + add_dest_as_src(srcs, dest); + } + } + } + + // If uop contains tail or masked elements that need to be left undisturbed, we need to add + // the destination registers as source registers + if constexpr (ADD_DEST_AS_SRC == false) + { + const VectorConfigPtr & vector_config = current_inst_->getVectorConfig(); + const uint32_t num_elems_per_uop = vector_config->getVLMAX() / vector_config->getSEW(); + const bool uop_contains_tail_elems = (num_elems_per_uop * num_uops_generated_) > vector_config->getVL(); + + if (uop_contains_tail_elems && (vector_config->getVTA() == false)) + { + for (auto & dest : dests) + { + add_dest_as_src(srcs, dest); + } + } + } + + // Create uop + InstPtr uop; + if (current_inst_->hasImmediate()) + { + mavis::ExtractorDirectOpInfoList ex_info(current_inst_->getMnemonic(), + srcs, + dests, + current_inst_->getImmediate()); + uop = mavis_facade_->makeInstDirectly(ex_info, getClock()); + } + else + { + mavis::ExtractorDirectOpInfoList ex_info(current_inst_->getMnemonic(), + srcs, + dests); + uop = mavis_facade_->makeInstDirectly(ex_info, getClock()); + } + + return uop; + } + + void VectorUopGenerator::handleFlush(const FlushManager::FlushingCriteria & flush_criteria) + { + if(current_inst_ && flush_criteria.includedInFlush(current_inst_)) + { + reset_(); + } + } +} // namespace olympia diff --git a/core/VectorUopGenerator.hpp b/core/VectorUopGenerator.hpp new file mode 100644 index 00000000..d819ada5 --- /dev/null +++ b/core/VectorUopGenerator.hpp @@ -0,0 +1,80 @@ +// -*- C++ -*- +//! \file VectorUopGenerator.hpp +#pragma once + +#include "sparta/simulation/Unit.hpp" +#include "sparta/simulation/TreeNode.hpp" +#include "sparta/simulation/ParameterSet.hpp" + +#include "Inst.hpp" +#include "FlushManager.hpp" +#include "MavisUnit.hpp" + +namespace olympia +{ + + /** + * @file VectorUopGenerator.hpp + * @brief TODO + */ + class VectorUopGenerator : public sparta::Unit + { + public: + //! \brief Parameters for VectorUopGenerator model + class VectorUopGeneratorParameterSet : public sparta::ParameterSet + { + public: + VectorUopGeneratorParameterSet(sparta::TreeNode* n) : sparta::ParameterSet(n) {} + + //! \brief Generate uops for widening vector instructions with two dests + //PARAMETER(bool, widening_dual_dest, false, + // "Generate uops for widening vector instructions with two dests") + }; + + /** + * @brief Constructor for VectorUopGenerator + * + * @param node The node that represents (has a pointer to) the VectorUopGenerator + * @param p The VectorUopGenerator's parameter set + */ + VectorUopGenerator(sparta::TreeNode* node, const VectorUopGeneratorParameterSet* p); + + //! \brief Name of this resource. Required by sparta::UnitFactory + static constexpr char name[] = "vec_uop_gen"; + + void setInst(const InstPtr & inst); + + const InstPtr generateUop(); + + template + const InstPtr generateArithUop(); + + uint64_t getNumUopsRemaining() const { return num_uops_to_generate_; } + + void handleFlush(const FlushManager::FlushingCriteria &); + + private: + void onBindTreeLate_() override; + + MavisType * mavis_facade_; + + //typedef std::function FUNC; + typedef std::function UopGenFunctionType; + typedef std::map UopGenFunctionMapType; + UopGenFunctionMapType uop_gen_function_map_; + + // TODO: Use Sparta ValidValue + InstPtr current_inst_ = nullptr; + //UopGenFunctionMapType::iterator current_uop_gen_function_; + + uint64_t num_uops_generated_ = 0; + uint64_t num_uops_to_generate_ = 0; + + void reset_() + { + current_inst_ = nullptr; + num_uops_generated_ = 0; + num_uops_to_generate_ = 0; + } + }; +} // namespace olympia diff --git a/docs/dcache.md b/docs/dcache.md new file mode 100644 index 00000000..107a29c7 --- /dev/null +++ b/docs/dcache.md @@ -0,0 +1,51 @@ +# DCACHE + +### Ports + + +in_lsu_lookup_req <-- Input from LSU ( Receive memory request ) + +in_l2cache_ack <-- Input from L2Cache ( Receive acknowledgement from cache ) + +in_l2cache_resp <-- Input from L2Cache ( Receive data for the l2 cache lookup request) + +out_lsu_free_req <-- Output to LSU ( Send cache available for requests signal ) + +out_lsu_lookup_ack <-- Output to LSU ( Send acknowledgement for the memory reques to the LSU ) + +out_lsu_lookup_req <-- Output to LSU ( Send data for the LSU memory request ) + +out_l2cache_req <-- Output to L2Cache ( Send dirty cacheline to L2cache ) + +### Configuration parameters + +`l1_line_size` - Size of the DL1 cache line (power of 2) + +`l1_size_kb` - Size of DL1 in KB (power of 2) + +`l1_associativity` - DL1 associativity (power of 2) + +`l1_always_hit` - DL1 will always hit + +`mshr_entries` - Number of MSHR Entries + +### Available counters +`dl1_cache_hits` - Number of DL1 cache hits + +`dl1_cache_misses` - Number of DL1 cache misses + +`dl1_hit_miss_ratio` - Ratio between the DL1 HIT/MISS + +### Microarchitecture +The dcache has configurable number of mshr entries to handle requests in a non blocking manner. + +The Dcache arbitrates requests from LSU and cache refill response from L2 Cache. +The Dcache prioritizes cache refill request over incoming memory requests from the LSU. + +The Dcache has one only pipeline with 3 different stages + +| Stage | Cache Refill | Memory lookup request | +|------------|-------------------------------------------------|-------------------------| +| LOOKUP | Do nothing | Create MSHR entry | +| DATA READ | Update cache with refill information | Send L2 request if miss | +| DEALLOCATE | Deallocate mshr entries linked to the cacheline | Do nothing | diff --git a/docs/lsu.md b/docs/lsu.md new file mode 100644 index 00000000..e0b1a95b --- /dev/null +++ b/docs/lsu.md @@ -0,0 +1,85 @@ +# LSU +The design of the LSU is loosely based on the LSU implementation in [BOOM](https://docs.boom-core.org/en/latest/sections/load-store-unit.html) microarchitecture and the [E500](https://www.nxp.com/docs/en/reference-manual/E500CORERM.pdf) core. + +### Ports +in_lsu_insts <-- Input from Dispatch (Receive new memory instructions) + +in_cache_lookup_ack <-- Input from DCache (Receive acknowledgement from cache if the data is present) + +in_cache_lookup_req <-- Input from DCache (Receive data for the cache lookup request) + +in_cache_free_req <-- Input from DCache (Cache lets the lsu know that its ready to accept new lookup requests) + +out_cache_lookup_req --> Output to DCache (Send a cache lookup request for a particular address) + +in_mmu_lookup_ack <-- Input from MMU (Receive acknowledgement from MMU of particular virtual address lookup) + +in_mmu_lookup_req <-- Input from MMU (Receive physical address for the virtual address lookup request) + +out_mmu_lookup_req --> Output to DCache (Send a VA to PA address translation request) + + +### Configuration Parameters +`ldst_inst_queue_size` - Size of the LSU instruction queue + +`allow_speculative_load_exec` - Allow loads to proceed speculatively before all older store addresses are known. + +`replay_buffer_size` - Size of the replay buffer. Defaults to the same size of the LSU instruction queue. + +`replay_issue_delay` - Delay in cycles to replay the instruction. + +`mmu_lookup_stage_length` - Number of cycles to complete a MMU lookup stage. + +`cache_lookup_stage_length` - Number of cycles to complete a Cache lookup stage. + +`cache_read_stage_length` - Number of cycles to complete a Cache read stage + +### Available counters +`lsu_insts_dispatched` - Number of LSU instructions dispatched + +`stores_retired` - Number of stores retired + +`lsu_insts_issued` - Number of LSU instructions issued + +`replay_insts` - Number of Replay instructions issued + +`lsu_insts_completed` - Number of LSU instructions completed + +`lsu_flushes` - Number of instruction flushes at LSU + +### Microarchitecture +The Load Unit currently has only one pipeline. It has five distinct stages.The instructions always flow through the pipeline in the order mentioned below. + +- ADDRESS_CALCULATION - The virtual address is calculated +- MMU_LOOKUP - Translation of the VA to PA +- CACHE_LOOKUP - Lookup data for the PA present in the cache +- CACHE_READ - Receive data from the cache +- COMPLETION - Final stage of the pipeline to cleanup and deallocate instructions + +If the MMU or CACHE responds with a miss for the lookup requests, the instruction is removed from the pipeline.Once the units respond with an `ack`, the instruction is marked as ready to added back into the pipeline. + +The completion stage is responsible to remove the instruction from the issue queue once the instruction has completed executing. + +##### Typical Flow +``` +handleOperandIssueCheck_ -> + appendToReadyQueue_() -> + issueInst_() -> + handleAddressCalculation_() -> + handleMMULookupReq_() -> + handleCacheLookupReq_() -> + handleCacheRead_() -> + completeInst_() +``` +#### Speculative Execution +By default the LSU operates with `allow_speculative_execution`, which allows loads to proceed even if older load address is not know. + +The replay queue is used to store the instruction if the instruction has a corresponding miss from the mmu or cache. +The `replay_delay` specifies the delay until the request which was present in the replay queue needs to be added back into the pipeline. + +Speculated Load instructions are removed from the pipeline if an older store receives its PA or there are existing older stores that are waiting in the queue, this prevents the load store hazard. + +--- +### Others +The LSU contains a virtual queue called the `ready_queue` to hold instructions which are ready to be pushed into the LSU pipeline.This queue is model specific queue and doesnt affect the microarchitecture of the LSU.Its used to reduce quering the LSU's instruction queue for a potentially ready instruction. +It is based on a priority queue which sorts orders based on the age of the instruction. diff --git a/fsl b/fsl new file mode 160000 index 00000000..4d831428 --- /dev/null +++ b/fsl @@ -0,0 +1 @@ +Subproject commit 4d831428613523cd99611190c7ac8aea9bbc824c diff --git a/fusion/CMakeLists.txt b/fusion/CMakeLists.txt deleted file mode 100644 index 98766a18..00000000 --- a/fusion/CMakeLists.txt +++ /dev/null @@ -1,25 +0,0 @@ -cmake_minimum_required(VERSION 3.17) -project(FusionProject) - -set(CMAKE_POSITION_INDEPENDENT_CODE ON) -set(FUSION_TOP ${CMAKE_SOURCE_DIR}) - -add_subdirectory(fusion) -add_subdirectory(test) - -find_package(Doxygen) -if(DOXYGEN_FOUND) - set(DOXYGEN_IN ${CMAKE_CURRENT_SOURCE_DIR}/Doxyfile) - set(DOXYGEN_OUT ${CMAKE_CURRENT_BINARY_DIR}/Doxygen) - - configure_file(${DOXYGEN_IN} ${DOXYGEN_OUT} @ONLY) - - add_custom_target(docs - COMMAND ${DOXYGEN_EXECUTABLE} ${DOXYGEN_OUT} - WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} - COMMENT "Generating API documentation with Doxygen" - VERBATIM) -else() - message("Doxygen needs to be installed to generate documentation") -endif() - diff --git a/fusion/Doxyfile b/fusion/Doxyfile deleted file mode 100644 index a39946ba..00000000 --- a/fusion/Doxyfile +++ /dev/null @@ -1,401 +0,0 @@ -# Doxyfile 1.9.1 - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- -DOXYFILE_ENCODING = UTF-8 -PROJECT_NAME = "CAM Fusion API" -PROJECT_NUMBER = -PROJECT_BRIEF = -PROJECT_LOGO = -OUTPUT_DIRECTORY = -CREATE_SUBDIRS = NO -ALLOW_UNICODE_NAMES = NO -OUTPUT_LANGUAGE = English -#OUTPUT_TEXT_DIRECTION = None -BRIEF_MEMBER_DESC = YES -REPEAT_BRIEF = YES -ABBREVIATE_BRIEF = "The $name class" \ - "The $name widget" \ - "The $name file" \ - is \ - provides \ - specifies \ - contains \ - represents \ - a \ - an \ - the -ALWAYS_DETAILED_SEC = NO -INLINE_INHERITED_MEMB = NO -FULL_PATH_NAMES = YES -STRIP_FROM_PATH = -STRIP_FROM_INC_PATH = -SHORT_NAMES = NO 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messages -#--------------------------------------------------------------------------- -QUIET = NO -WARNINGS = YES -WARN_IF_UNDOCUMENTED = YES -WARN_IF_DOC_ERROR = YES -WARN_NO_PARAMDOC = NO -WARN_AS_ERROR = NO -WARN_FORMAT = "$file:$line: $text" -WARN_LOGFILE = -#--------------------------------------------------------------------------- -# Configuration options related to the input files -#--------------------------------------------------------------------------- -INPUT = \ - ./fusion/FieldExtractor.hpp \ - ./fusion/Fusion.hpp \ - ./fusion/FusionContext.hpp \ - ./fusion/FusionExceptions.hpp \ - ./fusion/FusionGroup.hpp \ - ./fusion/FusionTypes.hpp \ - ./fusion/MachineInfo.hpp \ - ./fusion/RadixTrie.hpp \ - ./test/Msg.hpp \ - ./test/Options.hpp \ - ./test/TestBench.hpp \ - README.md - -INPUT_ENCODING = UTF-8 -FILE_PATTERNS = *.c \ - *.cc \ - *.cxx \ - *.cpp \ - *.c++ \ - *.java \ - *.ii \ - *.ixx \ - *.ipp \ - *.i++ \ - *.inl \ - *.idl \ - *.ddl \ - *.odl \ - *.h \ - *.hh \ - *.hxx \ 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-#--------------------------------------------------------------------------- -# Configuration options related to external references -#--------------------------------------------------------------------------- -TAGFILES = -GENERATE_TAGFILE = -ALLEXTERNALS = NO -EXTERNAL_GROUPS = YES -EXTERNAL_PAGES = YES -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- -#CLASS_DIAGRAMS = YES -DIA_PATH = -HIDE_UNDOC_RELATIONS = YES -HAVE_DOT = YES -DOT_NUM_THREADS = 0 -#DOT_FONTNAME = Helvetica -#DOT_FONTSIZE = 10 -DOT_FONTPATH = -CLASS_GRAPH = YES -COLLABORATION_GRAPH = YES -GROUP_GRAPHS = YES -UML_LOOK = NO -UML_LIMIT_NUM_FIELDS = 10 -DOT_UML_DETAILS = NO -DOT_WRAP_THRESHOLD = 17 -TEMPLATE_RELATIONS = NO -INCLUDE_GRAPH = YES -INCLUDED_BY_GRAPH = YES -CALL_GRAPH = NO -CALLER_GRAPH = NO -GRAPHICAL_HIERARCHY = YES -DIRECTORY_GRAPH = YES -DOT_IMAGE_FORMAT = png -INTERACTIVE_SVG = NO -DOT_PATH = -DOTFILE_DIRS = -MSCFILE_DIRS = -DIAFILE_DIRS = -PLANTUML_JAR_PATH = -PLANTUML_CFG_FILE = -PLANTUML_INCLUDE_PATH = -DOT_GRAPH_MAX_NODES = 50 -MAX_DOT_GRAPH_DEPTH = 0 -#DOT_TRANSPARENT = NO -DOT_MULTI_TARGETS = NO -GENERATE_LEGEND = YES -DOT_CLEANUP = YES diff --git a/fusion/README.md b/fusion/README.md deleted file mode 100644 index 93588243..00000000 --- a/fusion/README.md +++ /dev/null @@ -1,150 +0,0 @@ -# Fusion API draft - -``` -Contact: Jeff Nye - Condor Computing - 2023.12.12 -``` - -There are (will be) two interfaces provided to support implementation of fusion and fracture transforms in Map/Sparta based models, the examples below will be from the CAM/Olympia implementations. - -# Changes - -A summary of some recent changes is below. This is an overview. - -## From FusionSequence to FusionGroup - -\note As the requirements on ordering are relaxed the term 'sequence' -became less accurate. I am switching to 'fusion group' or just group, -but there may be some text/code that still uses the term sequence. - -## From Init/Search/ConstraintsTransform to just Transform - -\note previously the transform process had multiple functors for -each expected phase of the fusion process. This was restrictive for an -API. There is now a single functor for transform specified within -a FusionGroup and a single functor for the top level fusion operator, see below. - -### Similar functor methods in top level - -\note The top level fusion operation is wrapped into a single -functor called Fusion::fusionOperator. This encompasses the complete -fusion operation for a list of Inst::PtrTypes. The default fusion operation -is a simple append. The intent is fusionOperator is overridden with a -user defined method that matches the functor signature, declared in -Fusion. - - -``` - - using FusionFuncType = std::function; - - - static void defaultFusionOpr(Fusion & inst, InstPtrListType & in, - InstPtrListType & out) - { - out.insert(out.end(), in.begin(), in.end()); - in.clear(); - } - -``` - -# Usage of the draft PR - -Pull the DPR, build and run the local testbench, create the doxygen docs. - -The dpr is on branch jeffnye-gh/fusion_dpr - -``` - -cd riscv-perf-model -mkdir release; cd release; cmake .. -DCMAKE_BUILD_TYPE=Release - - -cd ../fusion -mkdir -p release; cd release; cmake .. -make -j32 regress -make docs -``` - -# C++ API and testbench - -A C++ API is defined and a baseline set of implementations are provided. -The implementations are linked to the performance model using the conventional -callback mechanism. The C++ API is intended for compiled execution, regressions, etc. - -The testbench is contained in TestBench, test/testbench.h. - -## C++ API summary - - - The primary classes in the API are: - -``` - Fusion - FusionGroup (FusionGroupCfg) - MachineInfo - FieldExtractor -``` - -The top level class is Fusion, fusion/fusion.h. This is the primary -interface to Sparta based decoders. - -FusionGroup holds the definition of a fusable group of instructions. FusionGroup -provides functor handles for user defined methods. FusionGroupCfg is a -ctor helper struct/class for FusionGroup. - -MachineInfo is a placeholder (currently) for machine microarchitecture information pertinent to fusion and fusion performance modeling. - -FieldExtractor is a shim between FusionGroup functors and Mavis. It provides -boolean and field extraction methods. I expect this to change, either remove -the shim or increase the number of FieldExtractor setter/getter methods. - -There are multiple input mechanisms intended to simplify implementing -the fusion operation. Currently I am using UID. There will be support -for opcodes, assembly text, a DSL syntax and possibly a Json input format. - -UID based fusion is the example in this draft. The others are planned. - -## Other classes - -The support classes for Fusion are: - -``` - FusionContext fusioncontext.h - FusionExceptionBase fusionexceptions.h - using and typedefs fusiontypes.h - RadixTrie radixtrie.h -``` - -There is a single context supported in this version of the implementation but -generalization to multiple contexts has placeholders in the source. - -FusionExceptionBase is the parent for a a number of fusion/dsl/json/run-time exceptions specific to fusion. - -RadixTrie is experimental. It is implemented and provided for performance analysis during development. The currently used container is an unordered\_map -used for functionality and test development. - -## Usage within a Sparta unit - -The currently considered procedure for Fusion is an implementation in a -Sparta unit typically in the Decode. The primary input to the -fusionOperator() is a form of the InstQueue, sparta::Queue. -(Other forms such as InstGroup are likely). An output buffer of similar type is also provided to fusionOperator(). The fusionOperator() performs the -search across the current FusionGroup context and executes the transform -functor in the FusionGroup and places the results as appropriate in the output -queue and modifies the input queue as needed. - -The format of the input/output queues will likely be adjusted or additional -functor signatures will be provided. - -Both the top level and FusionGroup functors can be overridden by the user. The -API provides the functor signature and handle but otherwise the API does -not constrain how the functors operate. - -This gives the necessary generality and extensibility while keeping the -API definition unobtrusive. - -The remainder of the code and support classes are template based. - diff --git a/fusion/fusion/CMakeLists.txt b/fusion/fusion/CMakeLists.txt deleted file mode 100644 index 0e150675..00000000 --- a/fusion/fusion/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -cmake_minimum_required(VERSION 3.17) -project(FusionLibrary) - -add_library(FusionLib INTERFACE) - -target_include_directories(FusionLib INTERFACE - $ - $ # for install - ${CMAKE_CURRENT_SOURCE_DIR}/../../mavis - ${CMAKE_CURRENT_SOURCE_DIR}/../../mavis/mavis -) diff --git a/fusion/fusion/FieldExtractor.hpp b/fusion/fusion/FieldExtractor.hpp deleted file mode 100644 index c89d76e2..00000000 --- a/fusion/fusion/FieldExtractor.hpp +++ /dev/null @@ -1,270 +0,0 @@ -// HEADER PLACEHOLDER -// contact Jeff Nye, jeffnye-gh -// -//! \file FieldExtractor.hpp mavis shim, extract fields from encodings -#pragma once -#include "FusionExceptions.hpp" -#include "uArchInfo.hpp" -#include "Instruction.hpp" -#include "Mavis.h" -#include -#include -#include -#include -using namespace std; - -//! \class FieldExtractor -//! -//! \brief example class for extracting field values from mavis encodings -//! -//! This implementation provides a shim between operations typically -//! used during fusion contraint checking and transformation and mavis. -//! -//! The intent is any alternative to FieldExtractor could be created -//! if compliant with the interface. This has not been tested. -//! -//! It would also be interesting to determine if more of this could be -//! delegated to existing methods in mavis. -class FieldExtractor -{ - public: - //! \brief Part of mechanism to extract named fields from encodings - //! - //! OperandFieldID has no entry for immediates - //! \note I am overloading RS_MAX when referencing immediate fields - using FieldName = mavis::InstMetaData::OperandFieldID; - //! \brief alias used to extract Special fields by enum - using SFieldName = mavis::ExtractorIF::SpecialField; - - //! \brief ... - using InstPtrType = Instruction::PtrType; - //! \brief ... - using InstPtrListType = std::vector::PtrType>; - //! \brief type for getXRegs operations from mavis - using MavisBitMaskType = mavis::DecodedInstructionInfo::BitMask; - //! \brief type for getXRegs operations from mavis - using RegsGetter = MavisBitMaskType (Instruction::*)() const; - //! \brief duplicated arguments do not need to be explicitly expressed - using OptArg = std::optional; - - //! \brief compairson function primitives - enum FUNC - { - EQ, - LT - }; - - //! \brief extract value of named encoding field - //! - //! handles field name and immediate checking - uint32_t getField(InstPtrType inst, FieldName field) const - { - bool isDest = false; - if (!checkInstHasField(inst, field, isDest)) - { - throw fusion::FieldExtUnknownField((uint32_t)field, inst->dasmString()); - } - - return getFieldById(inst, field, isDest); - } - - //! \brief get the encoded value of a named special field from an - //! instptr - //! - //! This is simpler than getField, a return value of 0 from mavis - //! indicates the field does not exist so checkInstHasSField() - //! is redundant. getSFieldById() is also not necessary since - //! SpecialFields are not distinguished as a source or destination - //! operand and can be accessed from the same method. - uint32_t getSField(InstPtrType inst, SFieldName field) const - { - uint32_t value = inst->getSpecialField(field); - if (value == 0) - { - throw fusion::FieldExtUnknownSpecialField((uint32_t)field, inst->dasmString()); - } - return value; - // return getSFieldById(inst, field); - } - - //! \brief helper function for getField, src/dst switch - //! - //! isDest is set previously by checkInstHasField() - uint32_t getFieldById(InstPtrType inst, FieldName field, bool isDest) const - { - if (isDest) - { - return inst->getDestOpInfo().getFieldValue(field); - } - return inst->getSourceOpInfo().getFieldValue(field); - } - - //! \brief Use mavis to determine if the FieldName exists in this inst - //! obj - //! - //! Special case check for immediates; - //! srcOp and dstOps have to be checked separately. - //! - //! This is legally marked const, it does not modify *this, - //! but it does modifies the argument isDest. - bool checkInstHasField(InstPtrType inst, FieldName field, bool & isDest) const - { - if (inst->hasImmediate() && field == FieldName::RS_MAX) - { - return true; - } - - if (inst->getSourceOpInfo().hasFieldID(field) && field != FieldName::RS_MAX) - { - return true; - } - - // FIXME: I do not see the reason but this if statement will fail - // with - // terminate called after throwing an instance of - // 'mavis::OperandInfoInvalidFieldID' - // what(): OperandInfo field ID '' is invalid - // - // if(inst->getDestOpInfo().hasFieldID(field) && field != - // FieldName::RS_MAX) - // { - // isDest = true; - // return true; - // } - // - // But doing this is fine... - bool idok = inst->getDestOpInfo().hasFieldID(field); - bool fok = field != FieldName::RS_MAX; - if (idok && fok) - { - isDest = true; - return true; - } - - // catch fall through - throw fusion::FieldExtUnknownField((uint32_t)field, inst->dasmString()); - return false; ///... - } - - //! \brief equality - bool eq(const InstPtrListType & input, size_t a, size_t b, const FieldName f1, - const OptArg f2 = std::nullopt) const - { - return compare(input[a], input[b], f1, f2, EQ); - } - - //! \brief less than - bool lt(const InstPtrListType & input, size_t a, size_t b, const FieldName f1, - const OptArg f2 = std::nullopt) const - { - return compare(input[a], input[b], f1, f2, LT); - } - - //! \brief not equal - bool noteq(const InstPtrListType & input, size_t a, size_t b, const FieldName f1, - const OptArg f2 = std::nullopt) const - { - return !compare(input[a], input[b], f1, f2, EQ); - } - - //! \brief greater than - bool gt(const InstPtrListType & input, size_t a, size_t b, const FieldName f1, - const OptArg f2 = std::nullopt) const - { - return compare(input[b], input[a], f1, f2, LT); - } - - //! \brief less than or equal - bool lteq(const InstPtrListType & input, size_t a, size_t b, const FieldName f1, - const OptArg f2 = std::nullopt) const - { - return !compare(input[b], input[a], f1, f2, LT); - } - - //! \brief greater than or equal - bool gteq(const InstPtrListType & input, size_t a, size_t b, const FieldName f1, - const OptArg f2 = std::nullopt) const - { - return !compare(input[a], input[b], f1, f2, LT); - } - - //! \brief return the integer read ports used by the input fusion group - uint32_t getIntRdPorts(const InstPtrListType & input) const - { - return countPorts(input, &Instruction::getIntSourceRegs); - } - - //! \brief return the integer write ports used by the input fusion - //! group - uint32_t getIntWrPorts(const InstPtrListType & input) const - { - return countPorts(input, &Instruction::getIntDestRegs); - } - - //! \brief return the float read ports used by the input fusion group - uint32_t getFloatRdPorts(const InstPtrListType & input) const - { - return countPorts(input, &Instruction::getFloatSourceRegs); - } - - //! \brief return the float write ports used by the input fusion group - uint32_t getFloatWrPorts(const InstPtrListType & input) const - { - return countPorts(input, &Instruction::getFloatDestRegs); - } - - //! \brief return the vector read ports used by the input fusion group - uint32_t getVecRdPorts(const InstPtrListType & input) const - { - return countPorts(input, &Instruction::getVectorSourceRegs); - } - - //! \brief return the vector write ports used by the input fusion group - uint32_t getVecWrPorts(const InstPtrListType & input) const - { - return countPorts(input, &Instruction::getVectorDestRegs); - } - - private: - //! \brief compare common method - bool compare(const InstPtrType LHS, const InstPtrType RHS, const FieldName f1, const OptArg _f2, - FUNC func) const - { - FieldName f2 = _f2.value_or(f1); - - auto lhs = getField(LHS, f1); - auto rhs = getField(RHS, f2); - - // clang-format off - switch (func) - { - case FUNC::LT: - { - return lhs < rhs; - } - case FUNC::EQ: - { - return lhs == rhs; - } - default: - { - throw fusion::FieldExtUnknownFunction((uint32_t)func); - } - } - // clang-format on - - return false; - } - - //! \brief count the number of read or write ports required by the - //! group - uint32_t countPorts(const InstPtrListType & input, RegsGetter getRegs) const - { - mavis::DecodedInstructionInfo::BitMask mask; - for (const auto & i : input) - { - mask |= (i.get()->*getRegs)(); - } - return mask.count(); - } -}; diff --git a/fusion/fusion/Fusion.hpp b/fusion/fusion/Fusion.hpp deleted file mode 100644 index a3885acd..00000000 --- a/fusion/fusion/Fusion.hpp +++ /dev/null @@ -1,171 +0,0 @@ -// HEADER PLACEHOLDER -// contact Jeff Nye, jeffnye-gh, Condor Computing Corp. -// -//! \file Fusion.hpp top level fusion API -#pragma once -#include "FieldExtractor.hpp" -//#include "FslParser.hpp" -#include "FusionContext.hpp" -#include "FusionExceptions.hpp" -#include "FusionGroup.hpp" -#include "FusionTypes.hpp" -#include "MachineInfo.hpp" - -#include -#include -#include -#include - -namespace fusion -{ - //! \class Fusion - //! - //! \brief top level fusion class - //! - //! In this implementation the allocators are placeholder for - //! more complex use cases. They are provided for future - //! extensions. - //! - //! Input needed to create a fusion 'context' can come - //! from explicity construction of FusionGroups, construction - //! from the helper class FusionGroupCfg, and eventually - //! from the DSL or from Json. - //! - //! Both the DSL and JSON are future features. With the DSL - //! having a parser and a defined syntax. The JSON form has - //! no definition at the moment, the JSON form could be a simple - //! syntax variation of the DSL form. The linkage to the - //! transform function object needs to be defined for JSON. - //! - //! There is a single context assumed although there are - //! stubs for multiple context support. At the moment it - //! is not clear if multiple context are actually a - //! useful feature for fusion enabled instruction - //! decoders in the existing performance models. - //! - //! For usage see the testbench.cpp in fusion/test. For the - //! final PR there will more usage examples. - template , - typename MachineInfoTypeAlloc = fusion::ShrPtrAlloc, - typename FieldExtractorTypeAlloc = fusion::ShrPtrAlloc> - struct Fusion - { - //! \brief ... - using FusionGroupListType = std::vector; - //! \brief ... - using FusionGroupCfgType = fusion::FusionGroupCfg; - //! \brief ... - using FusionGroupCfgListType = std::vector; - //! \brief ... - using TransformFuncType = bool (*)(FusionGroupType &, InstPtrListType &, InstPtrListType &); - //! \brief ... - using FusionContextType = fusion::FusionContext; - - //! \brief ... - using FusionFuncType = std::function; - - //! \brief main ctor - Fusion( - const FusionGroupListType & fusiongroup_list, - const FusionGroupCfgListType & fusiongroupcfg_list, - const FusionGroupTypeAlloc fusiongroup_alloc = fusion::ShrPtrAlloc(), - const MachineInfoTypeAlloc machine_info_alloc = fusion::ShrPtrAlloc(), - const FieldExtractorType field_extractor_alloc = - fusion::ShrPtrAlloc()) : - fusiongroup_alloc_(fusiongroup_alloc), - machine_info_alloc_(machine_info_alloc), - fusionOpr(defaultFusionOpr) - { - if (fusiongroup_list.size() > 0) - initialize(fusiongroup_list); - else if (fusiongroupcfg_list.size() > 0) - initialize(fusiongroupcfg_list); - context_.makeContext("fbase", fusiongroup_list); - } - - //! \brief ctor from group list - Fusion(const FusionGroupListType & fusiongroup_list) : - Fusion(fusiongroup_list, {}, FusionGroupTypeAlloc(), MachineInfoTypeAlloc(), - FieldExtractorType()) - { - } - - //! \brief ctor from cfg group list - Fusion(const FusionGroupCfgListType & fusiongroupcfg_list) : - Fusion({}, fusiongroupcfg_list, FusionGroupTypeAlloc(), MachineInfoTypeAlloc(), - FieldExtractorType()) - { - } - - //! \brief initialize state from a group list - void initialize(const FusionGroupListType & fusiongroup_list) - { - for (auto grp : fusiongroup_list) - { - registerGroup(grp); - } - } - - //! \brief initialize from a group cfg list - void initialize(const FusionGroupCfgListType & grp_list) - { - for (auto cfg : grp_list) - { - FusionGroupType f(cfg); - registerGroup(f); - } - } - - //! \brief alias for context_.insertGroup() - void registerGroup(FusionGroupType & grp) { context_.insertGroup(grp); } - - //! \brief create a single context from a list of fusiongroups - //! - //! This is here to support generality but I have - //! not seen an immediate need for dynamic switching - //! between multiple fusion contexts in a simulation. - //! Something to consider for the future. - void makeContext(const std::string & name, const FusionGroupListType & fusiongroup_list) - { - context_.makeContext(name, fusiongroup_list); - } - - //! \brief interface to the fusion operation - //! - //! This is the principle interface to the fusion operation. - //! The operator can modify both input and output as needed. - //! The default operator appends in to out and clears in. - //! - //! fusionOpr can be assigned with a user function. - void fusionOperator(InstPtrListType & in, InstPtrListType & out) - { - fusionOpr(*this, in, out); - } - - //! \brief assign the functor handle with a custom operator - void setFusionOpr(FusionFuncType customOpr) { fusionOpr = customOpr; } - - //! \brief default fusion operator appends in to out and clears - //! out. - static void defaultFusionOpr(Fusion & inst, InstPtrListType & in, InstPtrListType & out) - { - out.insert(out.end(), in.begin(), in.end()); - in.clear(); - } - - //! \brief future feature - FusionGroupTypeAlloc fusiongroup_alloc_; - //! \brief future feature - MachineInfoTypeAlloc machine_info_alloc_; - //! \brief the current fusion state - //! - //! There is a single context in this version of the - //! code. This could expand to support multiple - //! simultaneous contexts if there is a use case. - FusionContextType context_; - //! \brief the fusion operation handle - FusionFuncType fusionOpr; - }; - -} // namespace fusion diff --git a/fusion/fusion/FusionContext.hpp b/fusion/fusion/FusionContext.hpp deleted file mode 100644 index fbd90dff..00000000 --- a/fusion/fusion/FusionContext.hpp +++ /dev/null @@ -1,89 +0,0 @@ -// HEADER PLACEHOLDER -// contact Jeff Nye, jeffnye-gh -// -//! \file FusionContext.hpp FusionGroup set context -#pragma once -#include "FusionExceptions.hpp" -#include "FusionTypes.hpp" - -#include -#include -#include -#include - -namespace fusion -{ - // ----------------------------------------------------------------------- - //! \class FusionContext - //! - //! - //! \brief Holds an searchable list of the current FusionGroups - //! - //! In this implementation the groups are held and searched - //! within a uo/map. There is a trie implementation but that - //! is not used currently. Before adding the trie if will be - //! useful to spend more time with large fusion group definitions - //! and see how the map performs vs the trie (or alternatives). - //! - //! Future abstration : typename container or typename tree: - //! typename FusionGroupContainerType = - //! std::unordered_map, - //! typename LookupType = fusion::ShrPtrAlloc - // ----------------------------------------------------------------------- - template class FusionContext - { - //! \brief for now this is a uo/map with uint key - using FusionGroupListType = std::vector; - //! \brief for now this is a uo/map with uint key - using FusionGroupContainerType = std::unordered_map; - // Future : using LookupType = RadixTrie<4>; - - public: - FusionContext() = default; - - //! \brief basic ctor - //! - //! name_ member is assigned in makeContext - FusionContext(const std::string & name, const FusionGroupListType & groups) - { - makeContext(name, groups); - } - - //! \brief insert each group into the (only/current) context - void makeContext(const std::string & n, const FusionGroupListType & groups) - { - name_ = n; - for (const auto & grp : groups) - { - insertGroup(grp); - } - } - - //! \brief insert each group in current context w/ catch - void insertGroup(const FusionGroupType & group) - { - fusion::HashType hash = group.hash(); - if (hash == 0) - { - throw fusion::HashIllegalValueError(group.name(), group.hash()); - } - - if (container_.find(hash) != container_.end()) - { - throw fusion::HashDuplicateError(group.name(), group.hash()); - } - container_.insert(std::make_pair(hash, group)); - } - - private: - //! \brief context name - //! - //! When this is used in (future) multi-context implementations - //! the name must be unique - std::string name_{"base_ctx"}; - //! \brief this is an alias for map in this version - FusionGroupContainerType container_; - // Future: LookupType lookup_; - }; - -} // namespace fusion diff --git a/fusion/fusion/FusionExceptions.hpp b/fusion/fusion/FusionExceptions.hpp deleted file mode 100644 index 25281364..00000000 --- a/fusion/fusion/FusionExceptions.hpp +++ /dev/null @@ -1,118 +0,0 @@ -// HEADER PLACEHOLDER -// contact Jeff Nye, jeffnye-gh -// -//! \file FusionExceptions.hpp fusion defined exceptions -#pragma once -#include "FusionTypes.hpp" - -#include -#include -#include -#include - -//! \class FusionExceptionBase -//! \class HashDuplicateError -//! \class HashIllegalValueError -//! \class ContextDuplicateError -//! \class FieldExtUnknownField -//! \class FieldExtUnknownSpecialField -//! \class FieldExtUnknownFunction - -namespace fusion -{ - - //! \brief exception base class for fusion operation exceptions - //! - //! There are a number of forward looking struct definitions. - //! In the final implementation I expect this set to be modified - class FusionExceptionBase : public std::exception - { - public: - //! \brief ... - const char* what() const noexcept override { return why_.c_str(); } - - protected: - //! \brief ... - std::string why_; - //! \brief ... - std::stringstream ss; - }; - - //! \brief hashes within a context can not overlap - //! - //! Each fusion group has a hash formed from the uids of the - //! in the group. The hash is the key into a uo/map. These hashes - //! are checked for uniqueness on construction - struct HashDuplicateError : FusionExceptionBase - { - //! \brief ... - explicit HashDuplicateError(const std::string & name, const fusion::HashType & hash) - { - ss << "Duplicated hash detected, '" << name << "'" - << " 0x" << std::hex << hash; - why_ = ss.str(); - } - }; - - //! \brief illegal hash value cause this to be thrown - //! - //! At the moment 0 is a reserved/illegal hash value - struct HashIllegalValueError : FusionExceptionBase - { - //! \brief ... - explicit HashIllegalValueError(const std::string & name, const fusion::HashType & hash) - { - ss << "Illegal hash value detected, '" << name << "'" - << " 0x" << std::hex << hash; - why_ = ss.str(); - } - }; - - //! \brief context name duplication was detected - //! - //! This supports (future feature) of multiple - //! contexts keyed off the context name string - struct ContextDuplicateError : FusionExceptionBase - { - //! \brief ... - explicit ContextDuplicateError(const std::string & name) - { - ss << "Duplicated context detected, '" << name << "'"; - why_ = ss.str(); - } - }; - - //! \brief field extractor unknown field name - struct FieldExtUnknownField : FusionExceptionBase - { - //! \brief ... - explicit FieldExtUnknownField(uint32_t fn, std::string dasm) - { - ss << "Unknown field: " << fn << " in " << dasm; - why_ = ss.str(); - } - }; - - //! \brief field extractor unknown special field name - struct FieldExtUnknownSpecialField : FusionExceptionBase - { - //! \brief ... - explicit FieldExtUnknownSpecialField(uint32_t sfn, std::string dasm) - { - ss << "Unknown special field: " << sfn << " in " << dasm; - why_ = ss.str(); - } - }; - - //! \brief field extractor unknown function - struct FieldExtUnknownFunction : FusionExceptionBase - { - //! \brief ... - explicit FieldExtUnknownFunction(uint32_t func) - { - ss << "Unknown function selection: " << func; - why_ = ss.str(); - } - }; - -} // namespace fusion diff --git a/fusion/fusion/FusionGroup.hpp b/fusion/fusion/FusionGroup.hpp deleted file mode 100644 index 931b8b21..00000000 --- a/fusion/fusion/FusionGroup.hpp +++ /dev/null @@ -1,314 +0,0 @@ -// HEADER PLACEHOLDER -// contact Jeff Nye, jeffnye-gh -// -//! \file FusionGroup.hpp holds fusion definitions and transforms -#pragma once -#include "FusionTypes.hpp" -#include "Instruction.hpp" -#include "Mavis.h" - -#include -#include -#include -#include -#include -#include -#include - -//! \class FusionGroupCfg - -namespace fusion -{ - //! \brief forward decl - template class FusionGroup; - - // --------------------------------------------------------------- - //! \brief FusionGroup ctor helper - //! - //! FusionGroupCfg helps construct FusionGroups from combinations - //! of ctor arguments. There is more work to do here. - //! - //! MachineInfoType provides access to implementation details of the machine - //! - //! FieldExtractor provides an interface to mavis and support functions - //! for boolean operations. - //! - //! (will) support: - //! UIDs implemented - //! opcodes not implemented, future feature - //! asm text not implemented, future feature - // --------------------------------------------------------------- - template struct FusionGroupCfg - { - //! \brief convenient group type - using FusionGroupType = FusionGroup; - - //! \brief transform functor signature - using TransformFuncType = bool (*)(FusionGroup &, - InstPtrListType &, InstPtrListType &); - - // Future feature - // uids can be derived from opcs, but not the other way - // if conversion from opcs to uids is required so is Mavis - // std::optional opcs; - // std::optional asms; - // fusion::MavisType *mavis{nullptr}; - - //! \brief default transform functor - //! - //! The group is not fused, input is appended to out. input is cleared. - static bool default_transform(FusionGroupType &, InstPtrListType & in, - InstPtrListType & out) - { - out.insert(std::end(out), std::begin(in), std::end(in)); - in.clear(); - return true; - } - - //! \brief convenient name string - const std::string name; - //! \brief list of UIDs representing the group - std::optional uids; - //! \brief handle for the transform function - //! - //! In previous implementations constraints checking and - //! transformation were enforced as split operations. This is - //! no longer required. - std::optional transformFunc = default_transform; - }; - - // --------------------------------------------------------------- - //! \brief FusionGroup parent - //! - //! opcs & asm statements are not supported yet, future - // --------------------------------------------------------------- - class FusionGroupBase - { - public: - //! \brief save typing - using UidType = fusion::UidType; - //! \brief save typing - using HashType = fusion::HashType; - //! \brief save typing - using InstPtrListType = fusion::InstPtrListType; - //! \brief save typing - using InstUidListType = fusion::InstUidListType; - - //! \brief base ctor - FusionGroupBase(std::string n = "", InstUidListType u = InstUidListType(), HashType h = 0) : - name_(n), - uids_(u), - // Future feature - // opcs_(fusion::OpcodeListType()), - // asms_(fusion::AsmStmtListType()), - hash_(h) - { - } - - //! \brief capture the UIDs and create the hash key - virtual void setUids(InstUidListType & u) - { - uids_ = u; - initHash(); - } - - //! \brief uids accessor - virtual InstUidListType & uids() { return uids_; } - - // virtual OpcodeListType& opcs() { return opcs_; } - // virtual AsmStmtListType& asms() { return asms_; } - - //! \brief hash setter - virtual void setHash(HashType hash) { hash_ = hash; } - - //! \brief refresh the hash from uids_ - virtual void initHash() { hash_ = jenkins_1aat(uids_); } - - //! \brief hash accessor - virtual HashType hash() const { return hash_; } - - //! \brief convenience function - virtual void setName(std::string n) { name_ = n; } - - //! \brief name accessor - virtual std::string name() const { return name_; } - - //! \brief report fgroup state to stream - //! - //! I prefer this instead of overloading << - virtual void info(std::ostream & os = std::cout) const - { - std::cout << "Name: " << name() << std::endl; - std::cout << " HASH: " << std::hex << " 0x" << hash() << std::endl; - std::cout << " UIDS: "; - for (auto u : uids_) - std::cout << std::hex << " 0x" << u; - std::cout << std::endl; - // Future feature - // std::cout<<" OPCs: "; - // for(auto o : opcs_) std::cout< & v) - { - HashType hash = 0; - - for (auto i : v) - { - hash += i; - hash += (hash << 10); - hash ^= (hash >> 6); - } - - hash += (hash << 3); - hash ^= (hash >> 11); - hash += (hash << 15); - - return hash; - } - - private: - //! \brief convenient name string - std::string name_{""}; - //! \brief the instruction UIDs known to mavis - InstUidListType uids_; - // Future feature - // OpcodeListType opcs_; - // AsmStmtListType asms_; - //! \brief uint32_t hash key - HashType hash_{0}; - }; - - // --------------------------------------------------------------- - //! \brief A fusion group is the basis for fusion detection and transformation - //! - //! A fusion group is a list of UIDs that represent data useful for - //! matching a group against incoming Inst::PtrTypes as well as - //! constraints checking. - //! - //! TransformFuncType transform_ is the functor handle. The default - //! is expected to be overridden externally. - // --------------------------------------------------------------- - template - class FusionGroup : public FusionGroupBase - { - //! \brief convenient typedef - using FusionGroupType = FusionGroup; - - //! \brief conform to convention used else where - using MavisType = Mavis, uArchInfo>; - - //! \brief convenient typedef - using FusionGroupCfgType = FusionGroupCfg; - - //! \brief functor signature and typedef - using TransformFuncType = bool (*)(FusionGroup &, - InstPtrListType &, InstPtrListType &); - - public: - //! \brief conform to convention used elsewhere - typedef typename std::shared_ptr> PtrType; - - // -------------------------------------------------------------------- - //! \brief default ctor - FusionGroup(std::string n = "", InstUidListType u = InstUidListType(), - TransformFuncType t = nullptr) : - FusionGroupBase(n, u), - transform_(t) - { - initHash(); - } - - // -------------------------------------------------------------------- - //! \brief groupcfg ctor - FusionGroup(const FusionGroupCfgType & cfg) : - FusionGroupBase(cfg.name, - cfg.uids ? *cfg.uids : InstUidListType() //, - // cfg.opcs ? *cfg.opcs : OpcodeListType() - ), - transform_(cfg.transformFunc ? *cfg.transformFunc : nullptr) - { - if (uids().size() == 0) - { - throw std::invalid_argument("For " + cfg.name - + " uids are required in this implementation"); - } - initHash(); - } - - //! \brief transform elements of input to append to output - //! - //! transform() is called when a fusiongroup is selected by - //! Fusion (fusion.h). The return value returns true if - //! the transform function met the criterion. False if not. - //! On false Fusion continues to search the context. - //! - //! The transform operation is expected to modify in if fusion - //! occurs and also to append to out with the transformation - //! results. All combinations of true/false, modifying/not modifying - //! input and output are valid. - bool transform(InstPtrListType & in, InstPtrListType & out) - { - if (transform_) - return transform_(*this, in, out); - return false; - } - - //! \brief default transform functor - //! - //! The group is not fused, input is appended to out. input is cleared. - static bool default_transform(FusionGroupType &, InstPtrListType & in, - InstPtrListType & out) - { - out.insert(std::end(out), std::begin(in), std::end(in)); - in.clear(); - return true; - } - - //! \brief user method for changing the default transform functor - void setTransform(TransformFuncType func) { transform_ = func; } - - //! \brief tranform handle accessor - TransformFuncType getTransform() { return transform_; } - - //! \brief machine info handle accessor - MachineInfoType & mi() { return mi_; } - - //! \brief machine info handle accessor - MachineInfoType & machineInfo() { return mi(); } - - //! \brief field extractor handle accessor - FieldExtractorType & fe() { return fe_; } - - //! \brief field extractor handle accessor - FieldExtractorType & fieldExtractor() { return fe(); } - - private: - //! \brief MachineInfo provides access to uarch details - MachineInfoType mi_; - //! \brief FieldExtractor provides field access methods - FieldExtractorType fe_; - //! \brief handle to transform functor - TransformFuncType transform_ = default_transform; - }; - -} // namespace fusion diff --git a/fusion/fusion/FusionTypes.hpp b/fusion/fusion/FusionTypes.hpp deleted file mode 100644 index c224e513..00000000 --- a/fusion/fusion/FusionTypes.hpp +++ /dev/null @@ -1,57 +0,0 @@ -// HEADER PLACEHOLDER -// contact Jeff Nye, jeffnye-gh -// -//! \file FusionTypes.hpp marshalled types used by fusion -#pragma once -#include "Mavis.h" -#include "mavis/DecoderTypes.h" -#include "Instruction.hpp" -#include "uArchInfo.hpp" -#include -#include -#include - -namespace fusion -{ - //! \brief ... - using MavisType = Mavis, uArchInfo>; - - //! \brief ... - using FileNameListType = std::vector; - - //! \brief ... - using UidType = mavis::InstructionUniqueID; - //! \brief ... - using InstUidListType = std::vector; - - //! \brief ... - using FieldName = mavis::InstMetaData::OperandFieldID; - //! \brief ... - using SFieldName = mavis::ExtractorIF::SpecialField; - //! \brief ... - using Opcode = mavis::Opcode; - //! \brief ... - using OpcodeListType = std::vector; - - //! \brief ... - using AsmStmtListType = std::vector; - - //! \brief ... - using InstPtrListType = std::vector::PtrType>; - //! \brief ... - using HashType = uint32_t; - - //! \brief This is provided but has limited use currently - template struct ShrPtrAlloc - { - //! \brief ... - using Tptr = std::shared_ptr; - - //! \brief ... - template Tptr operator()(Args &&... args) - { - return std::make_shared(std::forward(args)...); - } - }; - -} // namespace fusion diff --git a/fusion/fusion/Instruction.hpp b/fusion/fusion/Instruction.hpp deleted file mode 100644 index accab0bf..00000000 --- a/fusion/fusion/Instruction.hpp +++ /dev/null @@ -1,152 +0,0 @@ -// -// Created by David Murrell on 11/7/19. -// -// JN: original file name was Inst.h - -#pragma once - -#include -#include -#include "mavis/OpcodeInfo.h" -#include "mavis/Extractor.h" - -/** - * EXAMPLE Instruction - */ -template class Instruction -{ - public: - typedef typename std::shared_ptr> PtrType; - - public: - // Instruction(const mavis::DecodedInstructionInfo::PtrType& dii, const - // uint64_t icode, const mavis::ExtractorIF::PtrType& extractor, const - // typename AnnotationType::PtrType& ui) : - Instruction(const mavis::OpcodeInfo::PtrType & dinfo, - const typename AnnotationType::PtrType & ui, uint32_t dummy) : - dinfo_(dinfo), - uinfo_(ui) - { - } - - // Copy construction (needed for cloning) - Instruction(const Instruction &) = default; - - // Morph into a different instruction (new mavis info) - void morph(const typename mavis::OpcodeInfo::PtrType & new_dinfo, - const typename AnnotationType::PtrType & new_ui) - { - // dinfo_.reset(new_dinfo); - dinfo_ = new_dinfo; - // uinfo_.reset(new_ui); - uinfo_ = new_ui; - - // TBD: Instruction user may need to reset any information cached with this - // instruction - } - - /** - * User code to "recycle" an instruction (which DTable has cached and is - * attempting to reuse) - */ - void recycle() {} - - typename mavis::OpcodeInfo::PtrType getOpInfo() const { return dinfo_; } - - std::string getMnemonic() const { return dinfo_->getMnemonic(); } - - std::string dasmString() const { return dinfo_->dasmString(); } - - bool isInstType(mavis::InstMetaData::InstructionTypes itype) const - { - return dinfo_->isInstType(itype); - } - - bool isExtInstType(mavis::DecodedInstructionInfo::ExtractedInstTypes itype) const - { - return dinfo_->isExtractedInstType(itype); - } - - int64_t getSignedOffset() const { return dinfo_->getSignedOffset(); } - - mavis::DecodedInstructionInfo::BitMask getSourceAddressRegs() const - { - return dinfo_->getSourceAddressRegs(); - } - - mavis::DecodedInstructionInfo::BitMask getSourceDataRegs() const - { - return dinfo_->getSourceDataRegs(); - } - - mavis::DecodedInstructionInfo::BitMask getIntSourceRegs() const - { - return dinfo_->getIntSourceRegs(); - } - - mavis::DecodedInstructionInfo::BitMask getFloatSourceRegs() const - { - return dinfo_->getFloatSourceRegs(); - } - - mavis::DecodedInstructionInfo::BitMask getVectorSourceRegs() const - { - return dinfo_->getVectorSourceRegs(); - } - - mavis::DecodedInstructionInfo::BitMask getIntDestRegs() const - { - return dinfo_->getIntDestRegs(); - } - - mavis::DecodedInstructionInfo::BitMask getFloatDestRegs() const - { - return dinfo_->getFloatDestRegs(); - } - - mavis::DecodedInstructionInfo::BitMask getVectorDestRegs() const - { - return dinfo_->getVectorDestRegs(); - } - - uint64_t getSpecialField(mavis::OpcodeInfo::SpecialField sfid) const - { - return dinfo_->getSpecialField(sfid); - } - - const mavis::OperandInfo & getSourceOpInfo() const { return dinfo_->getSourceOpInfo(); } - - const mavis::OperandInfo & getDestOpInfo() const { return dinfo_->getDestOpInfo(); } - - mavis::InstructionUniqueID getUID() const { return dinfo_->getInstructionUniqueID(); } - - bool hasImmediate() const { return dinfo_->hasImmediate(); } - - const typename AnnotationType::PtrType & getuArchInfo() const { return uinfo_; } - - // private: - typename mavis::OpcodeInfo::PtrType dinfo_; - typename AnnotationType::PtrType uinfo_; - - void print(std::ostream & os) const - { - std::ios_base::fmtflags os_state(os.flags()); - os << dinfo_->getMnemonic() << ", src[" << dinfo_->numSourceRegs() - << "]: " << dinfo_->getSourceRegs() << " (addr: " << dinfo_->getSourceAddressRegs() - << ")" - << ", dst: " << dinfo_->getDestRegs() << ", data size: " << std::dec - << dinfo_->getDataSize(); - if (uinfo_ != nullptr) - { - os << ", uInfo: " << *uinfo_; - } - os.flags(os_state); - } - - public: - friend std::ostream & operator<<(std::ostream & os, const Instruction & i) - { - i.print(os); - return os; - } -}; diff --git a/fusion/fusion/MachineInfo.hpp b/fusion/fusion/MachineInfo.hpp deleted file mode 100644 index 4c018592..00000000 --- a/fusion/fusion/MachineInfo.hpp +++ /dev/null @@ -1,77 +0,0 @@ -// HEADER PLACEHOLDER -// contact Jeff Nye, jeffnye-gh -// -//! \file MachineInfo.hpp processor implementation details -#pragma once -#include -#include -#include -#include - -//! \brief Placeholder for uarch and implementation details -//! -//! I have not followed up on the discussion on using -//! extension.core_extensions from the yaml for this information. -//! This is future work. -struct MachineInfo -{ - //! \brief there is only a default constructor provided - MachineInfo() {} - - //! \brief access number of implemented integer write ports - uint32_t maxIntWrPorts() const { return maxIntWrPorts_; } - - //! \brief access number of implemented float write ports - uint32_t maxFpWrPorts() const { return maxFpWrPorts_; } - - //! \brief access number of implemented vector write ports - uint32_t maxVecWrPorts() const { return maxVecWrPorts_; } - - //! \brief access number of implemented integer read ports - uint32_t maxIntRdPorts() const { return maxIntRdPorts_; } - - //! \brief access number of implemented float read ports - uint32_t maxFpRdPorts() const { return maxFpRdPorts_; } - - //! \brief access number of implemented vector read ports - uint32_t maxVecRdPorts() const { return maxVecRdPorts_; } - - //! \brief Is there a location available to execute a fused operator? - //! - //! Obviously, a placeholder. This would be a debug function - //! trap dispatch to execute pipes that do not implement the fused opr. - bool compSiteImplemented(uint32_t magic) const { return true; } - - //! \brief how many cycles to wait for the InstrQueue to fill - //! - //! Since fusion operates on 1 or more opcodes there are cases - //! where the InstrQueue may not have enough opcodes to validate - //! fusion groups. This is more of an issue for N-tuples > 2. - //! At some point the cycles saved by fusion are spent waiting - //! for fusable opportunities. This limits the impact. - uint32_t allowedLatency() const { return allowedLatency_; } - - //! \brief ... - void setName(std::string n) { name_ = n; } - - //! \brief ... - std::string name() const { return name_; } - - private: - //! \brief arbitrary name - std::string name_{"noname"}; - //! \brief ... - uint32_t maxIntWrPorts_{2}; - //! \brief ... - uint32_t maxFpWrPorts_{2}; - //! \brief ... - uint32_t maxVecWrPorts_{2}; - //! \brief ... - uint32_t maxIntRdPorts_{4}; - //! \brief ... - uint32_t maxFpRdPorts_{4}; - //! \brief ... - uint32_t maxVecRdPorts_{4}; - //! \brief ... - uint32_t allowedLatency_{1}; -}; diff --git a/fusion/fusion/RadixTrie.hpp b/fusion/fusion/RadixTrie.hpp deleted file mode 100644 index 6f7b738f..00000000 --- a/fusion/fusion/RadixTrie.hpp +++ /dev/null @@ -1,113 +0,0 @@ -// HEADER PLACEHOLDER -// contact Jeff Nye, jeffnye-gh -// -//! \file RadixTrie.hpp space optimized search tree(trie) -#pragma once -#include -#include -#include -#include -#include -#include -#include - -//! \brief Node for uint32_t radix trie -//! -template class RadixTrieNode -{ - public: - //! \brief ... - bool isEndOfWord; - //! \brief ... - std::vector> children; - - //! \brief ... - RadixTrieNode() : isEndOfWord(false) - { - children.resize(1 << BIT_WIDTH); - for (auto & child : children) - { - child = nullptr; - } - } -}; - -//! \brief RadixTrie with element width as template parameter -//! -//! This is self explanatory. 4 bits seems to be the most performant, -//! for state sizes of 1024*1024. -//! -//! This is not used in the current implementation. It is provided -//! in the DPR for comment on future use and because I am comparing -//! performance against real sets of fusion groups. There is little -//! to no protection against 'bad' input. That will come later. -//! -//! 1 1024*1024 -//! Time taken for insertion: 7.31112 seconds -//! Time taken for searching: 1.26558 seconds -//! 2 1024*1024 -//! Time taken for insertion: 4.85911 seconds -//! Time taken for searching: 0.691898 seconds -//! 4 1024*1024 -//! Time taken for insertion: 4.77562 seconds <=== 4 bits -//! Time taken for searching: 0.43249 seconds -//! 8 1024*1024 -//! Time taken for insertion: 25.8369 seconds -//! Time taken for searching: 0.319623 seconds -template class RadixTrie -{ - public: - //! \brief per convention used elsewhere - typedef std::shared_ptr PtrType; - - //! \brief default ctor - RadixTrie() : root(std::make_unique>()) {} - - //! \brief insert... - void insert(uint32_t key) { insertRecursive(root, key, 0); } - - //! \brief find... - bool search(uint32_t key) const { return searchRecursive(root, key, 0); } - - private: - //! \brief ... - void insertRecursive(std::unique_ptr> & node, uint32_t key, - uint32_t depth) - { - if (!node) - { - node = std::make_unique>(); - } - - if (depth == MAX_DEPTH) - { - node->isEndOfWord = true; - return; - } - - uint32_t index = (key >> (BIT_WIDTH * (MAX_DEPTH - depth - 1))) & ((1 << BIT_WIDTH) - 1); - insertRecursive(node->children[index], key, depth + 1); - } - - //! \brief ... - bool searchRecursive(const std::unique_ptr> & node, uint32_t key, - uint32_t depth) const - { - if (!node) - { - return false; - } - if (depth == MAX_DEPTH) - { - return node->isEndOfWord; - } - uint32_t index = (key >> (BIT_WIDTH * (MAX_DEPTH - depth - 1))) & ((1 << BIT_WIDTH) - 1); - return searchRecursive(node->children[index], key, depth + 1); - } - - //! \brief top of the trie - std::unique_ptr> root; - - //! \brief keep a limit on depth based on the template parameter - static constexpr uint32_t MAX_DEPTH = std::numeric_limits::digits / BIT_WIDTH; -}; diff --git a/fusion/fusion/uArchInfo.hpp b/fusion/fusion/uArchInfo.hpp deleted file mode 100644 index 74415582..00000000 --- a/fusion/fusion/uArchInfo.hpp +++ /dev/null @@ -1,214 +0,0 @@ -// -// Created by David Murrell on 12/2/19. -// -#pragma once -#include "json.hpp" -#include "mavis/DecoderExceptions.h" -#include "mavis/DecoderTypes.h" -#include "uArchInfoExceptions.hpp" - -#include -#include -#include -#include - -/** - * uArchInfo: encapsulates "static" u-arch specific information - */ -class uArchInfo -{ - public: - typedef std::shared_ptr PtrType; - - // TODO: flesh this out - enum class UnitSet : uint64_t - { - AGU = 1ull << 0, - INT = 1ull << 1, - FLOAT = 1ull << 2, - MULTIPLY = 1ull << 3, - DIVIDE = 1ull << 4, - BRANCH = 1ull << 5, - LOAD = 1ull << 6, - STORE = 1ull << 7, - SYSTEM = 1ull << 8, - VECTOR = 1ull << 9, - }; - - // BEGIN: Stuff imported from the old StaticInstructionData object - enum RegFile - { - INTEGER, - FLOAT, - INVALID, - N_REGFILES = INVALID - }; - - static inline const char* const regfile_names[] = {"integer", "float"}; - - // TODO: resolve this against the UnitSet - enum IssueTarget : std::uint16_t - { - IEX, - FEX, - BR, - LSU, - ROB, // Instructions that go right to retire - N_ISSUE_TARGETS - }; - - static constexpr uint32_t MAX_ARCH_REGS = 5; - // END: Stuff imported from the old StaticInstructionData object - - private: - // Map unit names to unit ID's - static inline std::map umap_ = { - {"agu", UnitSet::AGU}, {"int", UnitSet::INT}, {"float", UnitSet::FLOAT}, - {"mul", UnitSet::MULTIPLY}, {"div", UnitSet::DIVIDE}, {"branch", UnitSet::BRANCH}, - {"load", UnitSet::LOAD}, {"store", UnitSet::STORE}, {"system", UnitSet::SYSTEM}, - {"vector", UnitSet::VECTOR}, - }; - - // TEMPORARY: map unit names to TargetUnit for back-level compatibility - static inline std::map issue_target_map_ = { - {"int", IssueTarget::IEX}, {"float", IssueTarget::FEX}, - {"branch", IssueTarget::BR}, {"load", IssueTarget::LSU}, - {"store", IssueTarget::LSU}, {"system", IssueTarget::ROB}, // TEMPORARY! - {"vector", IssueTarget::FEX}, // TEMPORARY! - {"rob", IssueTarget::ROB}, // TEMPORARY! - }; - - public: - /** - * \brief This object encapsulates all the micro-architectural information - * that depends on the instruction type. It is "static" and cached by Mavis in - * the instruction factories. Mavis will pass the nlohmann::json object to - * this constructor so that the user can parse any of the desired fields from - * the u-arch JSON file supplied to Mavis \param jobj nlohmann::json object - * for the given instruction - */ - explicit uArchInfo(const nlohmann::json & jobj) { parse_(jobj); } - - uArchInfo() = default; - uArchInfo(const uArchInfo &) = delete; - - void update(const nlohmann::json & jobj) - { - // TODO: identical to constructor(jobj) for now, but we may want to provide - // update restrictions - parse_(jobj); - } - - bool isUnit(UnitSet u) const { return (static_cast(u) & units_) != 0; } - - IssueTarget getIssueTarget() const { return issue_target_; } - - uint32_t getLatency() const { return latency_; } - - bool isPipelined() const { return pipelined_; } - - bool isSerialized() const { return serialize_; } - - bool isROBGrpStart() const { return rob_grp_start_; } - - bool isROBGrpEnd() const { return rob_grp_end_; } - - private: - uint64_t units_ = 0; ///< Bit mask of target execution units (from UnitSet) - IssueTarget issue_target_ = IssueTarget::N_ISSUE_TARGETS; ///< Issue target - uint32_t latency_ = 0; ///< Execution latency - bool pipelined_ = true; ///< Pipelined execution (non-blocking)? - bool serialize_ = false; ///< Serializes execution? - bool rob_grp_start_ = false; ///< Starts a new ROB group? - bool rob_grp_end_ = false; ///< Ends a ROB group? - - private: - friend std::ostream & operator<<(std::ostream & os, const uArchInfo & ui); - - void print(std::ostream & os) const - { - os << "{units: 0x" << std::hex << units_ << ", lat: " << std::dec << latency_ - << ", piped: " << pipelined_ << ", serialize: " << serialize_ - << ", ROB group begin: " << rob_grp_start_ << ", ROB group end: " << rob_grp_end_ << "}"; - } - - /** - * \brief Parse the JSON file - * \param jobj - */ - void parse_(const nlohmann::json & jobj) - { - // Issue target (from IssueTarget) - if (jobj.find("issue") != jobj.end()) - { - const auto itr = issue_target_map_.find(jobj["issue"]); - if (itr == issue_target_map_.end()) - { - throw uArchInfoUnknownIssueTarget(jobj["mnemonic"], jobj["issue"]); - } - issue_target_ = itr->second; - } - - // Target execution unit (from UnitSet) -- bit mask allows multiple targets - if (jobj.find("unit") != jobj.end()) - { - mavis::UnitNameListType ulist = jobj["unit"].get(); - for (const auto & u : ulist) - { - const auto itr = umap_.find(u); - if (itr == umap_.end()) - { - throw uArchInfoUnknownUnit(jobj["mnemonic"], u); - } - units_ |= static_cast(itr->second); - } - } - - // Instruction latency - if (jobj.find("latency") != jobj.end()) - { - latency_ = jobj["latency"]; - } - - // Whether the instruction is piplined (non-blocking) - if (jobj.find("pipelined") != jobj.end()) - { - pipelined_ = jobj["pipelined"]; - } - - // Whether the instruction serializes execution - if (jobj.find("serialize") != jobj.end()) - { - serialize_ = jobj["serialize"]; - } - - // Whether the instruction starts a new ROB group - if (jobj.find("rob_group") != jobj.end()) - { - mavis::StringListType slist = jobj["rob_group"].get(); - for (const auto & str : slist) - { - if (str == "begin") - { - rob_grp_start_ = true; - } - else if (str == "end") - { - rob_grp_end_ = true; - } - else - { - throw uArchInfoROBGroupParseError(jobj["mnemonic"], str); - } - } - } - - std::cout << "uArchInfo: " << jobj["mnemonic"] << std::endl; - } -}; - -inline std::ostream & operator<<(std::ostream & os, const uArchInfo & ui) -{ - ui.print(os); - return os; -} diff --git a/fusion/fusion/uArchInfoExceptions.hpp b/fusion/fusion/uArchInfoExceptions.hpp deleted file mode 100644 index 625f33c5..00000000 --- a/fusion/fusion/uArchInfoExceptions.hpp +++ /dev/null @@ -1,89 +0,0 @@ -// -// Created by David Murrell on 2/19/20. -// -#pragma once - -#include -#include -#include - -/** - * Decoder exceptions base class - */ -class uArchInfoBaseException : public std::exception -{ - public: - virtual const char* what() const noexcept { return why_.c_str(); } - - protected: - std::string why_; -}; - -/** - * uArchInfo parse error: the given unit for the instruction was not found by - * the uArchInfo object. - * - * This can happen from a mis-spelling of the unit in the JSON, or from a need - * to update the uArchInfo's list of supported units - */ -class uArchInfoUnknownUnit : public uArchInfoBaseException -{ - public: - uArchInfoUnknownUnit(const std::string & mnemonic, const std::string & unit_name) : - uArchInfoBaseException() - { - std::stringstream ss; - ss << "Instruction '" << mnemonic << "': " - << " unit '" << unit_name << "' " - << "is not known (uArchInfo object). Could be a mis-spelling in the " - "JSON file"; - why_ = ss.str(); - } -}; - -/** - * uArchInfo parse error: the given issue target for the instruction was not - * found by the uArchInfo object. - * - * This can happen from a mis-spelling of the issue target in the JSON, or from - * a need to update the uArchInfo's list of supported units - */ -class uArchInfoUnknownIssueTarget : public uArchInfoBaseException -{ - public: - uArchInfoUnknownIssueTarget(const std::string & mnemonic, const std::string & target_name) : - uArchInfoBaseException() - { - std::stringstream ss; - ss << "Instruction '" << mnemonic << "': " - << " issue target '" << target_name << "' " - << "is not known (uArchInfo object). Could be a mis-spelling in the " - "JSON file"; - why_ = ss.str(); - } -}; - -/** - * uArchInfo parsing error: the given ROB group begin/end stanza in the JSON is - * malformed - * - * This can happen from a mis-spelling of the rob_group key in the JSON. The - * form should be one of the following: - * - * "rob_group" : ["begin"] - * "rob_group" : ["end"] - * "rob_group" : ["begin", "end"] - */ -class uArchInfoROBGroupParseError : public uArchInfoBaseException -{ - public: - uArchInfoROBGroupParseError(const std::string & mnemonic, const std::string & bad_string) : - uArchInfoBaseException() - { - std::stringstream ss; - ss << "Instruction '" << mnemonic << "': " - << " rob_group element '" << bad_string << "'" - << " is not valid. Needs to be one of 'begin' or 'end'"; - why_ = ss.str(); - } -}; diff --git a/fusion/test/CMakeLists.txt b/fusion/test/CMakeLists.txt deleted file mode 100644 index 6e6524f1..00000000 --- a/fusion/test/CMakeLists.txt +++ /dev/null @@ -1,55 +0,0 @@ -cmake_minimum_required(VERSION 3.17) -project(FusionTest) - -set(CMAKE_POSITION_INDEPENDENT_CODE ON) - -find_library(MAVIS_LIBRARY NAMES mavis - HINTS "${CMAKE_SOURCE_DIR}/../release/mavis" - "${CMAKE_SOURCE_DIR}/../debug/mavis" - "${CMAKE_SOURCE_DIR}/../fastdebug/mavis" - "${CMAKE_SOURCE_DIR}/../build/mavis") - -if(NOT MAVIS_LIBRARY) - message(FATAL_ERROR "libmavis.a not found") -endif() - -add_library(mavis STATIC IMPORTED) - -set_target_properties(mavis PROPERTIES IMPORTED_LOCATION ${MAVIS_LIBRARY}) - -add_executable(fusiontest - TestBench.cpp - TestData.cpp - TestFieldExtractor.cpp - main.cpp - Options.cpp ) - -target_compile_options(fusiontest PRIVATE -Wall -Wextra - -Wno-unused-parameter # mavis - ) - -find_package(Boost REQUIRED COMPONENTS program_options) -if(Boost_FOUND) - target_include_directories(fusiontest PRIVATE ${Boost_INCLUDE_DIRS}) - target_link_libraries(fusiontest - PRIVATE FusionLib mavis - PRIVATE ${Boost_LIBRARIES} pthread ) -else() - message(SEND_ERROR "Boost is a required package for the testbench") -endif() - -set(JSON_BASE "${FUSION_TOP}/test/json") - -set(TB_OPTS --tb_verbose) - -# There is a mavis required dependency for c after g -set(ISA_FILES - --isa_file ${JSON_BASE}/isa_rv64g.json - --isa_file ${JSON_BASE}/isa_rv64c.json) - -list(APPEND OPTS ${ISA_FILES} - ${TB_OPTS}) - -add_custom_target(regress - COMMAND fusiontest ${OPTS} -) diff --git a/fusion/test/Msg.hpp b/fusion/test/Msg.hpp deleted file mode 100644 index 53533b55..00000000 --- a/fusion/test/Msg.hpp +++ /dev/null @@ -1,118 +0,0 @@ -// HEADER PLACEHOLDER -// contact Jeff Nye, jeffnye-gh -// -//! \file Msg.hpp header for simple uniform messages -#pragma once -#include -#include -#include -#include - -//! \brief singleton for standardized messages -//! -//! I use this to standardize local output. -//! -//! I'm using an ad hoc test bench, a compliant testbench -//! would be part of a fusion capable Sparta unit. In that -//! case this would be replaced with the mechanism found -//! in the unit benches. -struct Msg -{ - //! \brief get the singleton instance - static Msg* getInstance() - { - if (!instance) - instance = new Msg; - return instance; - } - - ~Msg() {} // dtor - - //! \brief this adds an identifier prefix to messages - //! - //! Example -I:MYUNIT: {message} - void setWho(std::string _w) { w = _w + ": "; } - - //! \brief shared message method - void mmsg(std::string p, std::string m) const { std::cout << p << w << m << std::endl; } - - //! \brief debug messages - void dmsg(std::string m = "", int v = 4) const - { - if (v <= verbose) - mmsg("-D: ", m); - } - - //! \brief error messages - void emsg(std::string m = "", int v = 1) const - { - if (v <= verbose) - mmsg("-E: ", m); - } - - //! \brief info messages - void imsg(std::string m = "", int v = 3) const - { - if (v <= verbose) - mmsg("-I: ", m); - } - - //! \brief warining messages - void wmsg(std::string m = "", int v = 2) const - { - if (v <= verbose) - mmsg("-W: ", m); - } - - //! \brief ... - void msg(std::string m) const { std::cout << m << std::endl; } - - //! \brief helper to show potentially empty strings - std::string tq(std::string s) const { return "'" + s + "'"; } - - // ---------------------------------------------------------------- - //! \brief ... - std::string w; - /** - * \brief verbosity setting - * - * \verbatim - * verbose 0 - silent - * 1 - errors - * 2 - errors,warnings - * 3 - errors,warnings,info - * >= 4 - errors,warnings,info,debug4 - * - debug messages can be a various levels, debugN - * \endverbatim - */ - - //! \brief ... - int verbose{3}; - - //! \brief ... - static Msg* instance; - - private: - //! \brief ... - Msg() - { - w = ""; - verbose = 3; - } - - // ------------------------------------------------------------------- - // Msg(std::string _who="",int _verbose=3) - // : w(_who+": "), - // verbose(_verbose) - // {} - // ------------------------------------------------------------------- - //! \brief ...copy - Msg(const Msg &) = delete; - //! \brief ...move - Msg(Msg &&) = delete; - //! \brief ...assign - Msg & operator=(const Msg &) = delete; -}; - -//! \brief ... -extern std::unique_ptr msg; diff --git a/fusion/test/Options.cpp b/fusion/test/Options.cpp deleted file mode 100644 index b52e7b77..00000000 --- a/fusion/test/Options.cpp +++ /dev/null @@ -1,99 +0,0 @@ -// HEADER PLACEHOLDER -// contact Jeff Nye, jeffnye-gh, Condor Computing Corp. -// -#include "Msg.hpp" -#include "Options.hpp" -#include -using namespace std; - -// -------------------------------------------------------------------- -// Build the option set and check the options -// -------------------------------------------------------------------- -void Options::setupOptions(int ac, char** av) -{ - notify_error = false; - - po::options_description visibleOpts("\nFusion API test\n " - "Usage:: test [--help|-h|--version|-v] { options }"); - - po::options_description stdOpts("Standard options"); - buildOptions(stdOpts); - - try - { - po::store(po::command_line_parser(ac, av).options(stdOpts).run(), vm); - - // Without positional option po::parse_command_line can be used - // po::store(po::parse_command_line(ac, av, allOpts), vm); - } - catch (boost::program_options::error & e) - { - msg->msg(""); - msg->emsg("1st pass command line option parsing failed"); - msg->emsg("What: " + string(e.what())); - usage(stdOpts); - exit(1); - } - - po::notify(vm); - if (!checkOptions(vm, stdOpts, true)) - exit(1); -} - -// -------------------------------------------------------------------- -// Construct the std, hidden and positional option descriptions -// -------------------------------------------------------------------- -// clang-format off -void Options::buildOptions(po::options_description & stdOpts) -{ - stdOpts.add_options() - - ("help,h", "...") - - ("version,v", "report version and exit") - - ("stf", po::value(&stf_file), "STF input file") - - ("output,o", po::value(&output_file), - "Log output file") - - ("isa_file", po::value>(&isa_files), - "Multiple --isa_file accepted") - - ("tb_verbose", po::bool_switch(&tb_verbose) ->default_value(false), - "Test bench message control"); -} - -// clang-format on -// -------------------------------------------------------------------- -// Check sanity on the options, handle --help, --version -// -------------------------------------------------------------------- -bool Options::checkOptions(po::variables_map & vm, po::options_description & stdOpts, - bool firstPass) -{ - if (firstPass) - { - if (vm.count("help")) - { - usage(stdOpts); - return false; - } - if (vm.count("version")) - { - version(); - return false; - } - } - - return true; -} - -// -------------------------------------------------------------------- -// -------------------------------------------------------------------- -void Options::version() const -{ - msg->imsg(""); - msg->imsg("Fusion api tester"); - msg->imsg("Slack jeff w/any questions"); - msg->imsg(""); -} diff --git a/fusion/test/Options.hpp b/fusion/test/Options.hpp deleted file mode 100644 index 697749cf..00000000 --- a/fusion/test/Options.hpp +++ /dev/null @@ -1,76 +0,0 @@ -// HEADER PLACEHOLDER -// contact Jeff Nye, jeffnye-gh -// -//! \file Options.hpp testbench options -#pragma once -#include -#include -#include -#include -namespace po = boost::program_options; - -//! \brief container for boost program option settings -struct Options -{ - // ---------------------------------------------------------------- - //! \brief singleton - // ---------------------------------------------------------------- - static Options* getInstance() - { - if (!instance) - instance = new Options(); - return instance; - } - - // ---------------------------------------------------------------- - // support methods - // ---------------------------------------------------------------- - //! \brief ... - void buildOptions(po::options_description &); - - //! \brief ... - bool checkOptions(po::variables_map &, po::options_description &, bool); - - //! \brief ... - void setupOptions(int, char**); - - //! \brief ... - void usage(po::options_description & o) const { std::cout << o << std::endl; } - - //! \brief ... - void version() const; - - // ---------------------------------------------------------------- - //! \brief future STF file support in test bench - std::string stf_file{""}; - //! \brief ... - std::string output_file{""}; - //! \brief ... - std::vector isa_files; - //! \brief enable extra messages from the tb - bool tb_verbose{false}; - // ---------------------------------------------------------------- - // ---------------------------------------------------------------- - //! \brief ... - bool notify_error{false}; - //! \brief placeholder - bool _query_options{false}; - //! \brief ... - po::variables_map vm; - //! \brief ... - static Options* instance; - - private: - //! \brief ... - Options() {} - - //! \brief ... - Options(const Options &) = delete; - //! \brief ... - Options(Options &&) = delete; - //! \brief ... - Options & operator=(const Options &) = delete; -}; - -//! \brief ... -extern std::shared_ptr opts; diff --git a/fusion/test/TestBench.cpp b/fusion/test/TestBench.cpp deleted file mode 100644 index c5ed2ce4..00000000 --- a/fusion/test/TestBench.cpp +++ /dev/null @@ -1,665 +0,0 @@ -// HEADER PLACEHOLDER -// contact Jeff Nye, jeffnye-gh, Condor Computing Corp. -// -#include "FieldExtractor.hpp" -#include "Fusion.hpp" -#include "FusionContext.hpp" -#include "FusionGroup.hpp" -#include "FusionTypes.hpp" -#include "MachineInfo.hpp" -#include "Msg.hpp" -#include "Options.hpp" -#include "RadixTrie.hpp" -#include "TestBench.hpp" - -#include - -#include -#include -#include -#include -#include -#include -using namespace std; - -// ==================================================================== -// ==================================================================== -TestBench::TestBench(int ac, char** av) -{ - msg->setWho("TestBench"); - opts->setupOptions(ac, av); - verbose = opts->tb_verbose; -} - -// -------------------------------------------------------------------- -// -------------------------------------------------------------------- -bool TestBench::run() -{ - // sanity check files - if (!sanityTest()) - return false; - if (!basicMavisTest()) - return false; - if (!basicConstraintsTest()) - return false; - if (!fusionGroupAltCtorTest()) - return false; - if (!fusionGroupCfgCtorTest()) - return false; - if (!fusionContextTest(true)) - return false; - - if (!fusionCtorCompileTest(true)) - return false; - if (!fusionSearchTest(true)) - return false; - - // FieldExtractor method tests - if (!fieldExtractorTests(true)) - return false; - - return true; -} - -// -------------------------------------------------------------------- -// -------------------------------------------------------------------- -bool TestBench::fusionContextTest(bool debug) -{ - if (verbose) - msg->imsg("fusionContextTest BEGIN"); - - using FusionGroupType = fusion::FusionGroup; - using FusionGroupListType = std::vector; - - fusion::FusionContext context_; - - FusionGroupType grp1("uf1", uf1, cbProxy::uf1_func); - FusionGroupType grp2("uf2", uf2, cbProxy::uf2_func); - FusionGroupType grp3("uf3", uf3, cbProxy::uf3_func); - - FusionGroupListType grouplist = {grp1, grp2, grp3}; - - try - { - context_.makeContext("fusionContextTest", grouplist); - } - catch (const fusion::ContextDuplicateError & e) - { - std::cerr << "Caught ContextDuplicateError: " << e.what() << endl; - } - catch (const std::exception & e) - { - std::cerr << "Caught unclassified exception: " << e.what() << endl; - return false; - } - - if (verbose) - msg->imsg("fusionContextTest END"); - return true; -} - -// -------------------------------------------------------------------- -// -------------------------------------------------------------------- -bool TestBench::fusionSearchTest(bool debug) -{ - if (verbose) - msg->imsg("fusionSearchTest BEGIN"); - bool ok = true; - - using FusionGroupType = fusion::FusionGroup; - using FusionGroupCfgType = fusion::FusionGroupCfg; - using FusionType = fusion::Fusion; - - FusionType::FusionGroupCfgListType testCases = { - FusionGroupCfgType{.name = {"UF1"}, - .uids = uf1, - .transformFunc = &TestBench::cbProxy::uf1_func}, - FusionGroupCfgType{.name = {"UF1_1"}, - .uids = uf1_1, - .transformFunc = &TestBench::cbProxy::uf1_1_func}, - FusionGroupCfgType{.name = {"UF1_2"}, - .uids = uf1_2, - .transformFunc = &TestBench::cbProxy::uf1_2_func}, - FusionGroupCfgType{.name = {"UF1_3"}, - .uids = uf1_3, - .transformFunc = &TestBench::cbProxy::uf1_3_func}, - FusionGroupCfgType{.name = {"UF2"}, - .uids = uf2, - .transformFunc = &TestBench::cbProxy::uf2_func}, - FusionGroupCfgType{.name = {"UF3"}, - .uids = uf3, - .transformFunc = &TestBench::cbProxy::uf3_func}}; - - // Future add specific tests for hash creation - // std::unordered_map expHashes; - // generateExpectHashes(expHashes,testCases); - - InstPtrListType in, out; - - assign(in, of1, opts->isa_files); - assign(out, of1, opts->isa_files); - - size_t outSize = out.size(); - size_t inSize = in.size(); - - FusionType f(testCases); - f.fusionOperator(in, out); - - // The default operator appends in to out and clears in - if (in.size() != 0) - { - msg->emsg("fusionOperator failed to clean input vector"); - ok = false; - } - - if (out.size() != (outSize + inSize)) - { - msg->emsg("fusionOperator failed to properly append to output vector"); - ok = false; - } - - // Test the custom operator as lambda - auto customLambda = - [](FusionType & inst, fusion::InstPtrListType & in, fusion::InstPtrListType & out) - { - out = in; // in is not cleared - }; - - // Restore in/out - in.clear(); - out.clear(); - InstPtrListType tmp; - assign(in, of1, opts->isa_files); - inSize = in.size(); - - f.setFusionOpr(customLambda); - f.fusionOperator(in, out); - - // Did the lambda clear the in vector - if (in.size() == 0) - { - msg->emsg("the custom fusionOperator incorrectly cleared the " - "input vector"); - ok = false; - } - - // The resulting out vector should be the same size as in and tmp - bool sameSize = inSize == out.size() && inSize == in.size(); - if (!sameSize) - { - msg->emsg("with the custom fusionOperator the vector sizes are " - "mismatched"); - ok = false; - } - - if (verbose) - msg->imsg("fusionSearchTest END"); - return ok; -} - -// -------------------------------------------------------------------- -// -------------------------------------------------------------------- -void TestBench::generateExpectHashes(unordered_map & exp, - const FusionType::FusionGroupCfgListType & in) -{ - for (size_t i = 0; i < in.size(); ++i) - { - FusionGroupCfgType cfg = in[i]; - fusion::HashType expHash = jenkinsOneAtATime(cfg.uids.value()); - exp.insert(make_pair(cfg.name, expHash)); - } -} - -// -------------------------------------------------------------------- -// -------------------------------------------------------------------- -bool TestBench::fusionCtorCompileTest(bool debug) -{ - if (verbose) - msg->imsg("fusionCtorCompileTest BEGIN"); - bool ok = true; - - using FusionGroupType = fusion::FusionGroup; - using FusionType = fusion::Fusion; - - const FusionType::FusionGroupListType fusionGroup_list = {}; - const FusionType::FusionGroupCfgListType fusionGroupCfg_list = {}; - - FusionType f4(fusionGroup_list); - FusionType f5(fusionGroupCfg_list); - - if (verbose) - msg->imsg("fusionCtorCompileTest END"); - return ok; -} - -// -------------------------------------------------------------------- -// -------------------------------------------------------------------- -bool TestBench::basicMavisTest(bool debug) -{ - if (verbose) - msg->imsg("basicMavisTest BEGIN"); - InstUidListType goldenUid = uf1; // { 0xb, 0xd, 0x1c, 0xf, 0x13 }; - OpcodeListType goldenOpc = of1; // { 0x76e9,0x685,0x8d35,0x1542,0x9141 }; - - Instruction::PtrType inst = nullptr; - - using MavisType = Mavis, uArchInfo>; - MavisType mavis_facade(opts->isa_files, {}); - - // Make sure the opcodes convert correctly - InstPtrListType instrs; - for (const auto opc : goldenOpc) - { - try - { - instrs.emplace_back(mavis_facade.makeInst(opc, 0)); - } - catch (const mavis::IllegalOpcode & ex) - { - cout << ex.what() << endl; - msg->emsg("basicMavisTest failed to convert opcode"); - return false; - } - } - - InstUidListType uids; - for (const auto & inst : instrs) - { - uids.emplace_back(inst->getUID()); - } - - if (instrs.size() != goldenUid.size() || instrs.size() != goldenOpc.size() - || instrs.size() != uids.size()) - { - msg->emsg("basicMavisTest size mismatch in inst vector"); - return false; - } - - if (debug) - info(goldenUid, uids, instrs); - - if (verbose) - msg->imsg("basicMavisTest END"); - return true; -} - -// -------------------------------------------------------------------- -// -------------------------------------------------------------------- -bool TestBench::fusionGroupAltCtorTest() -{ - if (verbose) - msg->imsg("fusionGroupAltCtorTest BEGIN"); - - // fusion ctor compile checks - fusion::FusionGroup f1; - fusion::FusionGroup f2{}; - fusion::FusionGroup f3 = - fusion::FusionGroup(); - - struct OtherMachine - { - OtherMachine() {} - }; - - struct OtherExtractor - { - OtherExtractor() {} - }; - - // Alternative machineinfo and extractor - using AltFusionGroupType = fusion::FusionGroup; - - InstUidListType alt_uid = {}; - - AltFusionGroupType alt1("alt1"); - AltFusionGroupType alt2("alt2", alt_uid); - - struct proxy - { - static bool alt_func(AltFusionGroupType &, InstPtrListType &, InstPtrListType &) - { - return true; - } - }; - - bool ok = true; - - AltFusionGroupType alt3("alt3", alt_uid); - alt3.setTransform(proxy::alt_func); - - InstPtrListType in, out; - - if (!alt3.transform(in, out)) - { - msg->emsg("alt3.transform() failed"); - ok = false; - } - - AltFusionGroupType alt4("alt4", alt_uid, proxy::alt_func); - if (!alt4.transform(in, out)) - { - msg->emsg("alt4.transform() failed"); - ok = false; - } - - if (verbose) - msg->imsg("fusionGroupAltCtorTest END"); - return ok; -} - -// -------------------------------------------------------------------- -// -------------------------------------------------------------------- -bool TestBench::fusionGroupCfgCtorTest() -{ - if (verbose) - msg->imsg("fusionGroupCfgCtorTest BEGIN"); - using FusionGroupCfgType = fusion::FusionGroupCfg; - - // --------------------------------------------------------------- - // Test that hash created from the F1CfgUid matches the hash from a - // base class reference instance - // --------------------------------------------------------------- - // reference version - fusion::FusionGroupBase reference; - reference.setUids(uf1); - fusion::HashType referenceHash = reference.hash(); - - // With uids, no opcs, no mavis - FusionGroupCfgType F1CfgUid{.name = {"F1CfgUid"}, - .uids = uf1, - .transformFunc = &f1_constraints}; - - bool ok = true; - - using FusionGroupType = fusion::FusionGroup; - FusionGroupType F1fromF1CfgUid(F1CfgUid); - - F1fromF1CfgUid.info(); - - if (referenceHash != F1fromF1CfgUid.hash()) - { - msg->emsg("F1fromF1CfgUid hash does not match reference hash"); - ok = false; - } - // --------------------------------------------------------------- - // Test that the F1CfgUid ctor results in a FusionGroup that can - // correctly transform this input group - InstPtrListType in, out; - // assign the input vector before transform - assign(in, of1, opts->isa_files); - - if (!F1fromF1CfgUid.transform(in, out)) - { - msg->emsg("F1fromF1CfgUid.transform() returned false"); - ok = false; - } - - if (in.size() != 0) - { - msg->emsg("F1fromF1CfgUid.f1_constraints failed to modify input"); - ok = false; - } - if (out.size() != 1) - { - msg->emsg("F1fromF1CfgUid.f1_constraints failed to modify output"); - ok = false; - } - // --------------------------------------------------------------- - // Test that a FusionGroupCfg constructed from opcodes acts like - // a FusionGroupCfg constructed from respective UIDs - // - // Future support - - // --------------------------------------------------------------- - // Test that a FusionGroupCfg constructed from assembly statements acts - // like a FusionGroupCfg constructed from respective UIDs - // - // Future support - - if (verbose) - msg->imsg("fusionGroupCfgCtorTest END"); - return ok; -} - -// -------------------------------------------------------------------- -// Fusion group transform test -// -------------------------------------------------------------------- -bool TestBench::basicConstraintsTest() -{ - if (verbose) - msg->imsg("basicConstraintsTest BEGIN"); - - FusionGroupType F1("F1", TestBench::uf1, f1_constraints); - - InstPtrListType in; - InstPtrListType out; - - // Create instr from opcodes - assign(in, of1, opts->isa_files); - - bool ok = true; - - if (!F1.transform(in, out)) - { - msg->emsg("F1.transform() returned false"); - ok = false; - } - - if (in.size() != 0) - { - msg->emsg("F1.f1_constraints failed to modify input"); - ok = false; - } - - if (out.size() != 1) - { - msg->emsg("F1.f1_constraints failed to modify output"); - ok = false; - } - - FusionGroupType F2("F2", TestBench::uf2); - - if (F2.getTransform() != nullptr) - { - msg->emsg("F2.transform() was not a nullptr as expected"); - ok = false; - } - - F2.setTransform(f1_constraints); - - if (F2.getTransform() == nullptr) - { - msg->emsg("F2.transform() was not set to handler as expected"); - ok = false; - } - - if (F2.transform(in, out)) - { - msg->emsg("F2.transform() failed to reject uf2 sequence"); - ok = false; - } - - if (verbose) - msg->imsg("basicConstraintsTest END"); - return ok; -} - -// -------------------------------------------------------------------- -// -------------------------------------------------------------------- -bool TestBench::radixTrieTest(bool) -{ - if (verbose) - msg->imsg("radixTrieTest BEGIN"); - RadixTrie<4> trie; - uint32_t num_values = 1024 * 1024; - - bool ok = true; - - std::mt19937 generator(std::random_device{}()); - std::uniform_int_distribution distribution(0, std::numeric_limits::max()); - - auto start = std::chrono::high_resolution_clock::now(); - for (uint32_t i = 0; i < num_values; ++i) - { - uint32_t randomNumber = distribution(generator); - trie.insert(randomNumber); - } - - auto end = std::chrono::high_resolution_clock::now(); - std::chrono::duration insertDuration = end - start; - std::cout << "Time taken for insertion: " << insertDuration.count() << " seconds" << std::endl; - - start = std::chrono::high_resolution_clock::now(); - for (uint32_t i = 0; i < num_values; ++i) - { - uint32_t randomNumber = distribution(generator); - trie.search(randomNumber); - } - - end = std::chrono::high_resolution_clock::now(); - std::chrono::duration searchDuration = end - start; - std::cout << "Time taken for searching: " << searchDuration.count() << " seconds" << std::endl; - - trie.insert(12345); - trie.insert(67890); - - std::cout << "Found '12345' " << (trie.search(12345) ? "Yes" : "No") << std::endl; - std::cout << "Found '67890' " << (trie.search(67890) ? "Yes" : "No") << std::endl; - std::cout << "Found '54321' " << (trie.search(54321) ? "Yes" : "No") << std::endl; - - if (trie.search(12345) && trie.search(67890) && !trie.search(54321)) - { - ok = true; - } - else - { - ok = false; - } - if (verbose) - msg->imsg("radixTrieTest END"); - return ok; -} - -// -------------------------------------------------------------------- -// -------------------------------------------------------------------- -bool TestBench::sanityTest(bool) -{ - bool ok = true; - - for (auto fn : opts->isa_files) - { - if (!std::filesystem::exists(fn)) - { - msg->emsg("Can not find isa file " + fn); - ok = false; - } - } - - return ok; -} - -// -------------------------------------------------------------------- -// -------------------------------------------------------------------- -void TestBench::assign(InstPtrListType & in, OpcodeListType & opcodes, - const FileNameListType & json_files) -{ - using MavisType = Mavis, uArchInfo>; - MavisType mavis_facade(json_files, {}); - - Instruction::PtrType inst = nullptr; - - for (const auto icode : opcodes) - { - try - { - in.emplace_back(mavis_facade.makeInst(icode, 0)); - } - catch (const mavis::IllegalOpcode & ex) - { - cout << ex.what() << endl; - } - } -} - -// ------------------------------------------------------------------------ -// zoo.F1 specific checks -// -// Operand requirements -// - rgrp[0].RD == rgrp[1].RD == rgrp[2].RS2 (note RS2 change) -// - rgrp[2].RD == rgrp[3].RD == rgrp[4].RD -// - rgrp[3].IMM == rgrp[4].IMM getField IMM not implemented -// ------------------------------------------------------------------------ -bool TestBench::f1_constraints(FusionGroupType & g, InstPtrListType & in, InstPtrListType & out) -{ - // This goup expects at least 5 instruction positions in the input - if (in.size() < 5) - return false; - - // number of wr/rd ports required by group tested against machine - // limits - if (g.fe().getIntWrPorts(in) > g.mi().maxIntWrPorts()) - return false; - if (g.fe().getIntRdPorts(in) > g.mi().maxIntRdPorts()) - return false; - - // using enum FieldExtractor::FieldName; requires c++20 - constexpr auto RD = FieldExtractor::FieldName::RD; - constexpr auto RS2 = FieldExtractor::FieldName::RS2; - - // Operand field encodings comparison against constraints - // The indexes are positions in the group, 0 = 1st instruction - if (g.fe().noteq(in, 0, 1, RD) || g.fe().noteq(in, 0, 2, RD, RS2) || g.fe().noteq(in, 2, 3, RD) - || g.fe().noteq(in, 2, 4, RD)) - { - return false; - } - - // This test only does constraints checking - fake a transform - out.emplace_back(in[0]); - in.clear(); - return true; -} - -// -------------------------------------------------------------------- -// -------------------------------------------------------------------- -fusion::HashType TestBench::jenkinsOneAtATime(const ::vector & v) -{ - fusion::HashType hash = 0; - - for (auto i : v) - { - hash += i; - hash += (hash << 10); - hash ^= (hash >> 6); - } - - hash += (hash << 3); - hash ^= (hash >> 11); - hash += (hash << 15); - - return hash; -} - -// -------------------------------------------------------------------- -void TestBench::info(InstUidListType & aUIDs, InstUidListType & bUIDs, InstPtrListType & instrs) -{ - cout << "aUIDs "; - for (auto uid : aUIDs) - { - cout << " 0x" << setw(8) << hex << setfill('0') << uid; - } - cout << endl; - cout << "bUIDs "; - for (auto uid : bUIDs) - { - cout << " 0x" << setw(8) << hex << setfill('0') << uid; - } - cout << endl; - - cout << "Instrs" << endl; - string pad = " "; - for (auto inst : instrs) - { - cout << pad << inst << endl; - } -} diff --git a/fusion/test/TestBench.hpp b/fusion/test/TestBench.hpp deleted file mode 100644 index d9c801e3..00000000 --- a/fusion/test/TestBench.hpp +++ /dev/null @@ -1,238 +0,0 @@ -// HEADER PLACEHOLDER -// contact Jeff Nye, jeffnye-gh -// -//! \file TestBench.hpp testbench interface and utils -#pragma once -#include "Msg.hpp" -#include "FieldExtractor.hpp" -#include "Fusion.hpp" -#include "FusionGroup.hpp" -#include "FusionTypes.hpp" -#include "MachineInfo.hpp" - -//! \class TestBench -// ==================================================================== -// ==================================================================== -//! \brief local test bench for Fusion and related classes -struct TestBench -{ - //! \brief save typing - using FusionGroupType = fusion::FusionGroup; - //! \brief save typing - using FusionGroupListType = std::vector; - - //! \brief save typing - using FusionGroupCfgType = fusion::FusionGroupCfg; - - //! \brief save typing - using FusionType = fusion::Fusion; - - //! \brief save typing - using InstUidListType = fusion::InstUidListType; - - //! \brief save typing - using InstPtrListType = fusion::InstPtrListType; - - //! \brief save typing - using FileNameListType = fusion::FileNameListType; - - //! \brief save typing - using Opcode = fusion::Opcode; - - //! \brief save typing - using OpcodeListType = fusion::OpcodeListType; - - //! \brief save typing - using MavisType = fusion::MavisType; - - //! \brief ctor with boost program_option support - TestBench(int, char**); - - //! \brief hold functor proxies used by the tb - struct cbProxy; - - //! \brief run all tests - bool run(); - - //! \brief sanity check compilation of ctors - bool fusionCtorCompileTest(bool debug = false); - - //! \brief basic find fusiongroup, match to input, and transform - bool fusionSearchTest(bool debug = false); - - //! \brief sanity check the way mavis and isa files supplied are used - bool basicMavisTest(bool debug = false); - - //! \brief check constraints and perform simple transform - bool basicConstraintsTest(); - - //! \brief test using alternatives to MachineInfo and FieldExtractor - bool fusionGroupAltCtorTest(); - - //! \brief test choices in specifying FusionGroupCfg - bool fusionGroupCfgCtorTest(); - - //! \brief unit test for class::FusionContext - bool fusionContextTest(bool debug = false); - - //! \brief unit test for class::RadixTrie - bool radixTrieTest(bool debug = false); - - //! \brief catch all for start up checks - bool sanityTest(bool debug = false); - - // ------------------------------------------------------------- - // field extractor method tests and support, testfieldextractor.cpp - // ------------------------------------------------------------- - //! \brief top level extractor test runner - bool fieldExtractorTests(bool debug = false); - - //! \brief create an inst from opcode, catch conversion errors - FieldExtractor::InstPtrType makeInst(MavisType &, uint32_t); - - //! \brief helper for testing field values - bool testFieldValue(uint32_t, std::string, uint32_t act, uint32_t exp); - - //! \brief transform funcs - static bool f1_constraints(FusionGroupType &, InstPtrListType &, InstPtrListType &); - - //! \brief assign to InstPtrListType from opcodes - void assign(InstPtrListType &, std::vector &, const FileNameListType &); - //! \brief info debug function - void info(InstUidListType &, InstUidListType &, InstPtrListType &); - - //! \brief support golden reference hashes - void generateExpectHashes(std::unordered_map &, - const FusionType::FusionGroupCfgListType &); - - //! \brief duplicate of hash function found in fusion group - //! - //! duplicated to support debug - fusion::HashType jenkinsOneAtATime(const std::vector &); - - //! \brief common isa files to separate from the cmd line versions - static const std::vector stdIsaFiles; - - //! \brief extra messages - bool verbose{false}; - - //! \brief zoo.F1 example fusion group - //! - //! This is from the fusion group zoo, F1 has three variants. There are - //! three forms for each, opcode, uid, and asm text. I'm trying out - //! various methods for a user to express a fusion group when not using - //! the DSL. Note all of these will be needed. - //! @{ - static InstUidListType uf1, uf1_1, uf1_2, uf1_3; - static OpcodeListType of1, of1_1, of1_2, of1_3; - //! @} - - //! \brief zoo.F2 example fusion group - //! @{ - static InstUidListType uf2; - static OpcodeListType of2; - //! @} - - //! \brief zoo.F3 example fusion group - //! @{ - static InstUidListType uf3; - static OpcodeListType of3; - //! }@ - - //! \brief zoo.F4 example fusion group - //! @{ - static InstUidListType uf4; - static OpcodeListType of4; - //! }@ - - //! \brief zoo.F5 example fusion group and three variants - //! @{ - static InstUidListType uf5, uf5_1, uf5_2, uf5_3; - static OpcodeListType of5, of5_1, of5_2, of5_3; - //! }@ -}; - -// --------------------------------------------------------------------- -//! \brief call back proxies used in the unit test(s) -//! -//! There is a callback for each fusion group test case f1, f1.1, etc -// --------------------------------------------------------------------- -struct TestBench::cbProxy -{ - //! \brief ... - static bool uf1_func(FusionGroupType &, InstPtrListType &, InstPtrListType &) - { - msg->imsg("uf1_func called"); - return true; - } - - //! \brief ... - static bool uf1_1_func(FusionGroupType &, InstPtrListType &, InstPtrListType &) - { - msg->imsg("uf1_1_func called"); - return true; - } - - //! \brief ... - static bool uf1_2_func(FusionGroupType &, InstPtrListType &, InstPtrListType &) - { - msg->imsg("uf1_2_func called"); - return true; - } - - //! \brief ... - static bool uf1_3_func(FusionGroupType &, InstPtrListType &, InstPtrListType &) - { - msg->imsg("uf1_3_func called"); - return true; - } - - //! \brief ... - static bool uf2_func(FusionGroupType &, InstPtrListType &, InstPtrListType &) - { - msg->imsg("uf2_func called"); - return true; - } - - //! \brief ... - static bool uf3_func(FusionGroupType &, InstPtrListType &, InstPtrListType &) - { - msg->imsg("uf3_func called"); - return true; - } - - //! \brief ... - static bool uf4_func(FusionGroupType &, InstPtrListType &, InstPtrListType &) - { - msg->imsg("uf4_func called"); - return true; - } - - //! \brief ... - static bool uf5_func(FusionGroupType &, InstPtrListType &, InstPtrListType &) - { - msg->imsg("uf5_func called"); - return true; - } - - //! \brief ... - static bool uf5_1_func(FusionGroupType &, InstPtrListType &, InstPtrListType &) - { - msg->imsg("uf5_1_func called"); - return true; - } - - //! \brief ... - static bool uf5_2_func(FusionGroupType &, InstPtrListType &, InstPtrListType &) - { - msg->imsg("uf5_2_func called"); - return true; - } - - //! \brief ... - static bool uf5_3_func(FusionGroupType &, InstPtrListType &, InstPtrListType &) - { - msg->imsg("uf5_3_func called"); - return true; - } -}; diff --git a/fusion/test/TestData.cpp b/fusion/test/TestData.cpp deleted file mode 100644 index 951c8b8e..00000000 --- a/fusion/test/TestData.cpp +++ /dev/null @@ -1,125 +0,0 @@ -// HEADER PLACEHOLDER -// contact Jeff Nye, jeffnye-gh, Condor Computing Corp. -// -#include "FieldExtractor.hpp" -#include "Fusion.hpp" -#include "FusionContext.hpp" -#include "FusionGroup.hpp" -#include "FusionTypes.hpp" -#include "MachineInfo.hpp" -#include "Msg.hpp" -#include "Options.hpp" -#include "RadixTrie.hpp" -#include "TestBench.hpp" - -#include - -#include -#include -#include -using namespace std; -// -------------------------------------------------------------------- -// Example -// -------------------------------------------------------------------- -// TestBench::OpcodeListType TestBench::of1 = { -// // INDEX DISASM FORM FIELDS UID -// 0x76e9, // 0 c.lui x13, -6 CI-TYPE RD IMM 0xb -// 0x0685, // 1 c.addi x13,0x1 I-TYPE RD RS1 IMM 0xd -// 0x8d35, // 2 c.xor x10,x13 R-TYPE RD RS1 RS2 0x1c -// 0x1542, // 3 c.slli x10,48 I-TYPE RD RS1 IMM 0xf -// 0x9141 // 4 c.srli x10,48 I-TYPE RD RS1 IMM 0x13 -// }; -// -// 0 U RD = G1 IMM = C1 -// 1 I RD = G1 RS1 = G1 IMM = C2 -// 2 R RD = G1 RS1 = G2 RD2 = G1 -// 3 I RD = G2 RS1 = G2 IMM = C3 -// 4 I RD = G2 RS1 = G2 IMM = C3 -// ---------------------------------------------------------------------- -TestBench::InstUidListType TestBench::uf1 = {0xb, 0xd, 0x1c, 0xf, 0x13}; -TestBench::OpcodeListType TestBench::of1 = { - // INDEX DISASM FORM FIELDS UID - 0x76e9, // 0 c.lui x13, -6 CI-TYPE RD IMM 0xb - 0x0685, // 1 c.addi x13,0x1 I-TYPE RD RS1 IMM 0xd - 0x8d35, // 2 c.xor x10,x13 R-TYPE RD RS1 RS2 0x1c - 0x1542, // 3 c.slli x10,48 I-TYPE RD RS1 IMM 0xf - 0x9141 // 4 c.srli x10,48 I-TYPE RD RS1 IMM 0x13 -}; -// fusion::HashType TestBench::hf1 = { 0xb,0xd,0x1c,0xf,0x13 }; -// -------------------------------------------------------------------- -// Fragment of of1 -// -------------------------------------------------------------------- -TestBench::InstUidListType TestBench::uf1_1 = {0xd, 0x1c, 0xf, 0x13}; -TestBench::OpcodeListType TestBench::of1_1 = { - 0x0685, // "c.addi x13,0x1", 0xd - 0x8d35, // "c.xor x10,x13", 0x1c - 0x1542, // "c.slli x10,48", 0xf - 0x9141 // "c.srli x10,48" 0x13 -}; -//// -------------------------------------------------------------------- -TestBench::InstUidListType TestBench::uf1_2 = {0x1c, 0xf, 0x13}; -TestBench::OpcodeListType TestBench::of1_2 = { - 0x8d35, // "c.xor x10,x13", 0xf - 0x1542, // "c.slli x10,48", 0xf - 0x9141 // "c.srli x10,48" 0x13 -}; -// -------------------------------------------------------------------- -TestBench::InstUidListType TestBench::uf1_3 = {0xf, 0x13}; -TestBench::OpcodeListType TestBench::of1_3 = { - 0x1542, // "c.slli x10,48", 0xf - 0x9141 // "c.srli x10,48" 0x13 -}; -// -------------------------------------------------------------------- -// -------------------------------------------------------------------- -TestBench::InstUidListType TestBench::uf2 = {0xd, 0x34}; -TestBench::OpcodeListType TestBench::of2 = { - 0x7159, // "c.addi16sp -112", 0xd - 0xf0a2 // "c.fswsp f8, 96" 0x34 -}; -// -------------------------------------------------------------------- -// -------------------------------------------------------------------- -TestBench::InstUidListType TestBench::uf3 = {0x17, 0x2d}; -TestBench::OpcodeListType TestBench::of3 = { - 0x843a, // "c.mv x8, x14", 0x17 - 0x6018 // "c.flw f14, 0(x8)" 0x2d -}; -// -------------------------------------------------------------------- -// -------------------------------------------------------------------- -TestBench::InstUidListType TestBench::uf4 = {0xf, 0x13}; -TestBench::OpcodeListType TestBench::of4 = { - 0xe014, // "c.fsw f13, 0(x8)", 0xf - 0x86a2 // "c.mv x13, x8"; 0x13 -}; -// -------------------------------------------------------------------- -// -------------------------------------------------------------------- -TestBench::InstUidListType TestBench::uf5 = {0x17, 0x2d, 0x34, 0x17, 0x4}; -TestBench::OpcodeListType TestBench::of5 = { - 0x843a, // "c.mv x8, x14", 0x17 - 0x6018, // "c.flw f14, 0(x8)", 0x2d - 0xe014, // "c.fsw f13, 0(x8)", 0x34 - 0x86a2, // "c.mv x13, x8", 0x17 - 0xff65 // "c.bnez x14, -8" 0x4 -}; -// -------------------------------------------------------------------- -TestBench::InstUidListType TestBench::uf5_1 = {0x17, 0x2d, 0x34, 0x17}; -TestBench::OpcodeListType TestBench::of5_1 = { - 0x843a, // "c.mv x8, x14", 0x17 - 0x6018, // "c.flw f14, 0(x8)", 0x2d - 0xe014, // "c.fsw f13, 0(x8)", 0x34 - 0x86a2 // "c.mv x13, x8" 0x17 -}; -// -------------------------------------------------------------------- -TestBench::InstUidListType TestBench::uf5_2 = {0x2d, 0x34, 0x17, 0x4}; -TestBench::OpcodeListType TestBench::of5_2 = { - 0x6018, // "c.flw f14, 0(x8)", 0x2d - 0xe014, // "c.fsw f13, 0(x8)", 0x34 - 0x86a2, // "c.mv x13, x8", 0x17 - 0xff65, // "c.bnez x14, -8" 0x4 -}; -// -------------------------------------------------------------------- -TestBench::InstUidListType TestBench::uf5_3 = {0x2d, 0x34, 0x17}; -TestBench::OpcodeListType TestBench::of5_3 = { - 0x6018, // "c.flw f14, 0(x8)", 0x2d - 0xe014, // "c.fsw f13, 0(x8)", 0x34 - 0x86a2 // "c.mv x13, x8" 0x17 -}; diff --git a/fusion/test/TestFieldExtractor.cpp b/fusion/test/TestFieldExtractor.cpp deleted file mode 100644 index 5dff01eb..00000000 --- a/fusion/test/TestFieldExtractor.cpp +++ /dev/null @@ -1,120 +0,0 @@ -// HEADER PLACEHOLDER -// contact Jeff Nye, jeffnye-gh, Condor Computing Corp. -// -#include "Msg.hpp" -#include "Options.hpp" -#include "TestBench.hpp" -#include -#include -using namespace std; - -// -------------------------------------------------------------------- -// The intent is at least one test for the top level methods overall. -// -// Some method tests are covered as part of the Fusion Group and transform -// tests. SField and ImmField tests are less used elsewhere. -// These outliers are tested here. -// -------------------------------------------------------------------- -bool TestBench::fieldExtractorTests(bool debug) -{ - FieldExtractor fe; - using InstPtrType = FieldExtractor::InstPtrType; - - if (verbose) - msg->imsg("fieldExtractorTests BEGIN"); - - bool ok = true; - MavisType mavis(opts->isa_files, {}); - - // add x1,x2,x3 - InstPtrType inst_1 = makeInst(mavis, 0x003100b3); - - if (inst_1 == nullptr) - ok = false; - - using FN = FieldExtractor::FieldName; - using SFN = FieldExtractor::SFieldName; - - // Test for uint32_t getField(InstPtrType,FieldName) const - uint32_t rd_inst_1 = fe.getField(inst_1, FN::RD); - uint32_t rs1_inst_1 = fe.getField(inst_1, FN::RS1); - uint32_t rs2_inst_1 = fe.getField(inst_1, FN::RS2); - - if (!testFieldValue(0, "RD", rd_inst_1, 0x1)) - ok = false; - if (!testFieldValue(1, "RS1", rs1_inst_1, 0x2)) - ok = false; - if (!testFieldValue(2, "RS2", rs2_inst_1, 0x3)) - ok = false; - - bool isDest = false; - if (!fe.checkInstHasField(inst_1, FN::RD, isDest)) - { - msg->emsg("checkInstHasField() failed to detect RD"); - ok = false; - } - - if (!isDest) - { - msg->emsg("ID=3: checkInstHasField() failed to set isDest"); - ok = false; - } - - // Test for uint32_t getSField(InstPtrType,SFieldName) const - // [ funct7 | rs2 | rs1 | rm | rd | opcode ] - // 3322 2222 2222 1111 1111 11 - // 1098 7654 3210 9876 5432 1098 7654 3210 - // 0111 0010 1010 0111 1111 0101 0100 0011 - // RM should be 111 -> 0x7 - InstPtrType inst_2 = makeInst(mavis, 0x72a7f543); - if (inst_2 == nullptr) - ok = false; - uint32_t rm_inst_2 = fe.getSField(inst_2, SFN::RM); - if (!testFieldValue(4, "RM", rm_inst_2, 0x7)) - ok = false; - - // Test for uint32_t getImmField(InstPtrType inst) const - - if (!ok) - msg->emsg("fieldExtractor_tests FAILED"); - if (verbose) - msg->imsg("fieldExtractor_tests END"); - return ok; -} - -// -------------------------------------------------------------------- -// -------------------------------------------------------------------- -FieldExtractor::InstPtrType TestBench::makeInst(MavisType & m, uint32_t opc) -{ - FieldExtractor::InstPtrType inst; - - try - { - inst = m.makeInst(opc, 0); - } - catch (const std::exception &) - { - if (!inst) - { - std::ostringstream ss; - ss << "0x" << std::setw(8) << std::setfill('0') << std::hex << opc; - msg->emsg("Mavis could not create instruction from " + ss.str()); - return nullptr; - } - } - - return inst; -} - -// -------------------------------------------------------------------- -// -------------------------------------------------------------------- -bool TestBench::testFieldValue(uint32_t id, string name, uint32_t act, uint32_t exp) -{ - if (act != exp) - { - msg->emsg("ID:" + ::to_string(id) + ":FIELD:" + name + ": value mismatch"); - return false; - } - - return true; -} diff --git a/fusion/test/json/isa_rv64c.json b/fusion/test/json/isa_rv64c.json deleted file mode 100644 index 76e7a6f2..00000000 --- a/fusion/test/json/isa_rv64c.json +++ /dev/null @@ -1,293 +0,0 @@ -[ - { - "mnemonic" : "c.addi4spn", - "tags" : ["c"], - "expand" : "addi", - "form" : "C0", - "ignore" : ["func2A"], - "xform" : "CIW_sp", - "stencil" : "0x0" - }, - { - "mnemonic" : "c.lw", - "tags" : ["c"], - "expand" : "lw", - "form" : "C0", - "ignore" : ["func2A"], - "xform" : "C0_load_word", - "stencil" : "0x4000" - }, - { - "mnemonic" : "c.ld", - "tags" : ["c"], - "expand" : "ld", - "form" : "C0", - "ignore" : ["func2A"], - "xform" : "C0_load_double", - "stencil" : "0x6000" - }, - { - "mnemonic" : "c.sw", - "tags" : ["c"], - "expand" : "sw", - "form" : "C0", - "ignore" : ["func2A"], - "xform" : "C0_store_word", - "stencil" : "0xc000" - }, - { - "mnemonic" : "c.sd", - "tags" : ["c"], - "expand" : "sd", - "form" : "C0", - "ignore" : ["func2A"], - "xform" : "C0_store_double", - "stencil" : "0xe000" - }, - { - "mnemonic" : "c.addi", - "tags" : ["c"], - "expand" : "addi", - "form" : "C1", - "ignore" : ["func2", "func1", "func2b"], - "xform" : "CI_addi", - "stencil" : "0x1" - }, - { - "mnemonic" : "c.nop", - "tags" : ["c"], - "expand" : "nop", - "form" : "C1", - "ignore" : ["func1", "func2b"], - "fixed" : [ "rs1" ], - "xform" : "CI_addi", - "stencil" : "0x1" - }, - { - "mnemonic" : "c.addi16sp", - "tags" : ["c"], - "expand" : "addi", - "form" : "C1", - "ignore" : ["func1", "func2b"], - "fixed" : [ "rs1" ], - "xform" : "CI_sp", - "stencil" : "0x6101" - }, - { - "mnemonic" : "c.jr", - "tags" : ["c"], - "expand" : "jalr", - "form" : "C2", - "fixed" : ["rs2"], - "xform" : "CJR", - "stencil" : "0x8002" - }, - { - "mnemonic" : "c.addiw", - "tags" : ["c"], - "expand" : "addiw", - "form" : "C1", - "ignore" : ["func2", "func1", "func2b"], - "xform" : "CI_addiw", - "stencil" : "0x2001" - }, - { - "mnemonic" : "c.jalr", - "tags" : ["c"], - "expand" : "jalr", - "form" : "C2", - "fixed" : ["rs2"], - "xform" : "CJALR", - "stencil" : "0x9002" - }, - { - "mnemonic" : "c.li", - "tags" : ["c"], - "expand" : "li", - "form" : "C1", - "ignore" : ["func2", "func1", "func2b"], - "xform" : "CI_rD_only", - "stencil" : "0x4001" - }, - { - "mnemonic" : "c.lui", - "tags" : ["c"], - "expand" : "lui", - "form" : "C1", - "ignore" : ["func2", "func1", "func2b"], - "xform" : "CI_rD_shifted", - "stencil" : "0x6001" - }, - { - "mnemonic" : "c.srli", - "tags" : ["c"], - "expand" : "srli", - "form" : "C1", - "ignore" : ["func1", "func2b"], - "xform" : "CIX", - "stencil" : "0x8001" - }, - { - "mnemonic" : "c.srai", - "tags" : ["c"], - "expand" : "srai", - "form" : "C1", - "ignore" : ["func1", "func2b"], - "xform" : "CIX", - "stencil" : "0x8401" - }, - { - "mnemonic" : "c.andi", - "tags" : ["c"], - "expand" : "andi", - "form" : "C1", - "ignore" : ["func1", "func2b"], - "xform" : "CIX_andi", - "stencil" : "0x8801" - }, - { - "mnemonic" : "c.sub", - "tags" : ["c"], - "expand" : "sub", - "form" : "C1", - "xform" : "CA", - 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"form" : "Rfloat", - "fixed" : [ "rm" ], - "stencil" : "0xa0000053", - "s-oper" : ["rs1","rs2"], - "w-oper" : ["rd"], - "type" : ["float", "compare"] - }, - { - "mnemonic" : "flt.s", - "form" : "Rfloat", - "fixed" : [ "rm" ], - "stencil" : "0xa0001053", - "s-oper" : ["rs1","rs2"], - "w-oper" : ["rd"], - "type" : ["float", "compare"] - }, - { - "mnemonic" : "feq.s", - "form" : "Rfloat", - "fixed" : [ "rm" ], - "stencil" : "0xa0002053", - "s-oper" : ["rs1","rs2"], - "w-oper" : ["rd"], - "type" : ["float", "compare"] - }, - { - "mnemonic" : "fle.d", - "form" : "Rfloat", - "fixed" : [ "rm" ], - "stencil" : "0xa2000053", - "d-oper" : ["rs1","rs2"], - "w-oper" : ["rd"], - "type" : ["float", "compare"] - }, - { - "mnemonic" : "flt.d", - "form" : "Rfloat", - "fixed" : [ "rm" ], - "stencil" : "0xa2001053", - "d-oper" : ["rs1","rs2"], - "w-oper" : ["rd"], - "type" : ["float", "compare"] - }, - { - "mnemonic" : "feq.d", - "form" : "Rfloat", - "fixed" : [ "rm" ], - "stencil" : "0xa2002053", - "d-oper" : ["rs1","rs2"], - "w-oper" : ["rd"], - "type" : ["float", "compare"] - }, - { - "mnemonic" : "fcvt.w.s", - "form" : "Rfloat", - "fixed" : [ "rs2" ], - "stencil" : "0xc0000053", - "s-oper" : ["rs1"], - "w-oper" : ["rd"], - "type" : ["float", "convert"] - }, - { - "mnemonic" : "fcvt.wu.s", - "form" : "Rfloat", - "fixed" : [ "rs2" ], - "stencil" : "0xc0100053", - "s-oper" : ["rs1"], - "w-oper" : ["rd"], - "type" : ["float", "convert"] - }, - { - "mnemonic" : "fcvt.l.s", - "form" : "Rfloat", - "fixed" : [ "rs2" ], - "stencil" : "0xc0200053", - "s-oper" : ["rs1"], - "l-oper" : ["rd"], - "type" : ["float", "convert"] - }, - { - "mnemonic" : "fcvt.lu.s", - "form" : "Rfloat", - "fixed" : [ "rs2" ], - "stencil" : "0xc0300053", - "s-oper" : ["rs1"], - "l-oper" : ["rd"], - "type" : ["float", "convert"] - }, - { - "mnemonic" : "fmv.x.w", - "form" : "Rfloat", - "fixed" : [ "rm", "rs2" ], - "stencil" : "0xe0000053", - "s-oper" : ["rs1"], - "l-oper" : ["rd"], - "type" : ["float", "move"] - }, - { - "mnemonic" : "fclass.s", - "form" : "Rfloat", - "fixed" : [ "rm", "rs2" ], - "stencil" : "0xe0001053", - "s-oper" : ["rs1"], - "l-oper" : ["rd"], - "type" : ["float", "classify"] - }, - { - "mnemonic" : "fcvt.w.d", - "form" : "Rfloat", - "fixed" : [ "rs2" ], - "stencil" : "0xc2000053", - "d-oper" : ["rs1"], - "w-oper" : ["rd"], - "type" : ["float", "convert"] - }, - { - "mnemonic" : "fcvt.wu.d", - "form" : "Rfloat", - "fixed" : [ "rs2" ], - "stencil" : "0xc2100053", - "d-oper" : ["rs1"], - "w-oper" : ["rd"], - "type" : ["float", "convert"] - }, - { - "mnemonic" : "fcvt.l.d", - "form" : "Rfloat", - "fixed" : [ "rs2" ], - "stencil" : "0xc2200053", - "d-oper" : ["rs1"], - "l-oper" : ["rd"], - "type" : ["float", "convert"] - }, - { - "mnemonic" : "fcvt.lu.d", - "form" : "Rfloat", - "fixed" : [ "rs2" ], - "stencil" : "0xc2300053", - "d-oper" : ["rs1"], - "l-oper" : ["rd"], - "type" : ["float", "convert"] - }, - { - "mnemonic" : "fmv.x.d", - "form" : "Rfloat", - "fixed" : [ "rm", "rs2" ], - "stencil" : "0xe2000053", - "d-oper" : ["rs1"], - "l-oper" : ["rd"], - "type" : ["float", "move"] - }, - { - "mnemonic" : "fclass.d", - "form" : "Rfloat", - "fixed" : [ "rm", "rs2" ], - "stencil" : "0xe2001053", - "d-oper" : ["rs1"], - "l-oper" : ["rd"], - "type" : ["float", "classify"] - }, - { - "mnemonic" : "fcvt.s.w", - "form" : "Rfloat", - "fixed" : [ "rs2" ], - "stencil" : "0xd0000053", - "w-oper" : ["rs1"], - "s-oper" : ["rd"], - "type" : ["float", "convert"] - }, - { - "mnemonic" : "fcvt.s.wu", - "form" : "Rfloat", - "fixed" : [ "rs2" ], - "stencil" : "0xd0100053", - "w-oper" : ["rs1"], - "s-oper" : ["rd"], - "type" : ["float", "convert"] - }, - { - "mnemonic" : "fcvt.s.l", - "form" : "Rfloat", - "fixed" : [ "rs2" ], - "stencil" : "0xd0200053", - "l-oper" : ["rs1"], - "s-oper" : ["rd"], - "type" : ["float", "convert"] - }, - { - "mnemonic" : "fcvt.s.lu", - "form" : "Rfloat", - "fixed" : [ "rs2" ], - "stencil" : "0xd0300053", - "l-oper" : ["rs1"], - "s-oper" : ["rd"], - "type" : ["float", "convert"] - }, - { - "mnemonic" : "fmv.w.x", - "form" : "Rfloat", - "fixed" : [ "rm", "rs2" ], - "stencil" : "0xf0000053", - "l-oper" : ["rs1"], - "s-oper" : ["rd"], - "type" : ["float", "move"] - }, - { - "mnemonic" : "fcvt.d.w", - "form" : "Rfloat", - "fixed" : [ "rs2" ], - "stencil" : "0xd2000053", - "w-oper" : ["rs1"], - "d-oper" : ["rd"], - "type" : ["float", "convert"] - }, - { - "mnemonic" : "fcvt.d.wu", - "form" : "Rfloat", - "fixed" : [ "rs2" ], - "stencil" : "0xd2100053", - "w-oper" : ["rs1"], - "d-oper" : ["rd"], - "type" : ["float", "convert"] - }, - { - "mnemonic" : "fcvt.d.l", - "form" : "Rfloat", - "fixed" : [ "rs2" ], - "stencil" : "0xd2200053", - "l-oper" : ["rs1"], - "d-oper" : ["rd"], - "type" : ["float", "convert"] - }, - { - "mnemonic" : "fcvt.d.lu", - "form" : "Rfloat", - "fixed" : [ "rs2" ], - "stencil" : "0xd2300053", - "l-oper" : ["rs1"], - "d-oper" : ["rd"], - "type" : ["float", "convert"] - }, - { - "mnemonic" : "fmv.d.x", - "form" : "Rfloat", - "fixed" : [ "rm", "rs2" ], - "stencil" : "0xf2000053", - "l-oper" : ["rs1"], - "d-oper" : ["rd"], - "type" : ["float", "move"] - }, - { - "mnemonic" : "flw", - "form" : "VF_mem", - "xform" : "I_load", - "stencil" : "0x2007", - "ignore" : ["mewop"], - "type" : ["float", "load"], - "l-oper" : ["rs1"], - "s-oper" : ["rd"], - "data" : 32 - }, - { - "mnemonic" : "fld", - "form" : "VF_mem", - "xform" : "I_load", - "stencil" : "0x3007", - "ignore" : ["mewop"], - "type" : ["float", "load"], - "l-oper" : ["rs1"], - "d-oper" : ["rd"], - "data" : 64 - }, - { - "mnemonic" : "fsw", - "form" : "VF_mem", - "xform" : "S", - "stencil" : "0x2027", - "ignore" : ["mewop"], - "type" : ["float", "store"], - "l-oper" : ["rs1"], - "s-oper" : ["rs2"], - "data" : 32 - }, - { - "mnemonic" : "fsd", - "form" : "VF_mem", - "xform" : "S", - "stencil" : "0x3027", - "ignore" : ["mewop"], - "type" : ["float", "store"], - "l-oper" : ["rs1"], - "d-oper" : ["rs2"], - "data" : 64 - }, - { - "mnemonic" : "fmadd.s", - "form" : "R4", - "stencil" : "0x43", - "type" : ["float", "mac"], - "s-oper" : "all" - }, - { - "mnemonic" : "fmsub.s", - "form" : "R4", - "stencil" : "0x47", - "type" : ["float", "mac"], - "s-oper" : "all" - }, - { - "mnemonic" : "fnmsub.s", - "form" : "R4", - "stencil" : "0x4b", - "type" : ["float", "mac"], - "s-oper" : "all" - }, - { - "mnemonic" : "fnmadd.s", - "form" : "R4", - "stencil" : "0x4f", - "type" : ["float", "mac"], - "s-oper" : "all" - }, - { - "mnemonic" : "fmadd.d", - "form" : "R4", - "stencil" : "0x2000043", - "type" : ["float", "mac"], - "d-oper" : "all" - }, - { - "mnemonic" : "fmsub.d", - "form" : "R4", - "stencil" : "0x2000047", - "type" : ["float", "mac"], - "d-oper" : "all" - }, - { - "mnemonic" : "fnmsub.d", - "form" : "R4", - "stencil" : "0x200004b", - "type" : ["float", "mac"], - "d-oper" : "all" - }, - { - "mnemonic" : "fnmadd.d", - "form" : "R4", - "stencil" : "0x200004f", - "type" : ["float", "mac"], - "d-oper" : "all" - } -] diff --git a/fusion/test/main.cpp b/fusion/test/main.cpp deleted file mode 100644 index 6a3851d9..00000000 --- a/fusion/test/main.cpp +++ /dev/null @@ -1,40 +0,0 @@ -// HEADER PLACEHOLDER -// contact Jeff Nye, jeffnye-gh, Condor Computing Corp. -// -#include "TestBench.hpp" -#include "Msg.hpp" -#include "Options.hpp" - -#include -#include -using namespace std; - -Options* Options::instance = 0; -std::shared_ptr opts(Options::getInstance()); - -Msg* Msg::instance = 0; -std::unique_ptr msg(Msg::getInstance()); - -// ------------------------------------------------------------------------ -int main(int ac, char** av) -{ - TestBench tb(ac, av); - ofstream out("PASSFAIL"); - if (!out.is_open()) - { - msg->emsg("Could not open pass/fail status file"); - return 1; - } - - msg->imsg("Test run begin"); - bool ok = tb.run(); - if (!ok) - { - out << "FAIL" << endl; - msg->emsg("Test run end FAIL"); - return 1; - } - out << "PASS" << endl; - msg->imsg("Test run end PASS"); - return 0; -} diff --git a/mavis b/mavis index ba3d7e41..fe4a5570 160000 --- a/mavis +++ b/mavis @@ -1 +1 @@ -Subproject commit ba3d7e4141cd1dbce03cf7eb5481179836f2ac0f +Subproject commit fe4a557091d5322ded4e090f10fca1e9e0b1704a diff --git a/sim/OlympiaAllocators.hpp b/sim/OlympiaAllocators.hpp index 5f408973..38b05281 100644 --- a/sim/OlympiaAllocators.hpp +++ b/sim/OlympiaAllocators.hpp @@ -13,6 +13,7 @@ #include "Inst.hpp" #include "LoadStoreInstInfo.hpp" #include "MemoryAccessInfo.hpp" +#include "MSHREntryInfo.hpp" namespace olympia { @@ -54,8 +55,9 @@ namespace olympia InstArchInfoAllocator inst_arch_info_allocator{3000, 2500}; // For LSU/MSS - LoadStoreInstInfoAllocator load_store_info_allocator{128, 80}; - MemoryAccessInfoAllocator memory_access_allocator {128, 80}; + LoadStoreInstInfoAllocator load_store_info_allocator{128, 80}; + MemoryAccessInfoAllocator memory_access_allocator {128, 80}; + MSHREntryInfoAllocator mshr_entry_allocator {300, 150}; }; } diff --git a/stf_lib b/stf_lib index 69d48b1b..83bb798e 160000 --- a/stf_lib +++ b/stf_lib @@ -1 +1 @@ -Subproject commit 69d48b1bab14a410c859aa3591b4eb175323ec98 +Subproject commit 83bb798e0e6b009b99fc510dca7f3d8f740d0445 diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt index 4eb15341..41d1472b 100644 --- a/test/CMakeLists.txt +++ b/test/CMakeLists.txt @@ -33,3 +33,7 @@ add_subdirectory(core/rename) add_subdirectory(core/lsu) add_subdirectory(core/issue_queue) add_subdirectory(core/icache) +add_subdirectory(core/branch_pred) +add_subdirectory(core/dcache) +add_subdirectory(core/vector) +add_subdirectory(fusion) diff --git a/test/core/Testing/Temporary/LastTest.log b/test/core/Testing/Temporary/LastTest.log new file mode 100644 index 00000000..8e504756 --- /dev/null +++ b/test/core/Testing/Temporary/LastTest.log @@ -0,0 +1,3 @@ +Start testing: Sep 23 23:54 IST +---------------------------------------------------------- +End testing: Sep 23 23:54 IST diff --git a/test/core/branch_pred/BranchPred_test.cpp b/test/core/branch_pred/BranchPred_test.cpp new file mode 100644 index 00000000..b37ffe15 --- /dev/null +++ b/test/core/branch_pred/BranchPred_test.cpp @@ -0,0 +1,43 @@ +#include "SimpleBranchPred.hpp" +#include "sparta/utils/SpartaTester.hpp" + +TEST_INIT + +void runTest(int argc, char **argv) +{ + olympia::BranchPredictor::SimpleBranchPredictor predictor(4); //specify max num insts to fetch + + olympia::BranchPredictor::DefaultInput input; + input.fetch_PC = 0x0; + + // BTB miss + olympia::BranchPredictor::DefaultPrediction prediction = predictor.getPrediction(input); + + EXPECT_EQUAL(prediction.branch_idx, 4); + EXPECT_EQUAL(prediction.predicted_PC, 16); + + // there was a taken branch at the 3rd instruction from fetchPC, with target 0x100 + olympia::BranchPredictor::DefaultUpdate update; + update.fetch_PC = 0x0; + update.branch_idx = 2; + update.corrected_PC = 0x100; + update.actually_taken = true; + predictor.updatePredictor(update); + + // try the same input with fetchPC 0x0 again + prediction = predictor.getPrediction(input); + + EXPECT_EQUAL(prediction.branch_idx, 2); + EXPECT_EQUAL(prediction.predicted_PC, 0x100); + + // TODO: add more tests + +} + +int main(int argc, char **argv) +{ + runTest(argc, argv); + + REPORT_ERROR; + return (int)ERROR_CODE; +} diff --git a/test/core/branch_pred/CMakeLists.txt b/test/core/branch_pred/CMakeLists.txt new file mode 100644 index 00000000..a70c99c2 --- /dev/null +++ b/test/core/branch_pred/CMakeLists.txt @@ -0,0 +1,6 @@ +project(BranchPred_test) + +add_executable(BranchPred_test BranchPred_test.cpp) +target_link_libraries(BranchPred_test core common_test SPARTA::sparta) + +sparta_named_test(BranchPred_test_Run BranchPred_test) diff --git a/test/core/dcache/CMakeLists.txt b/test/core/dcache/CMakeLists.txt new file mode 100644 index 00000000..a8bce09d --- /dev/null +++ b/test/core/dcache/CMakeLists.txt @@ -0,0 +1,12 @@ +project(Dcache_test) + +add_executable(Dcache_test Dcache_test.cpp) + +target_link_libraries(Dcache_test core common_test mss ${STF_LINK_LIBS} SPARTA::sparta) +file(CREATE_LINK ${SIM_BASE}/mavis/json ${CMAKE_CURRENT_BINARY_DIR}/mavis_isa_files SYMBOLIC) +file(CREATE_LINK ${SIM_BASE}/arches ${CMAKE_CURRENT_BINARY_DIR}/arches SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/test_arches ${CMAKE_CURRENT_BINARY_DIR}/test_arches SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/expected_output ${CMAKE_CURRENT_BINARY_DIR}/expected_output SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/next_lvl_cache_refill.json ${CMAKE_CURRENT_BINARY_DIR}/next_lvl_cache_refill.json SYMBOLIC) + +sparta_named_test(Dcache_test_arbitrate Dcache_test arbitrate.out -c test_arches/1_src_Dcache.yaml --input-file next_lvl_cache_refill.json) \ No newline at end of file diff --git a/test/core/dcache/Dcache_test.cpp b/test/core/dcache/Dcache_test.cpp new file mode 100644 index 00000000..77a32d76 --- /dev/null +++ b/test/core/dcache/Dcache_test.cpp @@ -0,0 +1,151 @@ + +#include "DCache.hpp" +#include +#include +#include "sparta/utils/SpartaTester.hpp" +#include "test/core/dcache/NextLvlSourceSinkUnit.hpp" +#include "test/core/dcache/SourceUnit.hpp" +#include "sparta/utils/LogUtils.hpp" +#include "OlympiaAllocators.hpp" + +class DCacheSim : public sparta::app::Simulation +{ + public: + DCacheSim(sparta::Scheduler* sched, const std::string & mavis_isa_files, + const std::string & mavis_uarch_files, const std::string & output_file, + const std::string & input_file) : + sparta::app::Simulation("DCacheSim", sched), + input_file_(input_file), + test_tap_(getRoot(), "info", output_file) + { + } + + ~DCacheSim() { getRoot()->enterTeardown(); } + + void runRaw(uint64_t run_time) override final + { + (void)run_time; + + sparta::app::Simulation::runRaw(run_time); + } + + private: + void buildTree_() override + { + auto rtn = getRoot(); + + allocators_tn_.reset(new olympia::OlympiaAllocators(rtn)); + + sparta::ResourceTreeNode* mavis = new sparta::ResourceTreeNode( + rtn, olympia::MavisUnit::name, sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, "Mavis Unit", &mavis_fact); + tns_to_delete_.emplace_back(mavis); + + // Create a Source Units that represents DCache and ICache + sparta::ResourceTreeNode* Test_Lsu = + new sparta::ResourceTreeNode(rtn, "lsu", sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, "lsu", &lsu_fact); + + Test_Lsu->getParameterSet()->getParameter("input_file")->setValueFromString(input_file_); + tns_to_delete_.emplace_back(Test_Lsu); + + sparta::ResourceTreeNode* Test_DCache = + new sparta::ResourceTreeNode(rtn, "dcache", sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, "dcache", &dcache_fact); + tns_to_delete_.emplace_back(Test_DCache); + + sparta::ResourceTreeNode* Test_Next_Lvl = new sparta::ResourceTreeNode( + rtn, "next_lvl", sparta::TreeNode::GROUP_NAME_NONE, sparta::TreeNode::GROUP_IDX_NONE, + "next_lvl", &next_lvl_fact); + tns_to_delete_.emplace_back(Test_Next_Lvl); + } + + void configureTree_() override {} + + void bindTree_() override + { + auto* root_node = getRoot(); + + sparta::bind(root_node->getChildAs("lsu.ports.out_source_req"), + root_node->getChildAs("dcache.ports.in_lsu_lookup_req")); + sparta::bind(root_node->getChildAs("lsu.ports.in_source_resp"), + root_node->getChildAs("dcache.ports.out_lsu_lookup_req")); + sparta::bind(root_node->getChildAs("lsu.ports.in_source_ack"), + root_node->getChildAs("dcache.ports.out_lsu_lookup_ack")); + + sparta::bind(root_node->getChildAs("next_lvl.ports.in_biu_req"), + root_node->getChildAs("dcache.ports.out_l2cache_req")); + sparta::bind(root_node->getChildAs("next_lvl.ports.out_biu_resp"), + root_node->getChildAs("dcache.ports.in_l2cache_resp")); + sparta::bind(root_node->getChildAs("next_lvl.ports.out_biu_ack"), + root_node->getChildAs("dcache.ports.in_l2cache_credits")); + } + + std::unique_ptr allocators_tn_; + + sparta::ResourceFactory + lsu_fact; + + sparta::ResourceFactory dcache_fact; + + sparta::ResourceFactory + next_lvl_fact; + + olympia::MavisFactory mavis_fact; + std::vector> tns_to_delete_; + + const std::string input_file_; + sparta::log::Tap test_tap_; +}; + +const char USAGE[] = "Usage:\n" + " \n" + "\n"; +sparta::app::DefaultValues DEFAULTS; + +void runTest(int argc, char** argv) +{ + DEFAULTS.auto_summary_default = "off"; + std::vector datafiles; + std::string input_file; + + sparta::app::CommandLineSimulator cls(USAGE, DEFAULTS); + auto & app_opts = cls.getApplicationOptions(); + app_opts.add_options()( + "output_file", + sparta::app::named_value>("output_file", &datafiles), + "Specifies the output file")( + "input-file", + sparta::app::named_value("INPUT_FILE", &input_file)->default_value(""), + "Provide a JSON instruction stream", + "Provide a JSON file with instructions to run through Execute"); + + po::positional_options_description & pos_opts = cls.getPositionalOptions(); + pos_opts.add("output_file", -1); // example, look for the at the end + + int err_code = 0; + if (!cls.parse(argc, argv, err_code)) + { + sparta_assert(false, "Command line parsing failed"); // Any errors already printed to cerr + } + + sparta_assert(false == datafiles.empty(), + "Need an output file as the last argument of the test"); + + sparta::Scheduler sched; + DCacheSim dcache_sim(&sched, "mavis_isa_files", "arches/isa_json", datafiles[0], input_file); + + cls.populateSimulation(&dcache_sim); + + cls.runSimulator(&dcache_sim); + + EXPECT_FILES_EQUAL(datafiles[0], "expected_output/" + datafiles[0] + ".EXPECTED"); +} + +int main(int argc, char** argv) +{ + runTest(argc, argv); + REPORT_ERROR; + return (int)ERROR_CODE; +} diff --git a/test/core/dcache/NextLvlSourceSinkUnit.hpp b/test/core/dcache/NextLvlSourceSinkUnit.hpp new file mode 100644 index 00000000..e808370f --- /dev/null +++ b/test/core/dcache/NextLvlSourceSinkUnit.hpp @@ -0,0 +1,53 @@ +#pragma once + +#include +#include "sparta/utils/SpartaSharedPointer.hpp" +#include "sparta/simulation/TreeNode.hpp" +#include "sparta/utils/LogUtils.hpp" +#include "core/MemoryAccessInfo.hpp" +#include "core/MavisUnit.hpp" + +namespace dcache_test +{ + class NextLvlSourceSinkUnit : public sparta::Unit + { + public: + static constexpr char name[] = "NextLvlSourceSinkUnit"; + + class NextLvlSinkUnitParameters : public sparta::ParameterSet + { + public: + explicit NextLvlSinkUnitParameters(sparta::TreeNode* n) : sparta::ParameterSet(n) {} + PARAMETER(std::string, purpose, "grp", "Purpose of this SinkUnit: grp, single") + PARAMETER(sparta::Clock::Cycle, sink_latency, 1, "Latency of this SinkUnit") + }; + + NextLvlSourceSinkUnit(sparta::TreeNode* n, const NextLvlSinkUnitParameters* params) : + sparta::Unit(n) + { + + purpose_ = params->purpose; + sink_latency_ = params->sink_latency; + + in_biu_req_.registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA( + NextLvlSourceSinkUnit, sinkInst_, olympia::MemoryAccessInfoPtr)); + } + + private: + void sinkInst_(const olympia::MemoryAccessInfoPtr & mem_access_info_ptr) + { + ILOG("Instruction: '" << mem_access_info_ptr->getInstPtr() << "' sinked"); + + out_biu_resp_.send(mem_access_info_ptr, 2 * sink_latency_); + } + + sparta::DataInPort in_biu_req_{ + &unit_port_set_, "in_biu_req", sparta::SchedulingPhase::Tick, 1}; + sparta::DataOutPort out_biu_resp_{&unit_port_set_, + "out_biu_resp"}; + sparta::DataOutPort out_biu_ack_{&unit_port_set_, "out_biu_ack"}; + + std::string purpose_; + sparta::Clock::Cycle sink_latency_; + }; +} // namespace dcache_test \ No newline at end of file diff --git a/test/core/dcache/SourceUnit.hpp b/test/core/dcache/SourceUnit.hpp new file mode 100644 index 00000000..d5e1a345 --- /dev/null +++ b/test/core/dcache/SourceUnit.hpp @@ -0,0 +1,123 @@ +#pragma once + +#include "sparta/utils/LogUtils.hpp" +#include "core/MemoryAccessInfo.hpp" +#include "core/InstGenerator.hpp" +#include "sparta/utils/LogUtils.hpp" + +namespace dcache_test +{ + class SourceUnit : public sparta::Unit + { + public: + static constexpr char name[] = "SourceUnit"; + + class SourceUnitParameters : public sparta::ParameterSet + { + public: + explicit SourceUnitParameters(sparta::TreeNode* n) : sparta::ParameterSet(n) {} + PARAMETER(std::string, input_file, "", "Input file: STF or JSON") + PARAMETER(sparta::Clock::Cycle, delay_btwn_insts, 1, + "Clock delay between instruction/requests to DCache") + }; + + SourceUnit(sparta::TreeNode* n, const SourceUnitParameters* params) : + sparta::Unit(n), + mavis_facade_(olympia::getMavis(n)), + delay_btwn_insts_(params->delay_btwn_insts) + { + + sparta_assert(mavis_facade_ != nullptr, "Could not find the Mavis Unit"); + + in_source_resp_.registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA( + SourceUnit, ReceiveInst_, olympia::MemoryAccessInfoPtr)); + in_source_ack_.registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA( + SourceUnit, ReceiveAck_, olympia::MemoryAccessInfoPtr)); + + if (params->input_file != "") + { + inst_generator_ = olympia::InstGenerator::createGenerator( + mavis_facade_, params->input_file, false); + } + + sparta::StartupEvent(n, CREATE_SPARTA_HANDLER(SourceUnit, sendInitialInst_)); + } + + ~SourceUnit() {} + + void onStartingTeardown_() override {} + + private: + void sendInitialInst_() { injectInsts_(); } + + void injectInsts_() + { + olympia::InstPtr dinst; + + if (inst_generator_) + { + + while (!inst_generator_->isDone()) + { + + dinst = inst_generator_->getNextInst(getClock()); + dinst->setUniqueID(unique_id_++); + + olympia::MemoryAccessInfoPtr mem_info_ptr(new olympia::MemoryAccessInfo(dinst)); + + req_inst_queue_.emplace_back(mem_info_ptr); + ev_req_inst_.schedule(schedule_time_); + + schedule_time_ += delay_btwn_insts_; + } + } + } + + void req_inst_() + { + + ILOG("Instruction: '" << req_inst_queue_.front()->getInstPtr() << "' Requested"); + + pending_reqs_++; + pending_acks_++; + + out_source_req_.send(req_inst_queue_.front()); + req_inst_queue_.erase(req_inst_queue_.begin()); + } + + void ReceiveInst_(const olympia::MemoryAccessInfoPtr & mem_info_ptr) + { + pending_reqs_--; + ILOG("Instruction: '" << mem_info_ptr->getInstPtr() << "' Received"); + } + + void ReceiveAck_(const olympia::MemoryAccessInfoPtr & mem_info_ptr) + { + pending_acks_--; + ILOG("Ack: '" << mem_info_ptr << "' Received"); + } + + sparta::DataInPort in_source_resp_{ + &unit_port_set_, "in_source_resp", sparta::SchedulingPhase::Tick, 1}; + sparta::DataInPort in_source_ack_{&unit_port_set_, + "in_source_ack"}; + + sparta::DataOutPort out_source_req_{&unit_port_set_, + "out_source_req"}; + + uint32_t pending_acks_ = 1; + uint32_t pending_reqs_ = 0; + + uint32_t unique_id_ = 0; + + olympia::MavisType* mavis_facade_ = nullptr; + std::unique_ptr inst_generator_; + + sparta::UniqueEvent<> ev_req_inst_{&unit_event_set_, "req_inst", + CREATE_SPARTA_HANDLER(SourceUnit, req_inst_)}; + + std::vector req_inst_queue_; + sparta::Clock::Cycle schedule_time_ = 0; + sparta::Clock::Cycle delay_btwn_insts_ = 0; + }; +} // namespace dcache_test \ No newline at end of file diff --git a/test/core/dcache/expected_output/arbitrate.out.EXPECTED b/test/core/dcache/expected_output/arbitrate.out.EXPECTED new file mode 100644 index 00000000..a8e783d7 --- /dev/null +++ b/test/core/dcache/expected_output/arbitrate.out.EXPECTED @@ -0,0 +1,74 @@ +#Name: +#Cmdline: +#Exe: +#SimulatorVersion: +#Repro: +#Start: Thursday Thu Sep 26 22:18:34 2024 +#Elapsed: 0.002017s +{0000000000 00000000 top.lsu info} req_inst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'lw 5,3' ' Requested +{0000000000 00000000 top.dcache info} receiveMemReqFromLSU_: Received memory access request from LSU memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'lw 5,3' +{0000000000 00000000 top.lsu info} ReceiveAck_: Ack: 'memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'lw 5,3' ' Received +{0000000000 00000000 top.dcache info} arbitrateL2LsuReq_: Received LSU request memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'lw 5,3' +{0000000001 00000001 top.dcache info} handleLookup_: Lookup stage +{0000000001 00000001 top.dcache info} handleLookup_: memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'lw 5,3' in Lookup stage +{0000000001 00000001 top.dcache info} dataLookup_: DL1 DCache MISS: phyAddr=0xdeadbeef +{0000000001 00000001 top.dcache info} handleLookup_: memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'lw 5,3' performing lookup 0 +{0000000001 00000001 top.dcache info} handleLookup_: Creating new MSHR Entry memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'lw 5,3' +{0000000001 00000001 top.dcache info} handleLookup_: Load miss inst to LMQ; block address:0xdeadbee0 +{0000000001 00000001 top.lsu info} ReceiveAck_: Ack: 'memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'lw 5,3' ' Received +{0000000001 00000001 top.dcache info} mshrRequest_: Send mshr req +{0000000001 00000001 top.dcache info} mshrRequest_: Sending mshr request when not busy memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'lw 5,3' +{0000000002 00000002 top.next_lvl info} sinkInst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'lw 5,3' ' sinked +{0000000002 00000002 top.dcache info} handleDataRead_: Data Read stage +{0000000002 00000002 top.dcache info} handleDataRead_: memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'lw 5,3' in read stage +{0000000002 00000002 top.lsu info} ReceiveAck_: Ack: 'memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'lw 5,3' ' Received +{0000000003 00000003 top.dcache info} handleDeallocate_: Data Dellocate stage +{0000000003 00000003 top.dcache info} handleDeallocate_: memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'lw 5,3' in deallocate stage +{0000000003 00000003 top.dcache info} handleDeallocate_: Deallocating pipeline for memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'lw 5,3' +{0000000003 00000003 top.dcache info} mshrRequest_: Send mshr req +{0000000007 00000007 top.dcache info} receiveRespFromL2Cache_: Received cache refill memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'lw 5,3' +{0000000007 00000007 top.dcache info} receiveRespFromL2Cache_: Removing mshr entry for memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'lw 5,3' +{0000000007 00000007 top.dcache info} arbitrateL2LsuReq_: Received Refill request memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'lw 5,3' +{0000000008 00000008 top.dcache info} handleLookup_: Lookup stage +{0000000008 00000008 top.dcache info} handleLookup_: memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'lw 5,3' in Lookup stage +{0000000008 00000008 top.dcache info} handleLookup_: Incoming cache refill memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'lw 5,3' +{0000000008 00000008 top.lsu info} req_inst_: Instruction: 'uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3' ' Requested +{0000000008 00000008 top.dcache info} receiveMemReqFromLSU_: Received memory access request from LSU memptr: deedbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3' +{0000000008 00000008 top.lsu info} ReceiveAck_: Ack: 'memptr: deedbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3' ' Received +{0000000008 00000008 top.dcache info} mshrRequest_: Send mshr req +{0000000008 00000008 top.dcache info} arbitrateL2LsuReq_: Received LSU request memptr: deedbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3' +{0000000009 00000009 top.dcache info} handleLookup_: Lookup stage +{0000000009 00000009 top.dcache info} handleLookup_: memptr: deedbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3' in Lookup stage +{0000000009 00000009 top.dcache info} dataLookup_: DL1 DCache MISS: phyAddr=0xdeedbeef +{0000000009 00000009 top.dcache info} handleLookup_: memptr: deedbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3' performing lookup 0 +{0000000009 00000009 top.dcache info} handleLookup_: Creating new MSHR Entry memptr: deedbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3' +{0000000009 00000009 top.dcache info} handleLookup_: Load miss inst to LMQ; block address:0xdeedbee0 +{0000000009 00000009 top.lsu info} ReceiveAck_: Ack: 'memptr: deedbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3' ' Received +{0000000009 00000009 top.dcache info} handleDataRead_: Data Read stage +{0000000009 00000009 top.dcache info} handleDataRead_: memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'lw 5,3' in read stage +{0000000009 00000009 top.dcache info} reloadCache_: DCache reload complete! +{0000000009 00000009 top.dcache info} mshrRequest_: Send mshr req +{0000000009 00000009 top.dcache info} mshrRequest_: Sending mshr request when not busy memptr: deedbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3' +{0000000010 00000010 top.next_lvl info} sinkInst_: Instruction: 'uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3' ' sinked +{0000000010 00000010 top.dcache info} handleDataRead_: Data Read stage +{0000000010 00000010 top.dcache info} handleDataRead_: memptr: deedbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3' in read stage +{0000000010 00000010 top.lsu info} ReceiveAck_: Ack: 'memptr: deedbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3' ' Received +{0000000010 00000010 top.dcache info} handleDeallocate_: Data Dellocate stage +{0000000010 00000010 top.dcache info} handleDeallocate_: memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'lw 5,3' in deallocate stage +{0000000010 00000010 top.lsu info} ReceiveAck_: Ack: 'memptr: deedbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3' ' Received +{0000000010 00000010 top.dcache info} handleDeallocate_: Removing mshr entry for memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'lw 5,3' +{0000000011 00000011 top.dcache info} handleDeallocate_: Data Dellocate stage +{0000000011 00000011 top.dcache info} handleDeallocate_: memptr: deedbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3' in deallocate stage +{0000000011 00000011 top.dcache info} handleDeallocate_: Deallocating pipeline for memptr: deedbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3' +{0000000011 00000011 top.dcache info} mshrRequest_: Send mshr req +{0000000015 00000015 top.dcache info} receiveRespFromL2Cache_: Received cache refill memptr: deedbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3' +{0000000015 00000015 top.dcache info} arbitrateL2LsuReq_: Received Refill request memptr: deedbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3' +{0000000016 00000016 top.dcache info} handleLookup_: Lookup stage +{0000000016 00000016 top.dcache info} handleLookup_: memptr: deedbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3' in Lookup stage +{0000000016 00000016 top.dcache info} handleLookup_: Incoming cache refill memptr: deedbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3' +{0000000016 00000016 top.dcache info} mshrRequest_: Send mshr req +{0000000017 00000017 top.dcache info} handleDataRead_: Data Read stage +{0000000017 00000017 top.dcache info} handleDataRead_: memptr: deedbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3' in read stage +{0000000017 00000017 top.dcache info} reloadCache_: DCache reload complete! +{0000000018 00000018 top.dcache info} handleDeallocate_: Data Dellocate stage +{0000000018 00000018 top.dcache info} handleDeallocate_: memptr: deedbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3' in deallocate stage diff --git a/test/core/dcache/next_lvl_cache_refill.json b/test/core/dcache/next_lvl_cache_refill.json new file mode 100644 index 00000000..4633535c --- /dev/null +++ b/test/core/dcache/next_lvl_cache_refill.json @@ -0,0 +1,14 @@ +[ + { + "mnemonic": "lw", + "rs1": 3, + "rd": 5, + "vaddr" : "0xdeadbeef" + }, + { + "mnemonic": "lw", + "rs1": 3, + "rd": 5, + "vaddr" : "0xdeedbeef" + } +] \ No newline at end of file diff --git a/test/core/dcache/test_arches/1_src_Dcache.yaml b/test/core/dcache/test_arches/1_src_Dcache.yaml new file mode 100644 index 00000000..1f728dea --- /dev/null +++ b/test/core/dcache/test_arches/1_src_Dcache.yaml @@ -0,0 +1,14 @@ +top: + lsu: + params: + delay_btwn_insts: 8 + dcache: + params: + l1_size_kb: 64 + l1_line_size: 32 + l1_associativity: 8 + l1_always_hit: false + mshr_entries: 8 + next_lvl: + params: + sink_latency: 2 diff --git a/test/core/dispatch/expected_output/big_core.out.EXPECTED b/test/core/dispatch/expected_output/big_core.out.EXPECTED index 037a35d2..5f049f20 100644 --- a/test/core/dispatch/expected_output/big_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/big_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 5 13:38:28 2024 -#Elapsed: 0.017899s +#Start: Tuesday Tue Jul 16 09:09:57 2024 +#Elapsed: 0.003678s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: DIViq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq1 @@ -17,6 +17,10 @@ {0000000000 00000000 top.dispatch info} Dispatch: mapping target: FMACiq3 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: F2Iiq3 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: BRiq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VSETiq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VDIViq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VMULiq5 {0000000000 00000000 top.execute.exe0 info} ExecutePipe: ExecutePipe construct: #0 {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 @@ -27,6 +31,7 @@ {0000000000 00000000 top.execute.exe7 info} ExecutePipe: ExecutePipe construct: #7 {0000000000 00000000 top.execute.exe8 info} ExecutePipe: ExecutePipe construct: #8 {0000000000 00000000 top.execute.exe9 info} ExecutePipe: ExecutePipe construct: #9 +{0000000000 00000000 top.execute.exe10 info} ExecutePipe: ExecutePipe construct: #10 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 10 credits, total: 10 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 @@ -41,21 +46,23 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq4 got 8 credits, total: 8 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} receiveCredits_: iq5 got 8 credits, total: 8 +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add, 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add, 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 0 'add 2,0,1' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 0 'add 4,2,3' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0,3] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 0 'add 6,4,5' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [5,32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 0 'add 8,6,7' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [7,33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard @@ -63,182 +70,182 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add, 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 0 'add 2,0,1' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' to iq0 of target type: INT -{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid: 1 RENAMED 0 pid: 0 'add 4,2,3' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' to iq1 of target type: INT -{0000000002 00000002 top.dispatch info} acceptInst: iq2: dispatching uid: 2 RENAMED 0 pid: 0 'add 6,4,5' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' to iq2 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to iq1 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq2: dispatching uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to iq2 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 0 'add 10,8,9' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [9,34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 0 'add 12,10,11' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [11,35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 0 'add 14,12,13' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [13,36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 0 'add 16,14,15' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [15,37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 4 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add, 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' -{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' Bits needed:[0,3] -{0000000003 00000003 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' Bits needed:[5,32] +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' Bits needed:[0,3] rf: integer +{0000000003 00000003 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' Bits needed:[5,32] rf: integer {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 0 'add 2,0,1' for 4 +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 3 RENAMED 0 pid: 0 'add 8,6,7' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' to iq0 of target type: INT -{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid: 4 RENAMED 0 pid: 0 'add 10,8,9' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' to iq1 of target type: INT -{0000000003 00000003 top.dispatch info} acceptInst: iq2: dispatching uid: 5 RENAMED 0 pid: 0 'add 12,10,11' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' to iq2 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to iq1 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq2: dispatching uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to iq2 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 0 'add 18,16,17' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [17,38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 0 'add 20,18,19' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [19,39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 10 RENAMED 0 pid: 0 'add 22,20,21' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 10 RENAMED 0 pid: 0 uopid: 0 'add 22,20,21' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [21,40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 11 RENAMED 0 pid: 0 'add 24,22,23' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 11 RENAMED 0 pid: 0 uopid: 0 'add 24,22,23' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [23,41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [42] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 4 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add, 0x00000000 UID(20) PID(0) add, 0x00000000 UID(21) PID(0) add -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' Bits needed:[7,33] -{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' Bits needed:[9,34] -{0000000004 00000004 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' Bits needed:[11,35] +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' Bits needed:[7,33] rf: integer +{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' Bits needed:[9,34] rf: integer +{0000000004 00000004 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' Bits needed:[11,35] rf: integer {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 0 'add 2,0,1' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 6 RENAMED 0 pid: 0 'add 14,12,13' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' to iq0 of target type: INT -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 7 RENAMED 0 pid: 0 'add 16,14,15' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' to iq1 of target type: INT -{0000000004 00000004 top.dispatch info} acceptInst: iq2: dispatching uid: 8 RENAMED 0 pid: 0 'add 18,16,17' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' to iq2 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to iq0 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to iq1 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq2: dispatching uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to iq2 of target type: INT {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 12 RENAMED 0 pid: 0 'add 26,24,25' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 12 RENAMED 0 pid: 0 uopid: 0 'add 26,24,25' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [25,42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [43] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 13 RENAMED 0 pid: 0 'add 28,26,27' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 13 RENAMED 0 pid: 0 uopid: 0 'add 28,26,27' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [27,43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [44] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 14 RENAMED 0 pid: 0 'add 30,28,29' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 14 RENAMED 0 pid: 0 uopid: 0 'add 30,28,29' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [29,44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [45] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 15 RENAMED 0 pid: 0 'add 0,30,31' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 15 RENAMED 0 pid: 0 uopid: 0 'add 0,30,31' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [45] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [31,45] for 'integer' scoreboard {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 4 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(22) PID(0) add, 0x00000000 UID(23) PID(0) add, 0x00000000 UID(24) PID(0) add, 0x00000000 UID(25) PID(0) add -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' Bits needed:[13,36] -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' Bits needed:[15,37] -{0000000005 00000005 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' Bits needed:[17,38] +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' Bits needed:[13,36] rf: integer +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' Bits needed:[15,37] rf: integer +{0000000005 00000005 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' Bits needed:[17,38] rf: integer {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add, 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add -{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid: 0 COMPLETED 0 pid: 0 'add 2,0,1' -{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' to exe_pipe exe2 -{0000000005 00000005 top.execute.exe2 info} insertInst: Executing: uid: 1 SCHEDULED 0 pid: 0 'add 4,2,3' for 6 +{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid: 0 COMPLETED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to exe_pipe exe2 +{0000000005 00000005 top.execute.exe2 info} insertInst: Executing: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' for 6 {0000000005 00000005 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 6 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid: 9 RENAMED 0 pid: 0 'add 20,18,19' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' to iq0 of target type: INT +{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to iq0 of target type: INT {0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 16 RENAMED 0 pid: 0 'add 2,0,1' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 16 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [46] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 17 RENAMED 0 pid: 0 'add 4,2,3' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 17 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [3,46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [47] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 18 RENAMED 0 pid: 0 'add 6,4,5' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 18 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [47] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [5,47] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [48] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 19 RENAMED 0 pid: 0 'add 8,6,7' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 19 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [48] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [7,48] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [49] for 'integer' scoreboard {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 4 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(26) PID(0) add, 0x00000000 UID(27) PID(0) add, 0x00000000 UID(28) PID(0) add, 0x00000000 UID(29) PID(0) add -{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' Bits needed:[19,39] +{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' Bits needed:[19,39] rf: integer {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add, 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add {0000000006 00000006 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000006 00000006 top.execute.exe2 info} executeInst_: Executed inst: uid: 1 SCHEDULED 0 pid: 0 'add 4,2,3' -{0000000007 00000007 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' -{0000000007 00000007 top.execute.exe2 info} completeInst_: Completing inst: uid: 1 COMPLETED 0 pid: 0 'add 4,2,3' -{0000000007 00000007 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' to exe_pipe exe4 -{0000000007 00000007 top.execute.exe4 info} insertInst: Executing: uid: 2 SCHEDULED 0 pid: 0 'add 6,4,5' for 8 +{0000000006 00000006 top.execute.exe2 info} executeInst_: Executed inst: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000007 00000007 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000007 00000007 top.execute.exe2 info} completeInst_: Completing inst: uid: 1 COMPLETED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000007 00000007 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to exe_pipe exe4 +{0000000007 00000007 top.execute.exe4 info} insertInst: Executing: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' for 8 {0000000007 00000007 top.dispatch info} receiveCredits_: iq2 got 1 credits, total: 6 {0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000008 00000008 top.execute.exe4 info} executeInst_: Executed inst: uid: 2 SCHEDULED 0 pid: 0 'add 6,4,5' -{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' -{0000000009 00000009 top.execute.exe4 info} completeInst_: Completing inst: uid: 2 COMPLETED 0 pid: 0 'add 6,4,5' -{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' to exe_pipe exe0 -{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid: 3 SCHEDULED 0 pid: 0 'add 8,6,7' for 10 +{0000000008 00000008 top.execute.exe4 info} executeInst_: Executed inst: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000009 00000009 top.execute.exe4 info} completeInst_: Completing inst: uid: 2 COMPLETED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to exe_pipe exe0 +{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' for 10 {0000000009 00000009 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000009 00000009 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid: 3 SCHEDULED 0 pid: 0 'add 8,6,7' -{0000000011 00000011 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' -{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid: 3 COMPLETED 0 pid: 0 'add 8,6,7' -{0000000011 00000011 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' to exe_pipe exe2 -{0000000011 00000011 top.execute.exe2 info} insertInst: Executing: uid: 4 SCHEDULED 0 pid: 0 'add 10,8,9' for 12 +{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000011 00000011 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid: 3 COMPLETED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000011 00000011 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to exe_pipe exe2 +{0000000011 00000011 top.execute.exe2 info} insertInst: Executing: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' for 12 {0000000011 00000011 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 7 {0000000011 00000011 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000012 00000012 top.execute.exe2 info} executeInst_: Executed inst: uid: 4 SCHEDULED 0 pid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' -{0000000013 00000013 top.execute.exe2 info} completeInst_: Completing inst: uid: 4 COMPLETED 0 pid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' to exe_pipe exe4 -{0000000013 00000013 top.execute.exe4 info} insertInst: Executing: uid: 5 SCHEDULED 0 pid: 0 'add 12,10,11' for 14 +{0000000012 00000012 top.execute.exe2 info} executeInst_: Executed inst: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000013 00000013 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000013 00000013 top.execute.exe2 info} completeInst_: Completing inst: uid: 4 COMPLETED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000013 00000013 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to exe_pipe exe4 +{0000000013 00000013 top.execute.exe4 info} insertInst: Executing: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' for 14 {0000000013 00000013 top.dispatch info} receiveCredits_: iq2 got 1 credits, total: 7 {0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000014 00000014 top.execute.exe4 info} executeInst_: Executed inst: uid: 5 SCHEDULED 0 pid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' -{0000000015 00000015 top.execute.exe4 info} completeInst_: Completing inst: uid: 5 COMPLETED 0 pid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' to exe_pipe exe0 -{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid: 6 SCHEDULED 0 pid: 0 'add 14,12,13' for 16 +{0000000014 00000014 top.execute.exe4 info} executeInst_: Executed inst: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000015 00000015 top.execute.exe4 info} completeInst_: Completing inst: uid: 5 COMPLETED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to exe_pipe exe0 +{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' for 16 {0000000015 00000015 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid: 6 SCHEDULED 0 pid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' -{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid: 6 COMPLETED 0 pid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' to exe_pipe exe2 -{0000000017 00000017 top.execute.exe2 info} insertInst: Executing: uid: 7 SCHEDULED 0 pid: 0 'add 16,14,15' for 18 +{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid: 6 COMPLETED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to exe_pipe exe2 +{0000000017 00000017 top.execute.exe2 info} insertInst: Executing: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' for 18 {0000000017 00000017 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 8 {0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000018 00000018 top.execute.exe2 info} executeInst_: Executed inst: uid: 7 SCHEDULED 0 pid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' -{0000000019 00000019 top.execute.exe2 info} completeInst_: Completing inst: uid: 7 COMPLETED 0 pid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' to exe_pipe exe4 -{0000000019 00000019 top.execute.exe4 info} insertInst: Executing: uid: 8 SCHEDULED 0 pid: 0 'add 18,16,17' for 20 +{0000000018 00000018 top.execute.exe2 info} executeInst_: Executed inst: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000019 00000019 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000019 00000019 top.execute.exe2 info} completeInst_: Completing inst: uid: 7 COMPLETED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000019 00000019 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to exe_pipe exe4 +{0000000019 00000019 top.execute.exe4 info} insertInst: Executing: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' for 20 {0000000019 00000019 top.dispatch info} receiveCredits_: iq2 got 1 credits, total: 8 {0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000020 00000020 top.execute.exe4 info} executeInst_: Executed inst: uid: 8 SCHEDULED 0 pid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' -{0000000021 00000021 top.execute.exe4 info} completeInst_: Completing inst: uid: 8 COMPLETED 0 pid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' to exe_pipe exe0 -{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid: 9 SCHEDULED 0 pid: 0 'add 20,18,19' for 22 +{0000000020 00000020 top.execute.exe4 info} executeInst_: Executed inst: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000021 00000021 top.execute.exe4 info} completeInst_: Completing inst: uid: 8 COMPLETED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to exe_pipe exe0 +{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' for 22 {0000000021 00000021 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid: 9 SCHEDULED 0 pid: 0 'add 20,18,19' -{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid: 9 COMPLETED 0 pid: 0 'add 20,18,19' +{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid: 9 COMPLETED 0 pid: 0 uopid: 0 'add 20,18,19' diff --git a/test/core/dispatch/expected_output/medium_core.out.EXPECTED b/test/core/dispatch/expected_output/medium_core.out.EXPECTED index bc042b8f..837fbfc3 100644 --- a/test/core/dispatch/expected_output/medium_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/medium_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 5 13:38:34 2024 -#Elapsed: 0.004375s +#Start: Tuesday Tue Jul 16 09:09:57 2024 +#Elapsed: 0.003807s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -16,12 +16,17 @@ {0000000000 00000000 top.dispatch info} Dispatch: mapping target: FMACiq2 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: F2Iiq2 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: BRiq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VSETiq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VDIViq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VMULiq4 {0000000000 00000000 top.execute.exe0 info} ExecutePipe: ExecutePipe construct: #0 {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 {0000000000 00000000 top.execute.exe3 info} ExecutePipe: ExecutePipe construct: #3 {0000000000 00000000 top.execute.exe4 info} ExecutePipe: ExecutePipe construct: #4 {0000000000 00000000 top.execute.exe5 info} ExecutePipe: ExecutePipe construct: #5 +{0000000000 00000000 top.execute.exe6 info} ExecutePipe: ExecutePipe construct: #6 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 10 credits, total: 10 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 @@ -34,21 +39,23 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq3 got 8 credits, total: 8 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} receiveCredits_: iq4 got 8 credits, total: 8 +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add, 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add, 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 0 'add 2,0,1' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 0 'add 4,2,3' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0,3] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 0 'add 6,4,5' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [5,32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 0 'add 8,6,7' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [7,33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard @@ -56,191 +63,191 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add, 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 0 'add 2,0,1' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' to iq0 of target type: INT -{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid: 1 RENAMED 0 pid: 0 'add 4,2,3' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' to iq1 of target type: INT -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 2 RENAMED 0 pid: 0 'add 6,4,5' stall: INT_BUSY +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to iq1 of target type: INT +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' stall: INT_BUSY {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 0 'add 10,8,9' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [9,34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 0 'add 12,10,11' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [11,35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 0 'add 14,12,13' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [13,36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 0 'add 16,14,15' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [15,37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 4 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add, 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' -{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' Bits needed:[0,3] +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' Bits needed:[0,3] rf: integer {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 0 'add 2,0,1' for 4 +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 0 'add 6,4,5' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' to iq0 of target type: INT -{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid: 3 RENAMED 0 pid: 0 'add 8,6,7' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' to iq1 of target type: INT -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 4 RENAMED 0 pid: 0 'add 10,8,9' stall: INT_BUSY +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to iq1 of target type: INT +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' stall: INT_BUSY {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 0 'add 18,16,17' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [17,38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 0 'add 20,18,19' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [19,39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 10 RENAMED 0 pid: 0 'add 22,20,21' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 10 RENAMED 0 pid: 0 uopid: 0 'add 22,20,21' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [21,40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 11 RENAMED 0 pid: 0 'add 24,22,23' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 11 RENAMED 0 pid: 0 uopid: 0 'add 24,22,23' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [23,41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [42] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 4 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add, 0x00000000 UID(20) PID(0) add, 0x00000000 UID(21) PID(0) add -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' Bits needed:[5,32] -{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' Bits needed:[7,33] +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' Bits needed:[5,32] rf: integer +{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' Bits needed:[7,33] rf: integer {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 0 'add 2,0,1' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 4 RENAMED 0 pid: 0 'add 10,8,9' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' to iq0 of target type: INT -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 5 RENAMED 0 pid: 0 'add 12,10,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' to iq1 of target type: INT -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 6 RENAMED 0 pid: 0 'add 14,12,13' stall: INT_BUSY +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to iq0 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to iq1 of target type: INT +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' stall: INT_BUSY {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 12 RENAMED 0 pid: 0 'add 26,24,25' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 12 RENAMED 0 pid: 0 uopid: 0 'add 26,24,25' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [25,42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [43] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 13 RENAMED 0 pid: 0 'add 28,26,27' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 13 RENAMED 0 pid: 0 uopid: 0 'add 28,26,27' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [27,43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [44] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 14 RENAMED 0 pid: 0 'add 30,28,29' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 14 RENAMED 0 pid: 0 uopid: 0 'add 30,28,29' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [29,44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [45] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 15 RENAMED 0 pid: 0 'add 0,30,31' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 15 RENAMED 0 pid: 0 uopid: 0 'add 0,30,31' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [45] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [31,45] for 'integer' scoreboard {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 4 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(22) PID(0) add, 0x00000000 UID(23) PID(0) add, 0x00000000 UID(24) PID(0) add, 0x00000000 UID(25) PID(0) add -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' Bits needed:[9,34] -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' Bits needed:[11,35] +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' Bits needed:[9,34] rf: integer +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' Bits needed:[11,35] rf: integer {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add, 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add -{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid: 0 COMPLETED 0 pid: 0 'add 2,0,1' -{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' to exe_pipe exe1 -{0000000005 00000005 top.execute.exe1 info} insertInst: Executing: uid: 1 SCHEDULED 0 pid: 0 'add 4,2,3' for 6 +{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid: 0 COMPLETED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to exe_pipe exe1 +{0000000005 00000005 top.execute.exe1 info} insertInst: Executing: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' for 6 {0000000005 00000005 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 6 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid: 6 RENAMED 0 pid: 0 'add 14,12,13' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' to iq0 of target type: INT -{0000000005 00000005 top.dispatch info} acceptInst: iq1: dispatching uid: 7 RENAMED 0 pid: 0 'add 16,14,15' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' to iq1 of target type: INT -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 8 RENAMED 0 pid: 0 'add 18,16,17' stall: INT_BUSY +{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to iq0 of target type: INT +{0000000005 00000005 top.dispatch info} acceptInst: iq1: dispatching uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to iq1 of target type: INT +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' stall: INT_BUSY {0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 16 RENAMED 0 pid: 0 'add 2,0,1' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 16 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [46] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 17 RENAMED 0 pid: 0 'add 4,2,3' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 17 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [3,46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [47] for 'integer' scoreboard {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 2 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(26) PID(0) add, 0x00000000 UID(27) PID(0) add -{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' Bits needed:[13,36] -{0000000006 00000006 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' Bits needed:[15,37] +{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' Bits needed:[13,36] rf: integer +{0000000006 00000006 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' Bits needed:[15,37] rf: integer {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000006 00000006 top.execute.exe1 info} executeInst_: Executed inst: uid: 1 SCHEDULED 0 pid: 0 'add 4,2,3' +{0000000006 00000006 top.execute.exe1 info} executeInst_: Executed inst: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000006 00000006 top.dispatch info} dispatchInstructions_: Num to dispatch: 2 -{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid: 8 RENAMED 0 pid: 0 'add 18,16,17' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' to iq0 of target type: INT -{0000000006 00000006 top.dispatch info} acceptInst: iq1: dispatching uid: 9 RENAMED 0 pid: 0 'add 20,18,19' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' to iq1 of target type: INT +{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to iq0 of target type: INT +{0000000006 00000006 top.dispatch info} acceptInst: iq1: dispatching uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to iq1 of target type: INT {0000000006 00000006 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 18 RENAMED 0 pid: 0 'add 6,4,5' +{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 18 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [47] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [5,47] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [48] for 'integer' scoreboard -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 19 RENAMED 0 pid: 0 'add 8,6,7' +{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 19 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [48] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [7,48] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [49] for 'integer' scoreboard {0000000006 00000006 top.decode info} inCredits: Got credits from dut: 2 {0000000006 00000006 top.decode info} Sending group: 0x00000000 UID(28) PID(0) add, 0x00000000 UID(29) PID(0) add -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' Bits needed:[17,38] -{0000000007 00000007 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' Bits needed:[19,39] +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' Bits needed:[17,38] rf: integer +{0000000007 00000007 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' Bits needed:[19,39] rf: integer {0000000007 00000007 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add {0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000007 00000007 top.execute.exe1 info} completeInst_: Completing inst: uid: 1 COMPLETED 0 pid: 0 'add 4,2,3' -{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' to exe_pipe exe0 -{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid: 2 SCHEDULED 0 pid: 0 'add 6,4,5' for 8 +{0000000007 00000007 top.execute.exe1 info} completeInst_: Completing inst: uid: 1 COMPLETED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to exe_pipe exe0 +{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' for 8 {0000000007 00000007 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 5 {0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid: 2 SCHEDULED 0 pid: 0 'add 6,4,5' -{0000000009 00000009 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' -{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid: 2 COMPLETED 0 pid: 0 'add 6,4,5' -{0000000009 00000009 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' to exe_pipe exe1 -{0000000009 00000009 top.execute.exe1 info} insertInst: Executing: uid: 3 SCHEDULED 0 pid: 0 'add 8,6,7' for 10 +{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000009 00000009 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid: 2 COMPLETED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000009 00000009 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to exe_pipe exe1 +{0000000009 00000009 top.execute.exe1 info} insertInst: Executing: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' for 10 {0000000009 00000009 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 5 {0000000009 00000009 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000010 00000010 top.execute.exe1 info} executeInst_: Executed inst: uid: 3 SCHEDULED 0 pid: 0 'add 8,6,7' -{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' -{0000000011 00000011 top.execute.exe1 info} completeInst_: Completing inst: uid: 3 COMPLETED 0 pid: 0 'add 8,6,7' -{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' to exe_pipe exe0 -{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid: 4 SCHEDULED 0 pid: 0 'add 10,8,9' for 12 +{0000000010 00000010 top.execute.exe1 info} executeInst_: Executed inst: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000011 00000011 top.execute.exe1 info} completeInst_: Completing inst: uid: 3 COMPLETED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to exe_pipe exe0 +{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' for 12 {0000000011 00000011 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000011 00000011 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid: 4 SCHEDULED 0 pid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' -{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid: 4 COMPLETED 0 pid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' to exe_pipe exe1 -{0000000013 00000013 top.execute.exe1 info} insertInst: Executing: uid: 5 SCHEDULED 0 pid: 0 'add 12,10,11' for 14 +{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000013 00000013 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid: 4 COMPLETED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000013 00000013 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to exe_pipe exe1 +{0000000013 00000013 top.execute.exe1 info} insertInst: Executing: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' for 14 {0000000013 00000013 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 6 {0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000014 00000014 top.execute.exe1 info} executeInst_: Executed inst: uid: 5 SCHEDULED 0 pid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' -{0000000015 00000015 top.execute.exe1 info} completeInst_: Completing inst: uid: 5 COMPLETED 0 pid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' to exe_pipe exe0 -{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid: 6 SCHEDULED 0 pid: 0 'add 14,12,13' for 16 +{0000000014 00000014 top.execute.exe1 info} executeInst_: Executed inst: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000015 00000015 top.execute.exe1 info} completeInst_: Completing inst: uid: 5 COMPLETED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to exe_pipe exe0 +{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' for 16 {0000000015 00000015 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid: 6 SCHEDULED 0 pid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' -{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid: 6 COMPLETED 0 pid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' to exe_pipe exe1 -{0000000017 00000017 top.execute.exe1 info} insertInst: Executing: uid: 7 SCHEDULED 0 pid: 0 'add 16,14,15' for 18 +{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid: 6 COMPLETED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to exe_pipe exe1 +{0000000017 00000017 top.execute.exe1 info} insertInst: Executing: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' for 18 {0000000017 00000017 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 7 {0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000018 00000018 top.execute.exe1 info} executeInst_: Executed inst: uid: 7 SCHEDULED 0 pid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' -{0000000019 00000019 top.execute.exe1 info} completeInst_: Completing inst: uid: 7 COMPLETED 0 pid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' to exe_pipe exe0 -{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid: 8 SCHEDULED 0 pid: 0 'add 18,16,17' for 20 +{0000000018 00000018 top.execute.exe1 info} executeInst_: Executed inst: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000019 00000019 top.execute.exe1 info} completeInst_: Completing inst: uid: 7 COMPLETED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to exe_pipe exe0 +{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' for 20 {0000000019 00000019 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid: 8 SCHEDULED 0 pid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' -{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid: 8 COMPLETED 0 pid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' to exe_pipe exe1 -{0000000021 00000021 top.execute.exe1 info} insertInst: Executing: uid: 9 SCHEDULED 0 pid: 0 'add 20,18,19' for 22 +{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000021 00000021 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid: 8 COMPLETED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000021 00000021 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to exe_pipe exe1 +{0000000021 00000021 top.execute.exe1 info} insertInst: Executing: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' for 22 {0000000021 00000021 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 8 {0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000022 00000022 top.execute.exe1 info} executeInst_: Executed inst: uid: 9 SCHEDULED 0 pid: 0 'add 20,18,19' -{0000000023 00000023 top.execute.exe1 info} completeInst_: Completing inst: uid: 9 COMPLETED 0 pid: 0 'add 20,18,19' +{0000000022 00000022 top.execute.exe1 info} executeInst_: Executed inst: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000023 00000023 top.execute.exe1 info} completeInst_: Completing inst: uid: 9 COMPLETED 0 pid: 0 uopid: 0 'add 20,18,19' diff --git a/test/core/dispatch/expected_output/small_core.out.EXPECTED b/test/core/dispatch/expected_output/small_core.out.EXPECTED index 4e70d90a..f1f7560a 100644 --- a/test/core/dispatch/expected_output/small_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/small_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 5 13:38:37 2024 -#Elapsed: 0.004805s +#Start: Tuesday Tue Jul 16 09:09:57 2024 +#Elapsed: 0.003546s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -15,9 +15,14 @@ {0000000000 00000000 top.dispatch info} Dispatch: mapping target: FMACiq1 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: F2Iiq1 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: BRiq2 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VSETiq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VDIViq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VMULiq3 {0000000000 00000000 top.execute.exe0 info} ExecutePipe: ExecutePipe construct: #0 {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 +{0000000000 00000000 top.execute.exe3 info} ExecutePipe: ExecutePipe construct: #3 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 10 credits, total: 10 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 @@ -28,21 +33,23 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq2 got 8 credits, total: 8 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} receiveCredits_: iq3 got 8 credits, total: 8 +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add, 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add, 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 0 'add 2,0,1' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 0 'add 4,2,3' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0,3] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 0 'add 6,4,5' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [5,32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 0 'add 8,6,7' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [7,33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard @@ -50,218 +57,218 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add, 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 0 'add 2,0,1' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' to iq0 of target type: INT -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 1 RENAMED 0 pid: 0 'add 4,2,3' stall: INT_BUSY +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' stall: INT_BUSY {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 0 'add 10,8,9' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [9,34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 0 'add 12,10,11' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [11,35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 0 'add 14,12,13' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [13,36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 0 'add 16,14,15' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [15,37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 4 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add, 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 0 'add 2,0,1' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 0 'add 2,0,1' for 4 +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 0 'add 4,2,3' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' to iq0 of target type: INT -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 2 RENAMED 0 pid: 0 'add 6,4,5' stall: INT_BUSY +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' stall: INT_BUSY {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 0 'add 18,16,17' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [17,38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 0 'add 20,18,19' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [19,39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 10 RENAMED 0 pid: 0 'add 22,20,21' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 10 RENAMED 0 pid: 0 uopid: 0 'add 22,20,21' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [21,40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 11 RENAMED 0 pid: 0 'add 24,22,23' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 11 RENAMED 0 pid: 0 uopid: 0 'add 24,22,23' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [23,41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [42] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 4 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add, 0x00000000 UID(20) PID(0) add, 0x00000000 UID(21) PID(0) add -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' Bits needed:[0,3] +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' Bits needed:[0,3] rf: integer {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 0 'add 2,0,1' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 0 'add 6,4,5' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' to iq0 of target type: INT -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 3 RENAMED 0 pid: 0 'add 8,6,7' stall: INT_BUSY +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to iq0 of target type: INT +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' stall: INT_BUSY {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 12 RENAMED 0 pid: 0 'add 26,24,25' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 12 RENAMED 0 pid: 0 uopid: 0 'add 26,24,25' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [25,42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [43] for 'integer' scoreboard {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 1 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(22) PID(0) add -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' Bits needed:[5,32] +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' Bits needed:[5,32] rf: integer {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(12) PID(0) add -{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid: 0 COMPLETED 0 pid: 0 'add 2,0,1' -{0000000005 00000005 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 1 DISPATCHED 0 pid: 0 'add 4,2,3' to exe_pipe exe0 -{0000000005 00000005 top.execute.exe0 info} insertInst: Executing: uid: 1 SCHEDULED 0 pid: 0 'add 4,2,3' for 6 +{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid: 0 COMPLETED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000005 00000005 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to exe_pipe exe0 +{0000000005 00000005 top.execute.exe0 info} insertInst: Executing: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' for 6 {0000000005 00000005 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid: 3 RENAMED 0 pid: 0 'add 8,6,7' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' to iq0 of target type: INT -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 4 RENAMED 0 pid: 0 'add 10,8,9' stall: INT_BUSY +{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to iq0 of target type: INT +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' stall: INT_BUSY {0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 13 RENAMED 0 pid: 0 'add 28,26,27' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 13 RENAMED 0 pid: 0 uopid: 0 'add 28,26,27' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [43] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [27,43] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [44] for 'integer' scoreboard {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 1 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(23) PID(0) add -{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' Bits needed:[7,33] +{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' Bits needed:[7,33] rf: integer {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(13) PID(0) add -{0000000006 00000006 top.execute.exe0 info} executeInst_: Executed inst: uid: 1 SCHEDULED 0 pid: 0 'add 4,2,3' +{0000000006 00000006 top.execute.exe0 info} executeInst_: Executed inst: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000006 00000006 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid: 4 RENAMED 0 pid: 0 'add 10,8,9' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' to iq0 of target type: INT -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 5 RENAMED 0 pid: 0 'add 12,10,11' stall: INT_BUSY +{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to iq0 of target type: INT +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' stall: INT_BUSY {0000000006 00000006 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 14 RENAMED 0 pid: 0 'add 30,28,29' +{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 14 RENAMED 0 pid: 0 uopid: 0 'add 30,28,29' {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [44] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [29,44] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [45] for 'integer' scoreboard {0000000006 00000006 top.decode info} inCredits: Got credits from dut: 1 {0000000006 00000006 top.decode info} Sending group: 0x00000000 UID(24) PID(0) add -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' Bits needed:[9,34] +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' Bits needed:[9,34] rf: integer {0000000007 00000007 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(14) PID(0) add -{0000000007 00000007 top.execute.exe0 info} completeInst_: Completing inst: uid: 1 COMPLETED 0 pid: 0 'add 4,2,3' -{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 2 DISPATCHED 0 pid: 0 'add 6,4,5' to exe_pipe exe0 -{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid: 2 SCHEDULED 0 pid: 0 'add 6,4,5' for 8 +{0000000007 00000007 top.execute.exe0 info} completeInst_: Completing inst: uid: 1 COMPLETED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to exe_pipe exe0 +{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' for 8 {0000000007 00000007 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000007 00000007 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000007 00000007 top.dispatch info} acceptInst: iq0: dispatching uid: 5 RENAMED 0 pid: 0 'add 12,10,11' -{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' to iq0 of target type: INT -{0000000007 00000007 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 6 RENAMED 0 pid: 0 'add 14,12,13' stall: INT_BUSY +{0000000007 00000007 top.dispatch info} acceptInst: iq0: dispatching uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to iq0 of target type: INT +{0000000007 00000007 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' stall: INT_BUSY {0000000007 00000007 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000007 00000007 top.rename info} renameInstructions_: sending inst to dispatch: uid: 15 RENAMED 0 pid: 0 'add 0,30,31' +{0000000007 00000007 top.rename info} renameInstructions_: sending inst to dispatch: uid: 15 RENAMED 0 pid: 0 uopid: 0 'add 0,30,31' {0000000007 00000007 top.rename info} renameInstructions_: setup source register bit mask [45] for 'integer' scoreboard {0000000007 00000007 top.rename info} renameInstructions_: setup source register bit mask [31,45] for 'integer' scoreboard {0000000007 00000007 top.decode info} inCredits: Got credits from dut: 1 {0000000007 00000007 top.decode info} Sending group: 0x00000000 UID(25) PID(0) add -{0000000008 00000008 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' Bits needed:[11,35] +{0000000008 00000008 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' Bits needed:[11,35] rf: integer {0000000008 00000008 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(15) PID(0) add -{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid: 2 SCHEDULED 0 pid: 0 'add 6,4,5' +{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' {0000000008 00000008 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000008 00000008 top.dispatch info} acceptInst: iq0: dispatching uid: 6 RENAMED 0 pid: 0 'add 14,12,13' -{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' to iq0 of target type: INT -{0000000008 00000008 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 7 RENAMED 0 pid: 0 'add 16,14,15' stall: INT_BUSY +{0000000008 00000008 top.dispatch info} acceptInst: iq0: dispatching uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to iq0 of target type: INT +{0000000008 00000008 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' stall: INT_BUSY {0000000008 00000008 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000008 00000008 top.rename info} renameInstructions_: sending inst to dispatch: uid: 16 RENAMED 0 pid: 0 'add 2,0,1' +{0000000008 00000008 top.rename info} renameInstructions_: sending inst to dispatch: uid: 16 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' {0000000008 00000008 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000008 00000008 top.rename info} renameInstructions_: setup destination register bit mask [46] for 'integer' scoreboard {0000000008 00000008 top.decode info} inCredits: Got credits from dut: 1 {0000000008 00000008 top.decode info} Sending group: 0x00000000 UID(26) PID(0) add -{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' -{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' Bits needed:[13,36] +{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' Bits needed:[13,36] rf: integer {0000000009 00000009 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(16) PID(0) add -{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid: 2 COMPLETED 0 pid: 0 'add 6,4,5' -{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 3 DISPATCHED 0 pid: 0 'add 8,6,7' to exe_pipe exe0 -{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid: 3 SCHEDULED 0 pid: 0 'add 8,6,7' for 10 +{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid: 2 COMPLETED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to exe_pipe exe0 +{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' for 10 {0000000009 00000009 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 5 {0000000009 00000009 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000009 00000009 top.dispatch info} acceptInst: iq0: dispatching uid: 7 RENAMED 0 pid: 0 'add 16,14,15' -{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' to iq0 of target type: INT -{0000000009 00000009 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 8 RENAMED 0 pid: 0 'add 18,16,17' stall: INT_BUSY +{0000000009 00000009 top.dispatch info} acceptInst: iq0: dispatching uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to iq0 of target type: INT +{0000000009 00000009 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' stall: INT_BUSY {0000000009 00000009 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000009 00000009 top.rename info} renameInstructions_: sending inst to dispatch: uid: 17 RENAMED 0 pid: 0 'add 4,2,3' +{0000000009 00000009 top.rename info} renameInstructions_: sending inst to dispatch: uid: 17 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' {0000000009 00000009 top.rename info} renameInstructions_: setup source register bit mask [46] for 'integer' scoreboard {0000000009 00000009 top.rename info} renameInstructions_: setup source register bit mask [3,46] for 'integer' scoreboard {0000000009 00000009 top.rename info} renameInstructions_: setup destination register bit mask [47] for 'integer' scoreboard {0000000009 00000009 top.decode info} inCredits: Got credits from dut: 1 {0000000009 00000009 top.decode info} Sending group: 0x00000000 UID(27) PID(0) add -{0000000010 00000010 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' Bits needed:[15,37] +{0000000010 00000010 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' Bits needed:[15,37] rf: integer {0000000010 00000010 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(17) PID(0) add -{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid: 3 SCHEDULED 0 pid: 0 'add 8,6,7' +{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' {0000000010 00000010 top.dispatch info} dispatchInstructions_: Num to dispatch: 2 -{0000000010 00000010 top.dispatch info} acceptInst: iq0: dispatching uid: 8 RENAMED 0 pid: 0 'add 18,16,17' -{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' to iq0 of target type: INT -{0000000010 00000010 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 9 RENAMED 0 pid: 0 'add 20,18,19' stall: INT_BUSY +{0000000010 00000010 top.dispatch info} acceptInst: iq0: dispatching uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to iq0 of target type: INT +{0000000010 00000010 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' stall: INT_BUSY {0000000010 00000010 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000010 00000010 top.rename info} renameInstructions_: sending inst to dispatch: uid: 18 RENAMED 0 pid: 0 'add 6,4,5' +{0000000010 00000010 top.rename info} renameInstructions_: sending inst to dispatch: uid: 18 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' {0000000010 00000010 top.rename info} renameInstructions_: setup source register bit mask [47] for 'integer' scoreboard {0000000010 00000010 top.rename info} renameInstructions_: setup source register bit mask [5,47] for 'integer' scoreboard {0000000010 00000010 top.rename info} renameInstructions_: setup destination register bit mask [48] for 'integer' scoreboard {0000000010 00000010 top.decode info} inCredits: Got credits from dut: 1 {0000000010 00000010 top.decode info} Sending group: 0x00000000 UID(28) PID(0) add -{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' -{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' Bits needed:[17,38] +{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' Bits needed:[17,38] rf: integer {0000000011 00000011 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(18) PID(0) add -{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid: 3 COMPLETED 0 pid: 0 'add 8,6,7' -{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 4 DISPATCHED 0 pid: 0 'add 10,8,9' to exe_pipe exe0 -{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid: 4 SCHEDULED 0 pid: 0 'add 10,8,9' for 12 +{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid: 3 COMPLETED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to exe_pipe exe0 +{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' for 12 {0000000011 00000011 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 4 {0000000011 00000011 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000011 00000011 top.dispatch info} acceptInst: iq0: dispatching uid: 9 RENAMED 0 pid: 0 'add 20,18,19' -{0000000011 00000011 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' to iq0 of target type: INT +{0000000011 00000011 top.dispatch info} acceptInst: iq0: dispatching uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000011 00000011 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to iq0 of target type: INT {0000000011 00000011 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000011 00000011 top.rename info} renameInstructions_: sending inst to dispatch: uid: 19 RENAMED 0 pid: 0 'add 8,6,7' +{0000000011 00000011 top.rename info} renameInstructions_: sending inst to dispatch: uid: 19 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' {0000000011 00000011 top.rename info} renameInstructions_: setup source register bit mask [48] for 'integer' scoreboard {0000000011 00000011 top.rename info} renameInstructions_: setup source register bit mask [7,48] for 'integer' scoreboard {0000000011 00000011 top.rename info} renameInstructions_: setup destination register bit mask [49] for 'integer' scoreboard {0000000011 00000011 top.decode info} inCredits: Got credits from dut: 1 {0000000011 00000011 top.decode info} Sending group: 0x00000000 UID(29) PID(0) add -{0000000012 00000012 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' Bits needed:[19,39] +{0000000012 00000012 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' Bits needed:[19,39] rf: integer {0000000012 00000012 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(19) PID(0) add {0000000012 00000012 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid: 4 SCHEDULED 0 pid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' -{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid: 4 COMPLETED 0 pid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 5 DISPATCHED 0 pid: 0 'add 12,10,11' to exe_pipe exe0 -{0000000013 00000013 top.execute.exe0 info} insertInst: Executing: uid: 5 SCHEDULED 0 pid: 0 'add 12,10,11' for 14 +{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000013 00000013 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid: 4 COMPLETED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000013 00000013 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to exe_pipe exe0 +{0000000013 00000013 top.execute.exe0 info} insertInst: Executing: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' for 14 {0000000013 00000013 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 4 {0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000014 00000014 top.execute.exe0 info} executeInst_: Executed inst: uid: 5 SCHEDULED 0 pid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' -{0000000015 00000015 top.execute.exe0 info} completeInst_: Completing inst: uid: 5 COMPLETED 0 pid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 6 DISPATCHED 0 pid: 0 'add 14,12,13' to exe_pipe exe0 -{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid: 6 SCHEDULED 0 pid: 0 'add 14,12,13' for 16 +{0000000014 00000014 top.execute.exe0 info} executeInst_: Executed inst: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000015 00000015 top.execute.exe0 info} completeInst_: Completing inst: uid: 5 COMPLETED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to exe_pipe exe0 +{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' for 16 {0000000015 00000015 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 5 {0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid: 6 SCHEDULED 0 pid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' -{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid: 6 COMPLETED 0 pid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 7 DISPATCHED 0 pid: 0 'add 16,14,15' to exe_pipe exe0 -{0000000017 00000017 top.execute.exe0 info} insertInst: Executing: uid: 7 SCHEDULED 0 pid: 0 'add 16,14,15' for 18 +{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000017 00000017 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid: 6 COMPLETED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000017 00000017 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to exe_pipe exe0 +{0000000017 00000017 top.execute.exe0 info} insertInst: Executing: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' for 18 {0000000017 00000017 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000018 00000018 top.execute.exe0 info} executeInst_: Executed inst: uid: 7 SCHEDULED 0 pid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' -{0000000019 00000019 top.execute.exe0 info} completeInst_: Completing inst: uid: 7 COMPLETED 0 pid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 8 DISPATCHED 0 pid: 0 'add 18,16,17' to exe_pipe exe0 -{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid: 8 SCHEDULED 0 pid: 0 'add 18,16,17' for 20 +{0000000018 00000018 top.execute.exe0 info} executeInst_: Executed inst: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000019 00000019 top.execute.exe0 info} completeInst_: Completing inst: uid: 7 COMPLETED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to exe_pipe exe0 +{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' for 20 {0000000019 00000019 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid: 8 SCHEDULED 0 pid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' -{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid: 8 COMPLETED 0 pid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 9 DISPATCHED 0 pid: 0 'add 20,18,19' to exe_pipe exe0 -{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid: 9 SCHEDULED 0 pid: 0 'add 20,18,19' for 22 +{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid: 8 COMPLETED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to exe_pipe exe0 +{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' for 22 {0000000021 00000021 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid: 9 SCHEDULED 0 pid: 0 'add 20,18,19' -{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid: 9 COMPLETED 0 pid: 0 'add 20,18,19' +{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid: 9 COMPLETED 0 pid: 0 uopid: 0 'add 20,18,19' diff --git a/test/core/dispatch/test_cores/test_big_core.yaml b/test/core/dispatch/test_cores/test_big_core.yaml index 56fcd1c5..4119f823 100644 --- a/test/core/dispatch/test_cores/test_big_core.yaml +++ b/test/core/dispatch/test_cores/test_big_core.yaml @@ -13,7 +13,8 @@ top.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -21,25 +22,37 @@ top.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/test/core/dispatch/test_cores/test_medium_core.yaml b/test/core/dispatch/test_cores/test_medium_core.yaml index fe70dec9..a723a59e 100644 --- a/test/core/dispatch/test_cores/test_medium_core.yaml +++ b/test/core/dispatch/test_cores/test_medium_core.yaml @@ -1,6 +1,9 @@ + # -# Set up the pipeline for a 3-wide machine +# Set up the pipeline for a 2-wide machine # +#top.cpu: +# dispatch.num_to_dispatch: 2 top.extension.core_extensions: pipelines: @@ -10,14 +13,16 @@ top.extension.core_extensions: ["int"], ["float", "faddsub", "fmac"], ["float", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1", "2"], ["3", "4"], - ["5"] + ["5"], + ["6"] ] top.rename.scoreboards: @@ -25,16 +30,26 @@ top.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/dispatch/test_cores/test_small_core.yaml b/test/core/dispatch/test_cores/test_small_core.yaml index b154fa01..0d993d95 100644 --- a/test/core/dispatch/test_cores/test_small_core.yaml +++ b/test/core/dispatch/test_cores/test_small_core.yaml @@ -7,13 +7,15 @@ top.extension.core_extensions: [ ["int", "mul", "i2f", "cmov", "div"], ["float", "faddsub", "fmac", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1"], - ["2"] + ["2"], + ["3"] ] top.rename.scoreboards: @@ -21,14 +23,23 @@ top.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/issue_queue/test_cores/test_big_core.yaml b/test/core/issue_queue/test_cores/test_big_core.yaml index ec35e30b..4119f823 100644 --- a/test/core/issue_queue/test_cores/test_big_core.yaml +++ b/test/core/issue_queue/test_cores/test_big_core.yaml @@ -13,7 +13,8 @@ top.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -21,25 +22,37 @@ top.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/test/core/issue_queue/test_cores/test_big_core_full.yaml b/test/core/issue_queue/test_cores/test_big_core_full.yaml index 72e61334..fbac2fda 100644 --- a/test/core/issue_queue/test_cores/test_big_core_full.yaml +++ b/test/core/issue_queue/test_cores/test_big_core_full.yaml @@ -16,7 +16,8 @@ top.cpu.core0.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -24,25 +25,37 @@ top.cpu.core0.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.cpu.core0.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/test/core/l2cache/Testing/Temporary/LastTest.log b/test/core/l2cache/Testing/Temporary/LastTest.log new file mode 100644 index 00000000..8e504756 --- /dev/null +++ b/test/core/l2cache/Testing/Temporary/LastTest.log @@ -0,0 +1,3 @@ +Start testing: Sep 23 23:54 IST +---------------------------------------------------------- +End testing: Sep 23 23:54 IST diff --git a/test/core/l2cache/expected_output/hit_case.out.EXPECTED b/test/core/l2cache/expected_output/hit_case.out.EXPECTED index 6f77671c..eb450119 100644 --- a/test/core/l2cache/expected_output/hit_case.out.EXPECTED +++ b/test/core/l2cache/expected_output/hit_case.out.EXPECTED @@ -3,16 +3,16 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 12 14:22:32 2024 -#Elapsed: 0.002725s +#Start: Wednesday Wed Sep 25 22:41:27 2024 +#Elapsed: 0.002702s {0000000000 00000000 top.l2cache info} L2Cache: L2Cache construct: #4294967295 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to ICache : 8 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to DCache : 8 {0000000000 00000000 top.biu info} sendInitialCredits_: Sending initial credits to L2Cache : 32 {0000000000 00000000 top.icache info} ReceiveCredits_: Ack: '8' Received {0000000000 00000000 top.dcache info} ReceiveCredits_: Ack: '8' Received -{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' ' Requested -{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' ' Requested +{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' ' Requested +{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' ' Requested {0000000001 00000001 top.l2cache info} getCreditsFromBIU_: Credits received from BIU on the port : Current BIU credit available = 32 {0000000001 00000001 top.l2cache info} getReqFromDCache_: Request received from DCache on the port {0000000001 00000001 top.l2cache info} appendDCacheReqQueue_: Append DCache->L2Cache request queue! @@ -28,16 +28,16 @@ {0000000002 00000002 top.l2cache info} create_Req_: L2Cache->DCache : Credit is sent. {0000000003 00000003 top.dcache info} ReceiveCredits_: Ack: '1' Received {0000000003 00000003 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' +{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' {0000000011 00000011 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' {0000000012 00000012 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' {0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000012 00000012 top.l2cache info} appendBIUReqQueue_: Append L2Cache->BIU req queue {0000000012 00000012 top.l2cache info} handle_L2Cache_BIU_Req_: L2Cache Request sent to BIU : Current BIU credit available = 31 -{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' ' sinked -{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' +{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' ' sinked +{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' {0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000024 00000024 top.l2cache info} getCreditsFromBIU_: Credits received from BIU on the port : Current BIU credit available = 32 {0000000034 00000034 top.l2cache info} getRespFromBIU_: Response received from BIU on the port @@ -48,21 +48,21 @@ {0000000035 00000035 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU {0000000035 00000035 top.l2cache info} create_Req_: Request found in miss_pending_buffer_ with SrcUnit : DCACHE {0000000036 00000036 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : BIU -{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' +{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' {0000000044 00000044 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef {0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Reload Complete: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' {0000000045 00000045 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' {0000000045 00000045 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000045 00000045 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! -{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' ' Received -{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' +{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' ' Received +{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' {0000000046 00000046 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000046 00000046 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! -{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' ' Received -{0000000050 00000050 top.dcache info} req_inst_: Instruction: 'uid: 1 BEFORE_FETCH 0 pid: 2 'lw 5,3,4' ' Requested -{0000000050 00000050 top.icache info} req_inst_: Instruction: 'uid: 1 BEFORE_FETCH 0 pid: 2 'lw 5,3,4' ' Requested +{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' ' Received +{0000000050 00000050 top.dcache info} req_inst_: Instruction: 'uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3,4' ' Requested +{0000000050 00000050 top.icache info} req_inst_: Instruction: 'uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3,4' ' Requested {0000000051 00000051 top.l2cache info} getReqFromDCache_: Request received from DCache on the port {0000000051 00000051 top.l2cache info} appendDCacheReqQueue_: Append DCache->L2Cache request queue! {0000000051 00000051 top.l2cache info} getReqFromICache_: Request received from ICache on the port @@ -77,15 +77,15 @@ {0000000052 00000052 top.l2cache info} create_Req_: L2Cache->DCache : Credit is sent. {0000000053 00000053 top.dcache info} ReceiveCredits_: Ack: '1' Received {0000000053 00000053 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000061 00000061 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 1 BEFORE_FETCH 0 pid: 2 'lw 5,3,4' +{0000000061 00000061 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3,4' {0000000061 00000061 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000062 00000062 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 1 BEFORE_FETCH 0 pid: 2 'lw 5,3,4' +{0000000062 00000062 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3,4' {0000000062 00000062 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000062 00000062 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 1 BEFORE_FETCH 0 pid: 2 'lw 5,3,4' +{0000000062 00000062 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3,4' {0000000062 00000062 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000062 00000062 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! -{0000000063 00000063 top.icache info} ReceiveInst_: Instruction: 'uid: 1 BEFORE_FETCH 0 pid: 2 'lw 5,3,4' ' Received -{0000000063 00000063 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 1 BEFORE_FETCH 0 pid: 2 'lw 5,3,4' +{0000000063 00000063 top.icache info} ReceiveInst_: Instruction: 'uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3,4' ' Received +{0000000063 00000063 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3,4' {0000000063 00000063 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000063 00000063 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! -{0000000064 00000064 top.dcache info} ReceiveInst_: Instruction: 'uid: 1 BEFORE_FETCH 0 pid: 2 'lw 5,3,4' ' Received +{0000000064 00000064 top.dcache info} ReceiveInst_: Instruction: 'uid: 1 BEFORE_FETCH 0 pid: 2 uopid: 0 'lw 5,3,4' ' Received diff --git a/test/core/l2cache/expected_output/single_access.out.EXPECTED b/test/core/l2cache/expected_output/single_access.out.EXPECTED index eb45aa14..cf39d2be 100644 --- a/test/core/l2cache/expected_output/single_access.out.EXPECTED +++ b/test/core/l2cache/expected_output/single_access.out.EXPECTED @@ -3,16 +3,16 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 12 14:21:20 2024 -#Elapsed: 0.003237s +#Start: Wednesday Wed Sep 25 21:58:31 2024 +#Elapsed: 0.003535s {0000000000 00000000 top.l2cache info} L2Cache: L2Cache construct: #4294967295 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to ICache : 8 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to DCache : 8 {0000000000 00000000 top.biu info} sendInitialCredits_: Sending initial credits to L2Cache : 32 {0000000000 00000000 top.icache info} ReceiveCredits_: Ack: '8' Received {0000000000 00000000 top.dcache info} ReceiveCredits_: Ack: '8' Received -{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' ' Requested -{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' ' Requested +{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' ' Requested +{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' ' Requested {0000000001 00000001 top.l2cache info} getCreditsFromBIU_: Credits received from BIU on the port : Current BIU credit available = 32 {0000000001 00000001 top.l2cache info} getReqFromDCache_: Request received from DCache on the port {0000000001 00000001 top.l2cache info} appendDCacheReqQueue_: Append DCache->L2Cache request queue! @@ -28,16 +28,16 @@ {0000000002 00000002 top.l2cache info} create_Req_: L2Cache->DCache : Credit is sent. {0000000003 00000003 top.dcache info} ReceiveCredits_: Ack: '1' Received {0000000003 00000003 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' +{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' {0000000011 00000011 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' {0000000012 00000012 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' {0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000012 00000012 top.l2cache info} appendBIUReqQueue_: Append L2Cache->BIU req queue {0000000012 00000012 top.l2cache info} handle_L2Cache_BIU_Req_: L2Cache Request sent to BIU : Current BIU credit available = 31 -{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' ' sinked -{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' +{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' ' sinked +{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' {0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000024 00000024 top.l2cache info} getCreditsFromBIU_: Credits received from BIU on the port : Current BIU credit available = 32 {0000000034 00000034 top.l2cache info} getRespFromBIU_: Response received from BIU on the port @@ -48,16 +48,16 @@ {0000000035 00000035 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU {0000000035 00000035 top.l2cache info} create_Req_: Request found in miss_pending_buffer_ with SrcUnit : DCACHE {0000000036 00000036 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : BIU -{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' +{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' {0000000044 00000044 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef {0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Reload Complete: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' {0000000045 00000045 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' {0000000045 00000045 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000045 00000045 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! -{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' ' Received -{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' +{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' ' Received +{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' {0000000046 00000046 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000046 00000046 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! -{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 'sw 3' ' Received +{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 BEFORE_FETCH 0 pid: 1 uopid: 0 'sw 3' ' Received diff --git a/test/core/lsu/Lsu_test.cpp b/test/core/lsu/Lsu_test.cpp index 02f2f261..a71cfcf3 100644 --- a/test/core/lsu/Lsu_test.cpp +++ b/test/core/lsu/Lsu_test.cpp @@ -110,7 +110,7 @@ void runTest(int argc, char **argv) cls.runSimulator(&sim, 9); lsupipe_tester.test_inst_issue(*my_lsu, 2); // Loads operand dependency meet cls.runSimulator(&sim, 52); - lsupipe_tester.test_replay_issue_abort(*my_lsu, 2); // Loads operand dependency meet + lsupipe_tester.test_replay_issue_abort(*my_lsu, 3); // Loads operand dependency meet cls.runSimulator(&sim); } diff --git a/test/core/lsu/test_cores/test_big_core.yaml b/test/core/lsu/test_cores/test_big_core.yaml index e83682c6..4119f823 100644 --- a/test/core/lsu/test_cores/test_big_core.yaml +++ b/test/core/lsu/test_cores/test_big_core.yaml @@ -1,10 +1,6 @@ - # -# Set up the pipeline for a 2-wide machine +# Set up the pipeline for a 8-wide machine # -#top.cpu: -# dispatch.num_to_dispatch: 2 - top.extension.core_extensions: pipelines: [ @@ -17,7 +13,8 @@ top.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -25,25 +22,37 @@ top.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/test/core/lsu/test_cores/test_big_core_small_rename.yaml b/test/core/lsu/test_cores/test_big_core_small_rename.yaml index c0642231..bf1aaf72 100644 --- a/test/core/lsu/test_cores/test_big_core_small_rename.yaml +++ b/test/core/lsu/test_cores/test_big_core_small_rename.yaml @@ -4,10 +4,13 @@ # #top.cpu: # dispatch.num_to_dispatch: 2 - top: +top: rename.params.num_integer_renames: 34 rename.params.num_float_renames: 34 +# +# Set up the pipeline for a 8-wide machine +# top.extension.core_extensions: pipelines: [ @@ -20,7 +23,8 @@ top.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -28,25 +32,37 @@ top.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/lsu/test_cores/test_medium_core.yaml b/test/core/lsu/test_cores/test_medium_core.yaml index 979835d6..a723a59e 100644 --- a/test/core/lsu/test_cores/test_medium_core.yaml +++ b/test/core/lsu/test_cores/test_medium_core.yaml @@ -13,14 +13,16 @@ top.extension.core_extensions: ["int"], ["float", "faddsub", "fmac"], ["float", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1", "2"], ["3", "4"], - ["5"] + ["5"], + ["6"] ] top.rename.scoreboards: @@ -28,16 +30,26 @@ top.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/lsu/test_cores/test_medium_core_full.yaml b/test/core/lsu/test_cores/test_medium_core_full.yaml index a5d0ae4a..36e40fe3 100644 --- a/test/core/lsu/test_cores/test_medium_core_full.yaml +++ b/test/core/lsu/test_cores/test_medium_core_full.yaml @@ -21,14 +21,16 @@ top.cpu.core0.extension.core_extensions: ["int"], ["float", "faddsub", "fmac"], ["float", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1", "2"], ["3", "4"], - ["5"] + ["5"], + ["6"] ] top.cpu.core0.rename.scoreboards: @@ -36,16 +38,26 @@ top.cpu.core0.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/lsu/test_cores/test_small_core.yaml b/test/core/lsu/test_cores/test_small_core.yaml index 2704eaf3..0d993d95 100644 --- a/test/core/lsu/test_cores/test_small_core.yaml +++ b/test/core/lsu/test_cores/test_small_core.yaml @@ -1,22 +1,21 @@ - # # Set up the pipeline for a 2-wide machine # -#top.cpu: -# dispatch.num_to_dispatch: 2 top.extension.core_extensions: pipelines: [ ["int", "mul", "i2f", "cmov", "div"], ["float", "faddsub", "fmac", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1"], - ["2"] + ["2"], + ["3"] ] top.rename.scoreboards: @@ -24,14 +23,23 @@ top.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/lsu/test_cores/test_small_core_full.yaml b/test/core/lsu/test_cores/test_small_core_full.yaml index 35899e52..864ed793 100644 --- a/test/core/lsu/test_cores/test_small_core_full.yaml +++ b/test/core/lsu/test_cores/test_small_core_full.yaml @@ -24,14 +24,16 @@ top.cpu.core0.extension.core_extensions: pipelines: [ ["int", "mul", "i2f", "cmov", "div"], - ["float", "faddsub", "fmac", "f2i"], - ["br"] + ["float", "faddsub", "fmac", "f2i"], + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1"], - ["2"] + ["2"], + ["3"] ] top.cpu.core0.rename.scoreboards: @@ -39,14 +41,23 @@ top.cpu.core0.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] diff --git a/test/core/rename/expected_output/big_core.out.EXPECTED b/test/core/rename/expected_output/big_core.out.EXPECTED index 4af48d33..f954c737 100644 --- a/test/core/rename/expected_output/big_core.out.EXPECTED +++ b/test/core/rename/expected_output/big_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 5 13:40:26 2024 -#Elapsed: 0.012103s +#Start: Tuesday Tue Jul 16 09:09:57 2024 +#Elapsed: 0.003622s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: DIViq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq1 @@ -17,6 +17,10 @@ {0000000000 00000000 top.dispatch info} Dispatch: mapping target: FMACiq3 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: F2Iiq3 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: BRiq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VSETiq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VDIViq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VMULiq5 {0000000000 00000000 top.execute.exe0 info} ExecutePipe: ExecutePipe construct: #0 {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 @@ -27,6 +31,7 @@ {0000000000 00000000 top.execute.exe7 info} ExecutePipe: ExecutePipe construct: #7 {0000000000 00000000 top.execute.exe8 info} ExecutePipe: ExecutePipe construct: #8 {0000000000 00000000 top.execute.exe9 info} ExecutePipe: ExecutePipe construct: #9 +{0000000000 00000000 top.execute.exe10 info} ExecutePipe: ExecutePipe construct: #10 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 30 credits, total: 30 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 @@ -41,10 +46,12 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq4 got 8 credits, total: 8 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} receiveCredits_: iq5 got 8 credits, total: 8 +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -52,43 +59,43 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' Bits needed:[0,2] -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' to iq1 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 uopid: 0 'mul 13,12,11' to iq1 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 'sub 14,13,12' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 uopid: 0 'sub 14,13,12' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard diff --git a/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED b/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED index 98fa8906..395d3a52 100644 --- a/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED +++ b/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 5 13:38:59 2024 -#Elapsed: 0.005573s +#Start: Tuesday Tue Jul 16 09:09:57 2024 +#Elapsed: 0.00475s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: DIViq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq1 @@ -17,6 +17,10 @@ {0000000000 00000000 top.dispatch info} Dispatch: mapping target: FMACiq3 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: F2Iiq3 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: BRiq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VSETiq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VDIViq5 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VMULiq5 {0000000000 00000000 top.execute.exe0 info} ExecutePipe: ExecutePipe construct: #0 {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 @@ -27,6 +31,7 @@ {0000000000 00000000 top.execute.exe7 info} ExecutePipe: ExecutePipe construct: #7 {0000000000 00000000 top.execute.exe8 info} ExecutePipe: ExecutePipe construct: #8 {0000000000 00000000 top.execute.exe9 info} ExecutePipe: ExecutePipe construct: #9 +{0000000000 00000000 top.execute.exe10 info} ExecutePipe: ExecutePipe construct: #10 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 30 credits, total: 30 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 @@ -41,10 +46,12 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq4 got 8 credits, total: 8 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} receiveCredits_: iq5 got 8 credits, total: 8 +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -52,39 +59,39 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' Bits needed:[0,2] -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' to iq1 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 uopid: 0 'mul 13,12,11' to iq1 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NO_RENAMES diff --git a/test/core/rename/expected_output/medium_core.out.EXPECTED b/test/core/rename/expected_output/medium_core.out.EXPECTED index e0bf8a0f..5eb25f2f 100644 --- a/test/core/rename/expected_output/medium_core.out.EXPECTED +++ b/test/core/rename/expected_output/medium_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 5 13:39:26 2024 -#Elapsed: 0.013707s +#Start: Tuesday Tue Jul 16 09:09:57 2024 +#Elapsed: 0.004244s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -16,12 +16,17 @@ {0000000000 00000000 top.dispatch info} Dispatch: mapping target: FMACiq2 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: F2Iiq2 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: BRiq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VSETiq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VDIViq4 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VMULiq4 {0000000000 00000000 top.execute.exe0 info} ExecutePipe: ExecutePipe construct: #0 {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 {0000000000 00000000 top.execute.exe3 info} ExecutePipe: ExecutePipe construct: #3 {0000000000 00000000 top.execute.exe4 info} ExecutePipe: ExecutePipe construct: #4 {0000000000 00000000 top.execute.exe5 info} ExecutePipe: ExecutePipe construct: #5 +{0000000000 00000000 top.execute.exe6 info} ExecutePipe: ExecutePipe construct: #6 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 30 credits, total: 30 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 @@ -34,10 +39,12 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq3 got 8 credits, total: 8 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} receiveCredits_: iq4 got 8 credits, total: 8 +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -45,43 +52,43 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' Bits needed:[0,2] -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' to iq0 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 uopid: 0 'mul 13,12,11' to iq0 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 'sub 14,13,12' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 uopid: 0 'sub 14,13,12' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard diff --git a/test/core/rename/expected_output/small_core.out.EXPECTED b/test/core/rename/expected_output/small_core.out.EXPECTED index 0d97e3a5..37d343de 100644 --- a/test/core/rename/expected_output/small_core.out.EXPECTED +++ b/test/core/rename/expected_output/small_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Monday Mon Feb 5 13:39:15 2024 -#Elapsed: 0.019968s +#Start: Tuesday Tue Jul 16 09:09:57 2024 +#Elapsed: 0.004802s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -15,9 +15,14 @@ {0000000000 00000000 top.dispatch info} Dispatch: mapping target: FMACiq1 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: F2Iiq1 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: BRiq2 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VINTiq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VSETiq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VDIViq3 +{0000000000 00000000 top.dispatch info} Dispatch: mapping target: VMULiq3 {0000000000 00000000 top.execute.exe0 info} ExecutePipe: ExecutePipe construct: #0 {0000000000 00000000 top.execute.exe1 info} ExecutePipe: ExecutePipe construct: #1 {0000000000 00000000 top.execute.exe2 info} ExecutePipe: ExecutePipe construct: #2 +{0000000000 00000000 top.execute.exe3 info} ExecutePipe: ExecutePipe construct: #3 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} robCredits_: ROB got 30 credits, total: 30 {0000000000 00000000 top.dispatch info} receiveCredits_: lsu got 10 credits, total: 10 @@ -28,10 +33,12 @@ {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.dispatch info} receiveCredits_: iq2 got 8 credits, total: 8 {0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process +{0000000000 00000000 top.dispatch info} receiveCredits_: iq3 got 8 credits, total: 8 +{0000000000 00000000 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -39,43 +46,43 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' Bits needed:[0,2] -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 3 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 'mul 13,12,11' to iq0 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 uopid: 0 'mul 13,12,11' to iq0 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 'sub 14,13,12' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 uopid: 0 'sub 14,13,12' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard diff --git a/test/core/rename/test_cores/test_big_core.yaml b/test/core/rename/test_cores/test_big_core.yaml index ec35e30b..4119f823 100644 --- a/test/core/rename/test_cores/test_big_core.yaml +++ b/test/core/rename/test_cores/test_big_core.yaml @@ -13,7 +13,8 @@ top.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -21,25 +22,37 @@ top.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/test/core/rename/test_cores/test_big_core_full.yaml b/test/core/rename/test_cores/test_big_core_full.yaml index 66c1ec15..18315cad 100644 --- a/test/core/rename/test_cores/test_big_core_full.yaml +++ b/test/core/rename/test_cores/test_big_core_full.yaml @@ -13,7 +13,8 @@ top.cpu.core0.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -21,25 +22,37 @@ top.cpu.core0.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.cpu.core0.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/test/core/rename/test_cores/test_big_core_small_rename.yaml b/test/core/rename/test_cores/test_big_core_small_rename.yaml index dcbcfb37..bf1aaf72 100644 --- a/test/core/rename/test_cores/test_big_core_small_rename.yaml +++ b/test/core/rename/test_cores/test_big_core_small_rename.yaml @@ -23,7 +23,8 @@ top.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -31,25 +32,37 @@ top.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/rename/test_cores/test_big_core_small_rename_full.yaml b/test/core/rename/test_cores/test_big_core_small_rename_full.yaml index 07581a69..9423dee8 100644 --- a/test/core/rename/test_cores/test_big_core_small_rename_full.yaml +++ b/test/core/rename/test_cores/test_big_core_small_rename_full.yaml @@ -23,7 +23,8 @@ top.cpu.core0.extension.core_extensions: ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ @@ -31,25 +32,37 @@ top.cpu.core0.extension.core_extensions: ["2", "3"], ["4", "5"], ["6", "7"], - ["8", "9"] + ["8", "9"], + ["10"] ] top.cpu.core0.rename.scoreboards: # From # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], - ["lsu", 1, 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1, 1], - ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/rename/test_cores/test_medium_core.yaml b/test/core/rename/test_cores/test_medium_core.yaml index 979835d6..a723a59e 100644 --- a/test/core/rename/test_cores/test_medium_core.yaml +++ b/test/core/rename/test_cores/test_medium_core.yaml @@ -13,14 +13,16 @@ top.extension.core_extensions: ["int"], ["float", "faddsub", "fmac"], ["float", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1", "2"], ["3", "4"], - ["5"] + ["5"], + ["6"] ] top.rename.scoreboards: @@ -28,16 +30,26 @@ top.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/rename/test_cores/test_medium_core_full.yaml b/test/core/rename/test_cores/test_medium_core_full.yaml index ba3c5c0f..a4fd0849 100644 --- a/test/core/rename/test_cores/test_medium_core_full.yaml +++ b/test/core/rename/test_cores/test_medium_core_full.yaml @@ -23,14 +23,16 @@ top.cpu.core0.extension.core_extensions: ["int"], ["float", "faddsub", "fmac"], ["float", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1", "2"], ["3", "4"], - ["5"] + ["5"], + ["6"] ] top.cpu.core0.rename.scoreboards: @@ -38,16 +40,26 @@ top.cpu.core0.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2", "iq3"], - ["lsu", 1, 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1, 1], - ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"], + ["lsu", 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/rename/test_cores/test_small_core.yaml b/test/core/rename/test_cores/test_small_core.yaml index b154fa01..0d993d95 100644 --- a/test/core/rename/test_cores/test_small_core.yaml +++ b/test/core/rename/test_cores/test_small_core.yaml @@ -7,13 +7,15 @@ top.extension.core_extensions: [ ["int", "mul", "i2f", "cmov", "div"], ["float", "faddsub", "fmac", "f2i"], - ["br"] + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1"], - ["2"] + ["2"], + ["3"] ] top.rename.scoreboards: @@ -21,14 +23,23 @@ top.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/rename/test_cores/test_small_core_full.yaml b/test/core/rename/test_cores/test_small_core_full.yaml index 4a947668..0c0e29d2 100644 --- a/test/core/rename/test_cores/test_small_core_full.yaml +++ b/test/core/rename/test_cores/test_small_core_full.yaml @@ -21,14 +21,16 @@ top.cpu.core0.extension.core_extensions: pipelines: [ ["int", "mul", "i2f", "cmov", "div"], - ["float", "faddsub", "fmac", "f2i"], - ["br"] + ["float", "faddsub", "fmac", "f2i"], + ["br"], + ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: [ ["0"], ["1"], - ["2"] + ["2"], + ["3"] ] top.cpu.core0.rename.scoreboards: @@ -36,14 +38,23 @@ top.cpu.core0.rename.scoreboards: # | # V integer.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] float.params.latency_matrix: | - [["", "lsu", "iq0", "iq1", "iq2"], - ["lsu", 1, 1, 1, 1], - ["iq0", 1, 1, 1, 1], - ["iq1", 1, 1, 1, 1], - ["iq2", 1, 1, 1, 1]] \ No newline at end of file + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3"], + ["lsu", 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1]] \ No newline at end of file diff --git a/test/core/vector/CMakeLists.txt b/test/core/vector/CMakeLists.txt new file mode 100644 index 00000000..69e62a25 --- /dev/null +++ b/test/core/vector/CMakeLists.txt @@ -0,0 +1,31 @@ +project(Vector_test) + +add_executable(Vector_test Vector_test.cpp ${SIM_BASE}/sim/OlympiaSim.cpp) +target_link_libraries(Vector_test core common_test ${STF_LINK_LIBS} mavis SPARTA::sparta) + +file(CREATE_LINK ${SIM_BASE}/mavis/json ${CMAKE_CURRENT_BINARY_DIR}/mavis_isa_files SYMBOLIC) +file(CREATE_LINK ${SIM_BASE}/arches ${CMAKE_CURRENT_BINARY_DIR}/arches SYMBOLIC) + +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/test_cores ${CMAKE_CURRENT_BINARY_DIR}/test_cores SYMBOLIC) + +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/vsetivli_vaddvv_e8m4.json ${CMAKE_CURRENT_BINARY_DIR}/vsetivli_vaddvv_e8m4.json SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/vsetvli_vaddvv_e32m1ta.json ${CMAKE_CURRENT_BINARY_DIR}/vsetvli_vaddvv_e32m1ta.json SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/vsetvl_vaddvv_e64m1ta.json ${CMAKE_CURRENT_BINARY_DIR}/vsetvl_vaddvv_e64m1ta.json SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/vsetivli_vaddvv_tail_e8m8ta.json ${CMAKE_CURRENT_BINARY_DIR}/vsetivli_vaddvv_tail_e8m8ta.json SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/multiple_vset.json ${CMAKE_CURRENT_BINARY_DIR}/multiple_vset.json SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/vmulvx_e8m4.json ${CMAKE_CURRENT_BINARY_DIR}/vmulvx_e8m4.json SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/vwmulvv_e8m4.json ${CMAKE_CURRENT_BINARY_DIR}/vwmulvv_e8m4.json SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/vmseqvv_e8m4.json ${CMAKE_CURRENT_BINARY_DIR}/vmseqvv_e8m4.json SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/vrgather.json ${CMAKE_CURRENT_BINARY_DIR}/vrgather.json SYMBOLIC) + + + +sparta_named_test(Vector_test_vsetivli Vector_test -l top info vsetivli.out -c test_cores/test_big_core.yaml --input-file vsetivli_vaddvv_e8m4.json) +sparta_named_test(Vector_test_vsetvli Vector_test -l top info vsetvli.out -c test_cores/test_big_core.yaml --input-file vsetvli_vaddvv_e32m1ta.json) +sparta_named_test(Vector_test_vsetvl Vector_test -l top info vsetvl.out -c test_cores/test_big_core.yaml --input-file vsetvl_vaddvv_e64m1ta.json) +sparta_named_test(Vector_test_vsetivli_tail Vector_test -l top info vsetivli_tail.out -c test_cores/test_big_core.yaml --input-file vsetivli_vaddvv_tail_e8m8ta.json) +sparta_named_test(Vector_test_multiple_vset Vector_test -l top info mulitple_vset.out -c test_cores/test_big_core.yaml --input-file multiple_vset.json) +sparta_named_test(Vector_test_vmulvx Vector_test -l top info vmulvx.out -c test_cores/test_big_core.yaml --input-file vmulvx_e8m4.json) +sparta_named_test(Vector_test_vmulvv Vector_test -l top info vmulvv.out -c test_cores/test_big_core.yaml --input-file vwmulvv_e8m4.json) +sparta_named_test(Vector_test_vmseqvv Vector_test -l top info vmseqvv.out -c test_cores/test_big_core.yaml --input-file vmseqvv_e8m4.json) +sparta_named_test(Vector_unsupported_test Vector_test -l top info unsupported.out -c test_cores/test_big_core.yaml --input-file vrgather.json) diff --git a/test/core/vector/Vector_test.cpp b/test/core/vector/Vector_test.cpp new file mode 100644 index 00000000..1379fd19 --- /dev/null +++ b/test/core/vector/Vector_test.cpp @@ -0,0 +1,308 @@ + +#include "CPUFactory.hpp" +#include "CoreUtils.hpp" +#include "Dispatch.hpp" +#include "MavisUnit.hpp" +#include "OlympiaAllocators.hpp" +#include "OlympiaSim.hpp" +#include "IssueQueue.hpp" +#include "test/core/dispatch/Dispatch_test.hpp" + +#include "sparta/app/CommandLineSimulator.hpp" +#include "sparta/app/Simulation.hpp" +#include "sparta/events/UniqueEvent.hpp" +#include "sparta/kernel/Scheduler.hpp" +#include "sparta/report/Report.hpp" +#include "sparta/resources/Buffer.hpp" +#include "sparta/simulation/ClockManager.hpp" +#include "sparta/sparta.hpp" +#include "sparta/statistics/StatisticSet.hpp" +#include "sparta/utils/SpartaSharedPointer.hpp" +#include "sparta/utils/SpartaTester.hpp" + +#include +#include +#include +#include +#include +TEST_INIT + +//////////////////////////////////////////////////////////////////////////////// +// Set up the Mavis decoder globally for the testing +olympia::InstAllocator inst_allocator(2000, 1000); + +const char USAGE[] = "Usage:\n" + " \n" + "\n"; + +sparta::app::DefaultValues DEFAULTS; + +class olympia::DecodeTester +{ +public: + DecodeTester(olympia::Decode * decode) : + decode_(decode) + {} + + void test_waiting_on_vset() + { + EXPECT_TRUE(decode_->waiting_on_vset_ == true); + } + + void test_waiting_on_vset(const bool expected_val) + { + EXPECT_TRUE(decode_->waiting_on_vset_ == expected_val); + } + + void test_vl(const uint32_t expected_vl) + { + EXPECT_TRUE(decode_->vector_config_->getVL() == expected_vl); + } + + void test_sew(const uint32_t expected_sew) + { + EXPECT_TRUE(decode_->vector_config_->getSEW() == expected_sew); + } + + void test_lmul(const uint32_t expected_lmul) + { + EXPECT_TRUE(decode_->vector_config_->getLMUL() == expected_lmul); + } + + void test_vlmax(const uint32_t expected_vlmax) + { + EXPECT_TRUE(decode_->vector_config_->getVLMAX() == expected_vlmax); + } + + void test_vta(const bool expected_vta) + { + EXPECT_TRUE(decode_->vector_config_->getVTA() == expected_vta); + } + +private: + olympia::Decode * decode_; +}; + +class olympia::ROBTester +{ +public: + ROBTester(olympia::ROB * rob) : + rob_(rob) + {} + + void test_num_insts_retired(const uint64_t expected_num_insts_retired) + { + EXPECT_TRUE(rob_->num_retired_ == expected_num_insts_retired); + } + + void test_num_uops_retired(const uint64_t expected_num_uops_retired) + { + EXPECT_TRUE(rob_->num_uops_retired_ == expected_num_uops_retired); + } + + void test_last_inst_has_tail(const bool expected_tail) + { + EXPECT_TRUE(rob_->last_inst_retired_ != nullptr); + EXPECT_TRUE(rob_->last_inst_retired_->hasTail() == expected_tail); + } + +private: + olympia::ROB * rob_; +}; + +void runTests(int argc, char **argv) + { + DEFAULTS.auto_summary_default = "off"; + std::string input_file; + + sparta::app::CommandLineSimulator cls(USAGE, DEFAULTS); + auto &app_opts = cls.getApplicationOptions(); + app_opts.add_options() + ("input-file", + sparta::app::named_value("INPUT_FILE", &input_file)->default_value(""), + "Provide a JSON instruction stream", + "Provide a JSON file with instructions to run through Execute"); + + int err_code = 0; + if (!cls.parse(argc, argv, err_code)) + { + sparta_assert(false, + "Command line parsing failed"); // Any errors already printed to cerr + } + + sparta::Scheduler scheduler; + uint32_t num_cores = 1; + uint64_t ilimit = 0; + bool show_factories = false; + OlympiaSim sim("simple", + scheduler, + num_cores, + input_file, + ilimit, + show_factories); + sparta::RootTreeNode *root_node = sim.getRoot(); + cls.populateSimulation(&sim); + + olympia::Decode *my_decode = \ + root_node->getChild("cpu.core0.decode")->getResourceAs(); + olympia::DecodeTester decode_tester {my_decode}; + + olympia::ROB *my_rob = \ + root_node->getChild("cpu.core0.rob")->getResourceAs(); + olympia::ROBTester rob_tester {my_rob}; + + if (input_file.find("vsetivli_vaddvv_e8m4.json") != std::string::npos) + { + // Test Decode (defaults) + decode_tester.test_lmul(1); + decode_tester.test_vl(128); + decode_tester.test_vta(false); + decode_tester.test_sew(8); + decode_tester.test_vlmax(128); + + cls.runSimulator(&sim); + + // Test after vsetivli + decode_tester.test_waiting_on_vset(false); + decode_tester.test_lmul(4); + decode_tester.test_vl(512); + decode_tester.test_vta(false); + decode_tester.test_sew(8); + decode_tester.test_vlmax(512); + + // Test Retire + rob_tester.test_num_insts_retired(2); + // vset + 4 vadd.vv uops + rob_tester.test_num_uops_retired(5); + rob_tester.test_last_inst_has_tail(false); + } + else if(input_file.find("vsetvli_vaddvv_e32m1ta.json") != std::string::npos) + { + cls.runSimulator(&sim); + + // Test Decode + decode_tester.test_waiting_on_vset(false); + decode_tester.test_lmul(1); + decode_tester.test_vl(32); + decode_tester.test_vta(true); + decode_tester.test_sew(32); + decode_tester.test_vlmax(32); + + // Test Retire + rob_tester.test_num_insts_retired(2); + // vset + 1 vadd.vv uop + rob_tester.test_num_uops_retired(2); + rob_tester.test_last_inst_has_tail(false); + } + else if(input_file.find("vsetvl_vaddvv_e64m1ta.json") != std::string::npos) + { + cls.runSimulator(&sim); + + // Test Decode + decode_tester.test_waiting_on_vset(false); + decode_tester.test_lmul(1); + decode_tester.test_vl(16); + decode_tester.test_vta(true); + decode_tester.test_sew(64); + decode_tester.test_vlmax(16); + + // Test Retire + rob_tester.test_num_insts_retired(2); + // vset + 1 vadd.vv uop + rob_tester.test_num_uops_retired(2); + rob_tester.test_last_inst_has_tail(false); + } + else if(input_file.find("vsetivli_vaddvv_tail_e8m8ta.json") != std::string::npos) + { + cls.runSimulator(&sim); + + // Test Decode + decode_tester.test_lmul(8); + decode_tester.test_vl(900); + decode_tester.test_vta(false); + decode_tester.test_sew(8); + decode_tester.test_vlmax(1024); + + // Test Retire + rob_tester.test_num_insts_retired(2); + // vset + 8 vadd.vv uop + rob_tester.test_num_uops_retired(9); + rob_tester.test_last_inst_has_tail(true); + } + else if(input_file.find("multiple_vset.json") != std::string::npos) + { + cls.runSimulator(&sim); + + // Test Decode (last vset) + decode_tester.test_waiting_on_vset(false); + decode_tester.test_lmul(8); + decode_tester.test_vl(1024); + decode_tester.test_vta(false); + decode_tester.test_sew(8); + decode_tester.test_vlmax(1024); + + // Test Retire + rob_tester.test_num_insts_retired(8); + // vset + 1 vadd.vv + vset + 2 vadd.vv + vset + 4 vadd.vv uop + vset + 8 vadd.vv + rob_tester.test_num_uops_retired(19); + } + else if(input_file.find("vmulvx_e8m4.json") != std::string::npos) + { + cls.runSimulator(&sim); + + // Test Retire + rob_tester.test_num_insts_retired(3); + // vadd + 4 vmul.vx uop + rob_tester.test_num_uops_retired(6); + rob_tester.test_last_inst_has_tail(false); + + // TODO: Test source values for all uops + } + else if(input_file.find("vwmulvv_e8m4.json") != std::string::npos) + { + cls.runSimulator(&sim); + + // Test Retire + rob_tester.test_num_insts_retired(2); + // vadd + 8 vwmul.vv uop + rob_tester.test_num_uops_retired(9); + rob_tester.test_last_inst_has_tail(false); + + // TODO: Test destination values for all uops + } + else if(input_file.find("vmseqvv_e8m4.json") != std::string::npos) + { + cls.runSimulator(&sim); + + // Test Retire + rob_tester.test_num_insts_retired(2); + // vadd + 4 vmseq.vv uops + rob_tester.test_num_uops_retired(5); + rob_tester.test_last_inst_has_tail(false); + + // TODO: Test destination values for all uops + } + else if(input_file.find("vrgather.json") != std::string::npos) + { + // Unsupported vector instructions are expected to make the simulator to throw + bool sparta_exception_fired = false; + try { + cls.runSimulator(&sim); + } catch (const sparta::SpartaException& ex) { + sparta_exception_fired = true; + } + EXPECT_TRUE(sparta_exception_fired); + } + else + { + sparta_assert(false, "Invalid input file: " << input_file); + } +} + +int main(int argc, char **argv) + { + runTests(argc, argv); + + REPORT_ERROR; + return (int)ERROR_CODE; +} diff --git a/test/core/vector/multiple_vset.json b/test/core/vector/multiple_vset.json new file mode 100644 index 00000000..b4a08942 --- /dev/null +++ b/test/core/vector/multiple_vset.json @@ -0,0 +1,54 @@ +[ + { + "mnemonic": "vsetvli", + "rs1": 0, + "vtype": "0x10", + "rd": 1, + "vl": 128 + }, + { + "mnemonic": "vadd.vv", + "vs1": 8, + "vs2": 9, + "vd": 10 + }, + { + "mnemonic": "vsetvli", + "rs1": 0, + "vtype": "0x1", + "rd": 1, + "vl": 256 + }, + { + "mnemonic": "vadd.vv", + "vs1": 8, + "vs2": 10, + "vd": 12 + }, + { + "mnemonic": "vsetvli", + "rs1": 0, + "vtype": "0x2", + "rd": 1, + "vl": 512 + }, + { + "mnemonic": "vadd.vv", + "vs1": 8, + "vs2": 12, + "vd": 16 + }, + { + "mnemonic": "vsetvli", + "rs1": 2, + "vtype": "0x3", + "rd": 1, + "vl": 1024 + }, + { + "mnemonic": "vadd.vv", + "vs1": 8, + "vs2": 16, + "vd": 24 + } +] diff --git a/test/core/vector/test_cores/test_big_core.yaml b/test/core/vector/test_cores/test_big_core.yaml new file mode 100644 index 00000000..2ea2b8d1 --- /dev/null +++ b/test/core/vector/test_cores/test_big_core.yaml @@ -0,0 +1,69 @@ +# +# Set up the pipeline for a 8-wide machine +# +top.cpu.core0: + fetch.params.num_to_fetch: 8 + decode.params.num_to_decode: 3 + rename.params.num_integer_renames: 64 + rename.params.num_float_renames: 64 + rename.params.num_vector_renames: 64 + dispatch.params.num_to_dispatch: 8 + rob.params.num_to_retire: 8 + dcache.params: + l1_size_kb: 64 + +top.cpu.core0.extension.core_extensions: + pipelines: + [ + ["int"], # alu0 + ["int", "div"], # alu1 + ["int", "mul"], + ["int", "mul", "i2f", "cmov"], + ["int"], + ["int"], + ["float", "faddsub", "fmac"], + ["float", "f2i"], + ["br"], + ["br"], + ["vint", "vset", "vdiv", "vmul"] + ] + issue_queue_to_pipe_map: + [ + ["0", "1"], + ["2", "3"], + ["4", "5"], + ["6", "7"], + ["8", "9"], + ["10"] + ] +top.cpu.core0.rename.scoreboards: + # From + # | + # V + integer.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + float.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] + vector.params.latency_matrix: | + [["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"], + ["lsu", 1, 1, 1, 1, 1, 1, 1], + ["iq0", 1, 1, 1, 1, 1, 1, 1], + ["iq1", 1, 1, 1, 1, 1, 1, 1], + ["iq2", 1, 1, 1, 1, 1, 1, 1], + ["iq3", 1, 1, 1, 1, 1, 1, 1], + ["iq4", 1, 1, 1, 1, 1, 1, 1], + ["iq5", 1, 1, 1, 1, 1, 1, 1]] diff --git a/test/core/vector/vmaccvv_e8m4.json b/test/core/vector/vmaccvv_e8m4.json new file mode 100644 index 00000000..2e456cb5 --- /dev/null +++ b/test/core/vector/vmaccvv_e8m4.json @@ -0,0 +1,22 @@ +[ + { + "mnemonic": "vsetivli", + "rs1": 5, + "rd": 1, + "vtype": "0x2", + "vl": 512, + "vta": 0 + }, + { + "mnemonic": "vmacc.vv", + "vd": 0, + "vs1": 8, + "vs2": 16 + }, + { + "mnemonic": "vwmacc.vv", + "vd": 0, + "vs1": 8, + "vs2": 16 + } +] diff --git a/test/core/vector/vmseqvv_e8m4.json b/test/core/vector/vmseqvv_e8m4.json new file mode 100644 index 00000000..c8651d58 --- /dev/null +++ b/test/core/vector/vmseqvv_e8m4.json @@ -0,0 +1,16 @@ +[ + { + "mnemonic": "vsetivli", + "rs1": 5, + "rd": 1, + "vtype": "0x2", + "vl": 512, + "vta": 0 + }, + { + "mnemonic": "vmseq.vv", + "vd": 12, + "vs2": 8, + "vs1": 4 + } +] diff --git a/test/core/vector/vmulvx_e8m4.json b/test/core/vector/vmulvx_e8m4.json new file mode 100644 index 00000000..c6f97e61 --- /dev/null +++ b/test/core/vector/vmulvx_e8m4.json @@ -0,0 +1,22 @@ +[ + { + "mnemonic": "vsetivli", + "rs1": 5, + "rd": 1, + "vtype": "0x2", + "vl": 512, + "vta": 0 + }, + { + "mnemonic": "add", + "rs1": 1, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "vmul.vx", + "vd": 5, + "vs2": 4, + "rs1": 3 + } +] diff --git a/test/core/vector/vrgather.json b/test/core/vector/vrgather.json new file mode 100644 index 00000000..6d67a00d --- /dev/null +++ b/test/core/vector/vrgather.json @@ -0,0 +1,16 @@ +[ + { + "mnemonic": "vsetvl", + "rs1": 0, + "vtype": "0x18", + "rd": 1, + "vl": 512, + "vta": 1 + }, + { + "mnemonic": "vrgather.vv", + "vs1": 10, + "vs2": 17, + "vd": 3 + } +] diff --git a/test/core/vector/vsetivli_vaddvv_e8m4.json b/test/core/vector/vsetivli_vaddvv_e8m4.json new file mode 100644 index 00000000..dde1a6ba --- /dev/null +++ b/test/core/vector/vsetivli_vaddvv_e8m4.json @@ -0,0 +1,16 @@ +[ + { + "mnemonic": "vsetivli", + "rs1": 5, + "rd": 1, + "vtype": "0x2", + "vl": 512, + "vta": 0 + }, + { + "mnemonic": "vadd.vv", + "vs1": 10, + "vs2": 17, + "vd": 3 + } +] diff --git a/test/core/vector/vsetivli_vaddvv_tail_e8m8ta.json b/test/core/vector/vsetivli_vaddvv_tail_e8m8ta.json new file mode 100644 index 00000000..6855a96f --- /dev/null +++ b/test/core/vector/vsetivli_vaddvv_tail_e8m8ta.json @@ -0,0 +1,16 @@ +[ + { + "mnemonic": "vsetivli", + "rs1": 5, + "rd": 1, + "vtype": "0x3", + "vl": 900, + "vta": 0 + }, + { + "mnemonic": "vadd.vv", + "vs1": 10, + "vs2": 17, + "vd": 3 + } +] diff --git a/test/core/vector/vsetvl_vaddvv_e64m1ta.json b/test/core/vector/vsetvl_vaddvv_e64m1ta.json new file mode 100644 index 00000000..22e5a95d --- /dev/null +++ b/test/core/vector/vsetvl_vaddvv_e64m1ta.json @@ -0,0 +1,16 @@ +[ + { + "mnemonic": "vsetvl", + "rs1": 0, + "vtype": "0x18", + "rd": 1, + "vl": 16, + "vta": 1 + }, + { + "mnemonic": "vadd.vv", + "vs1": 10, + "vs2": 17, + "vd": 3 + } +] diff --git a/test/core/vector/vsetvli_vaddvv_e32m1ta.json b/test/core/vector/vsetvli_vaddvv_e32m1ta.json new file mode 100644 index 00000000..14749801 --- /dev/null +++ b/test/core/vector/vsetvli_vaddvv_e32m1ta.json @@ -0,0 +1,16 @@ +[ + { + "mnemonic": "vsetvli", + "rs1": 2, + "vtype": "0x10", + "rd": 1, + "vl": 32, + "vta": 1 + }, + { + "mnemonic": "vadd.vv", + "vs1": 10, + "vs2": 17, + "vd": 3 + } +] diff --git a/test/core/vector/vwmulvv_e8m4.json b/test/core/vector/vwmulvv_e8m4.json new file mode 100644 index 00000000..5b094e56 --- /dev/null +++ b/test/core/vector/vwmulvv_e8m4.json @@ -0,0 +1,16 @@ +[ + { + "mnemonic": "vsetivli", + "rs1": 5, + "rd": 1, + "vtype": "0x2", + "vl": 512, + "vta": 0 + }, + { + "mnemonic": "vwmul.vv", + "vd": 12, + "vs2": 8, + "vs1": 4 + } +] diff --git a/test/fusion/CMakeLists.txt b/test/fusion/CMakeLists.txt new file mode 100644 index 00000000..c643c747 --- /dev/null +++ b/test/fusion/CMakeLists.txt @@ -0,0 +1,21 @@ +project(olympia_test) +sparta_regress (olympia) + +file(CREATE_LINK ${SIM_BASE}/reports + ${CMAKE_CURRENT_BINARY_DIR}/reports SYMBOLIC) + +file(CREATE_LINK ${SIM_BASE}/arches + ${CMAKE_CURRENT_BINARY_DIR}/arches SYMBOLIC) + +file(CREATE_LINK ${SIM_BASE}/mavis/json + ${CMAKE_CURRENT_BINARY_DIR}/mavis_isa_files SYMBOLIC) + +file(CREATE_LINK ${SIM_BASE}/traces + ${CMAKE_CURRENT_BINARY_DIR}/traces SYMBOLIC) + +sparta_named_test(fusion_test olympia -i 1M + -l top debug debug.log + --arch-search-dir arches + --arch fusion + --report-all fusion.rpt text + --workload traces/dhry_riscv.zstf) diff --git a/traces/example_json.json b/traces/example_json.json index 9110a8e1..241cad88 100644 --- a/traces/example_json.json +++ b/traces/example_json.json @@ -17,6 +17,12 @@ "rs2": 3, "rd": 5 }, + { + "mnemonic": "csrrw", + "rs1": 1, + "rd": 4, + "csr": 9 + }, { "mnemonic": "lw", "rs1": 4, From 7e225d172bb10584a2e621d56690d2f1c6886642 Mon Sep 17 00:00:00 2001 From: Shobhit Date: Tue, 1 Oct 2024 12:50:25 +0530 Subject: [PATCH 09/14] Removed extra files --- .idea/.gitignore | 8 - .idea/codeStyles/Project.xml | 32 - .idea/codeStyles/codeStyleConfig.xml | 5 - .idea/editor.xml | 15 - .idea/misc.xml | 11 - .idea/modules.xml | 8 - .idea/riscv-perf-model.iml | 2 - .idea/vcs.xml | 10 - .../.cmake/api/v1/query/cache-v2 | 0 .../.cmake/api/v1/query/cmakeFiles-v1 | 0 .../.cmake/api/v1/query/codemodel-v2 | 0 .../.cmake/api/v1/query/toolchains-v1 | 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10) -# define COMPILER_VERSION_PATCH DEC(__IBMCPP__ % 10) - -#elif defined(__IBMCPP__) && !defined(__COMPILER_VER__) && __IBMCPP__ < 800 -# define COMPILER_ID "VisualAge" - /* __IBMCPP__ = VRP */ -# define COMPILER_VERSION_MAJOR DEC(__IBMCPP__/100) -# define COMPILER_VERSION_MINOR DEC(__IBMCPP__/10 % 10) -# define COMPILER_VERSION_PATCH DEC(__IBMCPP__ % 10) - -#elif defined(__NVCOMPILER) -# define COMPILER_ID "NVHPC" -# define COMPILER_VERSION_MAJOR DEC(__NVCOMPILER_MAJOR__) -# define COMPILER_VERSION_MINOR DEC(__NVCOMPILER_MINOR__) -# if defined(__NVCOMPILER_PATCHLEVEL__) -# define COMPILER_VERSION_PATCH DEC(__NVCOMPILER_PATCHLEVEL__) -# endif - -#elif defined(__PGI) -# define COMPILER_ID "PGI" -# define COMPILER_VERSION_MAJOR DEC(__PGIC__) -# define COMPILER_VERSION_MINOR DEC(__PGIC_MINOR__) -# if defined(__PGIC_PATCHLEVEL__) -# define COMPILER_VERSION_PATCH DEC(__PGIC_PATCHLEVEL__) -# endif - -#elif defined(__clang__) && defined(__cray__) -# define COMPILER_ID "CrayClang" -# define COMPILER_VERSION_MAJOR DEC(__cray_major__) -# define COMPILER_VERSION_MINOR DEC(__cray_minor__) -# define COMPILER_VERSION_PATCH DEC(__cray_patchlevel__) -# define COMPILER_VERSION_INTERNAL_STR __clang_version__ - - -#elif defined(_CRAYC) -# define COMPILER_ID "Cray" -# define COMPILER_VERSION_MAJOR DEC(_RELEASE_MAJOR) -# define COMPILER_VERSION_MINOR DEC(_RELEASE_MINOR) - -#elif defined(__TI_COMPILER_VERSION__) -# define COMPILER_ID "TI" - /* __TI_COMPILER_VERSION__ = VVVRRRPPP */ -# define COMPILER_VERSION_MAJOR DEC(__TI_COMPILER_VERSION__/1000000) -# define COMPILER_VERSION_MINOR DEC(__TI_COMPILER_VERSION__/1000 % 1000) -# define COMPILER_VERSION_PATCH DEC(__TI_COMPILER_VERSION__ % 1000) - -#elif defined(__CLANG_FUJITSU) -# define COMPILER_ID "FujitsuClang" -# define COMPILER_VERSION_MAJOR DEC(__FCC_major__) -# define COMPILER_VERSION_MINOR DEC(__FCC_minor__) -# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__) -# define COMPILER_VERSION_INTERNAL_STR __clang_version__ - - -#elif defined(__FUJITSU) -# define COMPILER_ID "Fujitsu" -# if defined(__FCC_version__) -# define COMPILER_VERSION __FCC_version__ -# elif defined(__FCC_major__) -# define COMPILER_VERSION_MAJOR DEC(__FCC_major__) -# define COMPILER_VERSION_MINOR DEC(__FCC_minor__) -# define COMPILER_VERSION_PATCH DEC(__FCC_patchlevel__) -# endif -# if defined(__fcc_version) -# define COMPILER_VERSION_INTERNAL DEC(__fcc_version) -# elif defined(__FCC_VERSION) -# define COMPILER_VERSION_INTERNAL DEC(__FCC_VERSION) -# endif - - -#elif defined(__ghs__) -# define COMPILER_ID "GHS" -/* __GHS_VERSION_NUMBER = VVVVRP */ -# ifdef __GHS_VERSION_NUMBER -# define COMPILER_VERSION_MAJOR DEC(__GHS_VERSION_NUMBER / 100) -# define COMPILER_VERSION_MINOR DEC(__GHS_VERSION_NUMBER / 10 % 10) -# define COMPILER_VERSION_PATCH DEC(__GHS_VERSION_NUMBER % 10) -# endif - -#elif defined(__TASKING__) -# define COMPILER_ID "Tasking" - # define COMPILER_VERSION_MAJOR DEC(__VERSION__/1000) - # define COMPILER_VERSION_MINOR DEC(__VERSION__ % 100) -# define COMPILER_VERSION_INTERNAL DEC(__VERSION__) - -#elif defined(__ORANGEC__) -# define COMPILER_ID "OrangeC" -# define COMPILER_VERSION_MAJOR DEC(__ORANGEC_MAJOR__) -# define COMPILER_VERSION_MINOR DEC(__ORANGEC_MINOR__) -# define COMPILER_VERSION_PATCH DEC(__ORANGEC_PATCHLEVEL__) - -#elif defined(__SCO_VERSION__) -# define COMPILER_ID "SCO" - -#elif defined(__ARMCC_VERSION) && !defined(__clang__) -# define COMPILER_ID "ARMCC" -#if __ARMCC_VERSION >= 1000000 - /* __ARMCC_VERSION = VRRPPPP */ - # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/1000000) - # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 100) - # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000) -#else - /* __ARMCC_VERSION = VRPPPP */ - # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/100000) - # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 10) - # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000) -#endif - - -#elif defined(__clang__) && defined(__apple_build_version__) -# define COMPILER_ID "AppleClang" -# if defined(_MSC_VER) -# define SIMULATE_ID "MSVC" -# endif -# define COMPILER_VERSION_MAJOR DEC(__clang_major__) -# define COMPILER_VERSION_MINOR DEC(__clang_minor__) -# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__) -# if defined(_MSC_VER) - /* _MSC_VER = VVRR */ -# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) -# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) -# endif -# define COMPILER_VERSION_TWEAK DEC(__apple_build_version__) - -#elif defined(__clang__) && defined(__ARMCOMPILER_VERSION) -# define COMPILER_ID "ARMClang" - # define COMPILER_VERSION_MAJOR DEC(__ARMCOMPILER_VERSION/1000000) - # define COMPILER_VERSION_MINOR DEC(__ARMCOMPILER_VERSION/10000 % 100) - # define COMPILER_VERSION_PATCH DEC(__ARMCOMPILER_VERSION/100 % 100) -# define COMPILER_VERSION_INTERNAL DEC(__ARMCOMPILER_VERSION) - -#elif defined(__clang__) && defined(__ti__) -# define COMPILER_ID "TIClang" - # define COMPILER_VERSION_MAJOR DEC(__ti_major__) - # define COMPILER_VERSION_MINOR DEC(__ti_minor__) - # define COMPILER_VERSION_PATCH DEC(__ti_patchlevel__) -# define COMPILER_VERSION_INTERNAL DEC(__ti_version__) - -#elif defined(__clang__) -# define COMPILER_ID "Clang" -# if defined(_MSC_VER) -# define SIMULATE_ID "MSVC" -# endif -# define COMPILER_VERSION_MAJOR DEC(__clang_major__) -# define COMPILER_VERSION_MINOR DEC(__clang_minor__) -# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__) -# if defined(_MSC_VER) - /* _MSC_VER = VVRR */ -# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100) -# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100) -# endif - -#elif defined(__LCC__) && (defined(__GNUC__) || defined(__GNUG__) || defined(__MCST__)) -# define COMPILER_ID "LCC" -# define COMPILER_VERSION_MAJOR DEC(__LCC__ / 100) -# define COMPILER_VERSION_MINOR DEC(__LCC__ % 100) -# if defined(__LCC_MINOR__) -# define COMPILER_VERSION_PATCH DEC(__LCC_MINOR__) -# endif -# if defined(__GNUC__) && defined(__GNUC_MINOR__) -# define SIMULATE_ID "GNU" -# define SIMULATE_VERSION_MAJOR DEC(__GNUC__) -# define SIMULATE_VERSION_MINOR DEC(__GNUC_MINOR__) -# if defined(__GNUC_PATCHLEVEL__) -# define SIMULATE_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) -# endif -# endif - -#elif defined(__GNUC__) || defined(__GNUG__) -# define COMPILER_ID "GNU" -# if defined(__GNUC__) -# define COMPILER_VERSION_MAJOR DEC(__GNUC__) -# else -# define COMPILER_VERSION_MAJOR DEC(__GNUG__) -# endif -# if defined(__GNUC_MINOR__) -# define COMPILER_VERSION_MINOR DEC(__GNUC_MINOR__) -# endif -# if defined(__GNUC_PATCHLEVEL__) -# define COMPILER_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__) -# endif - -#elif defined(_MSC_VER) -# define COMPILER_ID "MSVC" - /* _MSC_VER = VVRR */ -# define COMPILER_VERSION_MAJOR DEC(_MSC_VER / 100) -# define COMPILER_VERSION_MINOR DEC(_MSC_VER % 100) -# if defined(_MSC_FULL_VER) -# if _MSC_VER >= 1400 - /* _MSC_FULL_VER = VVRRPPPPP */ -# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 100000) -# else - /* _MSC_FULL_VER = VVRRPPPP */ -# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 10000) -# endif -# endif -# if defined(_MSC_BUILD) -# define COMPILER_VERSION_TWEAK DEC(_MSC_BUILD) -# endif - -#elif defined(_ADI_COMPILER) -# define COMPILER_ID "ADSP" -#if defined(__VERSIONNUM__) - /* __VERSIONNUM__ = 0xVVRRPPTT */ -# define COMPILER_VERSION_MAJOR DEC(__VERSIONNUM__ >> 24 & 0xFF) -# define COMPILER_VERSION_MINOR DEC(__VERSIONNUM__ >> 16 & 0xFF) -# define COMPILER_VERSION_PATCH DEC(__VERSIONNUM__ >> 8 & 0xFF) -# define COMPILER_VERSION_TWEAK DEC(__VERSIONNUM__ & 0xFF) -#endif - -#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) -# define COMPILER_ID "IAR" -# if defined(__VER__) && defined(__ICCARM__) -# define COMPILER_VERSION_MAJOR DEC((__VER__) / 1000000) -# define COMPILER_VERSION_MINOR DEC(((__VER__) / 1000) % 1000) -# define COMPILER_VERSION_PATCH DEC((__VER__) % 1000) -# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) -# elif defined(__VER__) && (defined(__ICCAVR__) || defined(__ICCRX__) || defined(__ICCRH850__) || defined(__ICCRL78__) || defined(__ICC430__) || defined(__ICCRISCV__) || defined(__ICCV850__) || defined(__ICC8051__) || defined(__ICCSTM8__)) -# define COMPILER_VERSION_MAJOR DEC((__VER__) / 100) -# define COMPILER_VERSION_MINOR DEC((__VER__) - (((__VER__) / 100)*100)) -# define COMPILER_VERSION_PATCH DEC(__SUBVERSION__) -# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__) -# endif - - -/* These compilers are either not known or too old to define an - identification macro. Try to identify the platform and guess that - it is the native compiler. */ -#elif defined(__hpux) || defined(__hpua) -# define COMPILER_ID "HP" - -#else /* unknown compiler */ -# define COMPILER_ID "" -#endif - -/* Construct the string literal in pieces to prevent the source from - getting matched. Store it in a pointer rather than an array - because some compilers will just produce instructions to fill the - array rather than assigning a pointer to a static array. */ -char const* info_compiler = "INFO" ":" "compiler[" COMPILER_ID "]"; -#ifdef SIMULATE_ID -char const* info_simulate = "INFO" ":" "simulate[" SIMULATE_ID "]"; -#endif - -#ifdef __QNXNTO__ -char const* qnxnto = "INFO" ":" "qnxnto[]"; -#endif - -#if defined(__CRAYXT_COMPUTE_LINUX_TARGET) -char const *info_cray = "INFO" ":" "compiler_wrapper[CrayPrgEnv]"; -#endif - -#define STRINGIFY_HELPER(X) #X -#define STRINGIFY(X) STRINGIFY_HELPER(X) - -/* Identify known platforms by name. */ -#if defined(__linux) || defined(__linux__) || defined(linux) -# define PLATFORM_ID "Linux" - -#elif defined(__MSYS__) -# define PLATFORM_ID "MSYS" - -#elif defined(__CYGWIN__) -# define PLATFORM_ID "Cygwin" - -#elif defined(__MINGW32__) -# define PLATFORM_ID "MinGW" - -#elif defined(__APPLE__) -# define PLATFORM_ID "Darwin" - -#elif defined(_WIN32) || defined(__WIN32__) || defined(WIN32) -# define PLATFORM_ID "Windows" - -#elif defined(__FreeBSD__) || defined(__FreeBSD) -# define PLATFORM_ID "FreeBSD" - -#elif defined(__NetBSD__) || defined(__NetBSD) -# define PLATFORM_ID "NetBSD" - -#elif defined(__OpenBSD__) || defined(__OPENBSD) -# define PLATFORM_ID "OpenBSD" - -#elif defined(__sun) || defined(sun) -# define PLATFORM_ID "SunOS" - -#elif defined(_AIX) || defined(__AIX) || defined(__AIX__) || defined(__aix) || defined(__aix__) -# define PLATFORM_ID "AIX" - -#elif defined(__hpux) || defined(__hpux__) -# define PLATFORM_ID "HP-UX" - -#elif defined(__HAIKU__) -# define PLATFORM_ID "Haiku" - -#elif defined(__BeOS) || defined(__BEOS__) || defined(_BEOS) -# define PLATFORM_ID "BeOS" - -#elif defined(__QNX__) || defined(__QNXNTO__) -# define PLATFORM_ID "QNX" - -#elif defined(__tru64) || defined(_tru64) || defined(__TRU64__) -# define PLATFORM_ID "Tru64" - -#elif defined(__riscos) || defined(__riscos__) -# define PLATFORM_ID "RISCos" - -#elif defined(__sinix) || defined(__sinix__) || defined(__SINIX__) -# define PLATFORM_ID "SINIX" - -#elif defined(__UNIX_SV__) -# define PLATFORM_ID "UNIX_SV" - -#elif defined(__bsdos__) -# define PLATFORM_ID "BSDOS" - -#elif defined(_MPRAS) || defined(MPRAS) -# define PLATFORM_ID "MP-RAS" - -#elif defined(__osf) || defined(__osf__) -# define PLATFORM_ID "OSF1" - -#elif defined(_SCO_SV) || defined(SCO_SV) || defined(sco_sv) -# define PLATFORM_ID "SCO_SV" - -#elif defined(__ultrix) || defined(__ultrix__) || defined(_ULTRIX) -# define PLATFORM_ID "ULTRIX" - -#elif defined(__XENIX__) || defined(_XENIX) || defined(XENIX) -# define PLATFORM_ID "Xenix" - -#elif defined(__WATCOMC__) -# if defined(__LINUX__) -# define PLATFORM_ID "Linux" - -# elif defined(__DOS__) -# define PLATFORM_ID "DOS" - -# elif defined(__OS2__) -# define PLATFORM_ID "OS2" - -# elif defined(__WINDOWS__) -# define PLATFORM_ID "Windows3x" - -# elif defined(__VXWORKS__) -# define PLATFORM_ID "VxWorks" - -# else /* unknown platform */ -# define PLATFORM_ID -# endif - -#elif defined(__INTEGRITY) -# if defined(INT_178B) -# define PLATFORM_ID "Integrity178" - -# else /* regular Integrity */ -# define PLATFORM_ID "Integrity" -# endif - -# elif defined(_ADI_COMPILER) -# define PLATFORM_ID "ADSP" - -#else /* unknown platform */ -# define PLATFORM_ID - -#endif - -/* For windows compilers MSVC and Intel we can determine - the architecture of the compiler being used. This is because - the compilers do not have flags that can change the architecture, - but rather depend on which compiler is being used -*/ -#if defined(_WIN32) && defined(_MSC_VER) -# if defined(_M_IA64) -# define ARCHITECTURE_ID "IA64" - -# elif defined(_M_ARM64EC) -# define ARCHITECTURE_ID "ARM64EC" - -# elif defined(_M_X64) || defined(_M_AMD64) -# define ARCHITECTURE_ID "x64" - -# elif defined(_M_IX86) -# define ARCHITECTURE_ID "X86" - -# elif defined(_M_ARM64) -# define ARCHITECTURE_ID "ARM64" - -# elif defined(_M_ARM) -# if _M_ARM == 4 -# define ARCHITECTURE_ID "ARMV4I" -# elif _M_ARM == 5 -# define ARCHITECTURE_ID "ARMV5I" -# else -# define ARCHITECTURE_ID "ARMV" STRINGIFY(_M_ARM) -# endif - -# elif defined(_M_MIPS) -# define ARCHITECTURE_ID "MIPS" - -# elif defined(_M_SH) -# define ARCHITECTURE_ID "SHx" - -# else /* unknown architecture */ -# define ARCHITECTURE_ID "" -# endif - -#elif defined(__WATCOMC__) -# if defined(_M_I86) -# define ARCHITECTURE_ID "I86" - -# elif defined(_M_IX86) -# define ARCHITECTURE_ID "X86" - -# else /* unknown architecture */ -# define ARCHITECTURE_ID "" -# endif - -#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC) -# if defined(__ICCARM__) -# define ARCHITECTURE_ID "ARM" - -# elif defined(__ICCRX__) -# define ARCHITECTURE_ID "RX" - -# elif defined(__ICCRH850__) -# define ARCHITECTURE_ID "RH850" - -# elif defined(__ICCRL78__) -# define ARCHITECTURE_ID "RL78" - -# elif defined(__ICCRISCV__) -# define ARCHITECTURE_ID "RISCV" - -# elif defined(__ICCAVR__) -# define ARCHITECTURE_ID "AVR" - -# elif defined(__ICC430__) -# define ARCHITECTURE_ID "MSP430" - -# elif defined(__ICCV850__) -# define ARCHITECTURE_ID "V850" - -# elif defined(__ICC8051__) -# define ARCHITECTURE_ID "8051" - -# elif defined(__ICCSTM8__) -# define ARCHITECTURE_ID "STM8" - -# else /* unknown architecture */ -# define ARCHITECTURE_ID "" -# endif - -#elif defined(__ghs__) -# if defined(__PPC64__) -# define ARCHITECTURE_ID "PPC64" - -# elif defined(__ppc__) -# define ARCHITECTURE_ID "PPC" - -# elif defined(__ARM__) -# define ARCHITECTURE_ID "ARM" - -# elif defined(__x86_64__) -# define ARCHITECTURE_ID "x64" - -# elif defined(__i386__) -# define ARCHITECTURE_ID "X86" - -# else /* unknown architecture */ -# define ARCHITECTURE_ID "" -# endif - -#elif defined(__clang__) && defined(__ti__) -# if defined(__ARM_ARCH) -# define ARCHITECTURE_ID "Arm" - -# else /* unknown architecture */ -# define ARCHITECTURE_ID "" -# endif - -#elif defined(__TI_COMPILER_VERSION__) -# if defined(__TI_ARM__) -# define ARCHITECTURE_ID "ARM" - -# elif defined(__MSP430__) -# define ARCHITECTURE_ID "MSP430" - -# elif defined(__TMS320C28XX__) -# define ARCHITECTURE_ID "TMS320C28x" - -# elif defined(__TMS320C6X__) || defined(_TMS320C6X) -# define ARCHITECTURE_ID "TMS320C6x" - -# else /* unknown architecture */ -# define ARCHITECTURE_ID "" -# endif - -# elif defined(__ADSPSHARC__) -# define ARCHITECTURE_ID "SHARC" - -# elif defined(__ADSPBLACKFIN__) -# define ARCHITECTURE_ID "Blackfin" - -#elif defined(__TASKING__) - -# if defined(__CTC__) || defined(__CPTC__) -# define ARCHITECTURE_ID "TriCore" - -# elif defined(__CMCS__) -# define ARCHITECTURE_ID "MCS" - -# elif defined(__CARM__) -# define ARCHITECTURE_ID "ARM" - -# elif defined(__CARC__) -# define ARCHITECTURE_ID "ARC" - -# elif defined(__C51__) -# define ARCHITECTURE_ID "8051" - -# elif defined(__CPCP__) -# define ARCHITECTURE_ID "PCP" - -# else -# define ARCHITECTURE_ID "" -# endif - -#else -# define ARCHITECTURE_ID -#endif - -/* Convert integer to decimal digit literals. */ -#define DEC(n) \ - ('0' + (((n) / 10000000)%10)), \ - ('0' + (((n) / 1000000)%10)), \ - ('0' + (((n) / 100000)%10)), \ - ('0' + (((n) / 10000)%10)), \ - ('0' + (((n) / 1000)%10)), \ - ('0' + (((n) / 100)%10)), \ - ('0' + (((n) / 10)%10)), \ - ('0' + ((n) % 10)) - -/* Convert integer to hex digit literals. */ -#define HEX(n) \ - ('0' + ((n)>>28 & 0xF)), \ - ('0' + ((n)>>24 & 0xF)), \ - ('0' + ((n)>>20 & 0xF)), \ - ('0' + ((n)>>16 & 0xF)), \ - ('0' + ((n)>>12 & 0xF)), \ - ('0' + ((n)>>8 & 0xF)), \ - ('0' + ((n)>>4 & 0xF)), \ - ('0' + ((n) & 0xF)) - -/* Construct a string literal encoding the version number. */ -#ifdef COMPILER_VERSION -char const* info_version = "INFO" ":" "compiler_version[" COMPILER_VERSION "]"; - -/* Construct a string literal encoding the version number components. */ -#elif defined(COMPILER_VERSION_MAJOR) -char const info_version[] = { - 'I', 'N', 'F', 'O', ':', - 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','[', - COMPILER_VERSION_MAJOR, -# ifdef COMPILER_VERSION_MINOR - '.', COMPILER_VERSION_MINOR, -# ifdef COMPILER_VERSION_PATCH - '.', COMPILER_VERSION_PATCH, -# ifdef COMPILER_VERSION_TWEAK - '.', COMPILER_VERSION_TWEAK, -# endif -# endif -# endif - ']','\0'}; -#endif - -/* Construct a string literal encoding the internal version number. */ -#ifdef COMPILER_VERSION_INTERNAL -char const info_version_internal[] = { - 'I', 'N', 'F', 'O', ':', - 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','_', - 'i','n','t','e','r','n','a','l','[', - COMPILER_VERSION_INTERNAL,']','\0'}; -#elif defined(COMPILER_VERSION_INTERNAL_STR) -char const* info_version_internal = "INFO" ":" "compiler_version_internal[" COMPILER_VERSION_INTERNAL_STR "]"; -#endif - -/* Construct a string literal encoding the version number components. */ -#ifdef SIMULATE_VERSION_MAJOR -char const info_simulate_version[] = { - 'I', 'N', 'F', 'O', ':', - 's','i','m','u','l','a','t','e','_','v','e','r','s','i','o','n','[', - SIMULATE_VERSION_MAJOR, -# ifdef SIMULATE_VERSION_MINOR - '.', SIMULATE_VERSION_MINOR, -# ifdef SIMULATE_VERSION_PATCH - '.', SIMULATE_VERSION_PATCH, -# ifdef SIMULATE_VERSION_TWEAK - '.', SIMULATE_VERSION_TWEAK, -# endif -# endif -# endif - ']','\0'}; -#endif - -/* Construct the string literal in pieces to prevent the source from - getting matched. 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By not providing "FindSparta.cmake" in CMAKE_MODULE_PATH this project has - asked CMake to find a package configuration file provided by "Sparta", but - CMake did not find one. - - Could not find a package configuration file provided by "Sparta" with any - of the following names: - - SpartaConfig.cmake - sparta-config.cmake - - Add the installation prefix of "Sparta" to CMAKE_PREFIX_PATH or set - "Sparta_DIR" to a directory containing one of the above files. If "Sparta" - provides a separate development package or SDK, be sure it has been - installed. - - --- Configuring incomplete, errors occurred! diff --git a/cmake-build-debug/CMakeFiles/clion-environment.txt b/cmake-build-debug/CMakeFiles/clion-environment.txt deleted file mode 100644 index cd47557a2a4555afbb8639481d27d02a83eff8bc..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 112 zcmWH^&(8@?EwNHC)H6`f$jMJm%+d5OD9OyvE4EVL;({@CU7UR#y Date: Tue, 15 Oct 2024 20:47:29 +0530 Subject: [PATCH 10/14] Fusing instructions only when enough instructions are sent from fetch --- arches/fusion.yaml | 2 +- core/Decode.cpp | 5 ++++- core/FusionDecode.cpp | 2 ++ 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arches/fusion.yaml b/arches/fusion.yaml index d944d6e9..654de05a 100644 --- a/arches/fusion.yaml +++ b/arches/fusion.yaml @@ -3,7 +3,7 @@ top.cpu.core0: decode: params: num_to_decode: 8 - fusion_enable: false + fusion_enable: true fusion_debug: false fusion_enable_register: 0xFFFFFFFF fusion_max_latency: 8 diff --git a/core/Decode.cpp b/core/Decode.cpp index 9a92fbcd..a7dc6b27 100644 --- a/core/Decode.cpp +++ b/core/Decode.cpp @@ -276,7 +276,10 @@ namespace olympia } } - if (fusion_enable_) + // fuse instructions only when uids.size() is large enough + // to not cause problems with matchFusionGroups_() + // hardcoded lower bound as 4 for now + if (fusion_enable_ && uids.size() > 4) { MatchInfoListType matches; uint32_t max_itrs = 0; diff --git a/core/FusionDecode.cpp b/core/FusionDecode.cpp index ef1f3f3c..f83c56a7 100644 --- a/core/FusionDecode.cpp +++ b/core/FusionDecode.cpp @@ -126,6 +126,8 @@ namespace olympia { auto & fGrp = fgPair.second; size_t grpSize = fGrp.uids().size(); + + sparta_assert(inputUids.size() > grpSize); hcache_.buildHashCacheEntry(inputUids, grpSize); } From 1a56ca934ef8f87c68a0884667f1948ccdfe1152 Mon Sep 17 00:00:00 2001 From: Shobhit Date: Sat, 19 Oct 2024 00:31:07 +0530 Subject: [PATCH 11/14] Replaced condition using hardcoded value with condition using attributes for filtering instructions for fusion --- core/Decode.cpp | 5 +---- core/FusionDecode.cpp | 7 ++++++- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/core/Decode.cpp b/core/Decode.cpp index a7dc6b27..9a92fbcd 100644 --- a/core/Decode.cpp +++ b/core/Decode.cpp @@ -276,10 +276,7 @@ namespace olympia } } - // fuse instructions only when uids.size() is large enough - // to not cause problems with matchFusionGroups_() - // hardcoded lower bound as 4 for now - if (fusion_enable_ && uids.size() > 4) + if (fusion_enable_) { MatchInfoListType matches; uint32_t max_itrs = 0; diff --git a/core/FusionDecode.cpp b/core/FusionDecode.cpp index f83c56a7..3b0296c8 100644 --- a/core/FusionDecode.cpp +++ b/core/FusionDecode.cpp @@ -127,7 +127,12 @@ namespace olympia auto & fGrp = fgPair.second; size_t grpSize = fGrp.uids().size(); - sparta_assert(inputUids.size() > grpSize); + // grpSize should be less than the input for matching fusion pairs + if(grpSize > inputUids.size()) + { + continue; + } + hcache_.buildHashCacheEntry(inputUids, grpSize); } From 515e160913d0c1a4115cc0aa8b0905e82ee3198b Mon Sep 17 00:00:00 2001 From: Shobhit Date: Sat, 19 Oct 2024 17:08:58 +0530 Subject: [PATCH 12/14] updated EXPECTED files and ../core/Inst.hpp for whitespace between pid and status --- core/Inst.hpp | 2 +- .../expected_output/arbitrate.out.EXPECTED | 86 +++---- .../expected_output/big_core.out.EXPECTED | 202 ++++++++-------- .../expected_output/medium_core.out.EXPECTED | 210 ++++++++--------- .../expected_output/small_core.out.EXPECTED | 220 +++++++++--------- .../expected_output/hit_case.out.EXPECTED | 70 +++--- .../single_access.out.EXPECTED | 46 ++-- .../expected_output/big_core.out.EXPECTED | 40 ++-- .../big_core_small_rename.out.EXPECTED | 38 +-- .../expected_output/medium_core.out.EXPECTED | 40 ++-- .../expected_output/small_core.out.EXPECTED | 40 ++-- 11 files changed, 497 insertions(+), 497 deletions(-) diff --git a/core/Inst.hpp b/core/Inst.hpp index 12157976..78f8afb1 100644 --- a/core/Inst.hpp +++ b/core/Inst.hpp @@ -531,7 +531,7 @@ namespace olympia // - any changes here will break EXPECT inline std::ostream & operator<<(std::ostream & os, const Inst & inst) { - os << "uid:" << inst.getUniqueID() << std::setw(10) << inst.getStatus() << " " + os << "uid:" << inst.getUniqueID() << " " << std::setw(10) << inst.getStatus() << " " << std::hex << inst.getPC() << std::dec << " pid:" << inst.getProgramID() << " uopid:" << inst.getUOpID() << " '" << inst.getDisasm() << "' "; return os; diff --git a/test/core/dcache/expected_output/arbitrate.out.EXPECTED b/test/core/dcache/expected_output/arbitrate.out.EXPECTED index 56419b63..fb2b71ae 100644 --- a/test/core/dcache/expected_output/arbitrate.out.EXPECTED +++ b/test/core/dcache/expected_output/arbitrate.out.EXPECTED @@ -3,70 +3,70 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Oct 8 16:49:19 2024 -#Elapsed: 0.00278s -{0000000000 00000000 top.lsu info} req_inst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' ' Requested -{0000000000 00000000 top.dcache info} receiveMemReqFromLSU_: Received memory access request from LSU memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' -{0000000000 00000000 top.dcache info} arbitrateL2LsuReq_: Received LSU request memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' +#Start: Saturday Sat Oct 19 15:35:23 2024 +#Elapsed: 0.002073s +{0000000000 00000000 top.lsu info} req_inst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' ' Requested +{0000000000 00000000 top.dcache info} receiveMemReqFromLSU_: Received memory access request from LSU memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' +{0000000000 00000000 top.dcache info} arbitrateL2LsuReq_: Received LSU request memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' {0000000001 00000001 top.dcache info} handleLookup_: Lookup stage -{0000000001 00000001 top.dcache info} handleLookup_: memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' in Lookup stage +{0000000001 00000001 top.dcache info} handleLookup_: memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' in Lookup stage {0000000001 00000001 top.dcache info} dataLookup_: DL1 DCache MISS: phyAddr=0xdeadbeef -{0000000001 00000001 top.dcache info} handleLookup_: memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' performing lookup 0 -{0000000001 00000001 top.dcache info} handleLookup_: Creating new MSHR Entry memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' +{0000000001 00000001 top.dcache info} handleLookup_: memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' performing lookup 0 +{0000000001 00000001 top.dcache info} handleLookup_: Creating new MSHR Entry memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' {0000000001 00000001 top.dcache info} handleLookup_: Load miss inst to LMQ; block address:0xdeadbee0 -{0000000001 00000001 top.lsu info} ReceiveAck_: Ack: 'memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' ' Received +{0000000001 00000001 top.lsu info} ReceiveAck_: Ack: 'memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' ' Received {0000000001 00000001 top.dcache info} mshrRequest_: Send mshr req -{0000000001 00000001 top.dcache info} mshrRequest_: Sending mshr request when not busy memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' -{0000000002 00000002 top.next_lvl info} sinkInst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' ' sinked +{0000000001 00000001 top.dcache info} mshrRequest_: Sending mshr request when not busy memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' +{0000000002 00000002 top.next_lvl info} sinkInst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' ' sinked {0000000002 00000002 top.dcache info} handleDataRead_: Data Read stage -{0000000002 00000002 top.dcache info} handleDataRead_: memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' in read stage -{0000000002 00000002 top.lsu info} ReceiveAck_: Ack: 'memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' ' Received +{0000000002 00000002 top.dcache info} handleDataRead_: memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' in read stage +{0000000002 00000002 top.lsu info} ReceiveAck_: Ack: 'memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' ' Received {0000000003 00000003 top.dcache info} handleDeallocate_: Data Dellocate stage -{0000000003 00000003 top.dcache info} handleDeallocate_: memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' in deallocate stage -{0000000003 00000003 top.dcache info} handleDeallocate_: Deallocating pipeline for memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' +{0000000003 00000003 top.dcache info} handleDeallocate_: memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' in deallocate stage +{0000000003 00000003 top.dcache info} handleDeallocate_: Deallocating pipeline for memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' {0000000003 00000003 top.dcache info} mshrRequest_: Send mshr req -{0000000007 00000007 top.dcache info} receiveRespFromL2Cache_: Received cache refill memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' -{0000000007 00000007 top.dcache info} receiveRespFromL2Cache_: Removing mshr entry for memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' -{0000000007 00000007 top.dcache info} arbitrateL2LsuReq_: Received Refill request memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' +{0000000007 00000007 top.dcache info} receiveRespFromL2Cache_: Received cache refill memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' +{0000000007 00000007 top.dcache info} receiveRespFromL2Cache_: Removing mshr entry for memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' +{0000000007 00000007 top.dcache info} arbitrateL2LsuReq_: Received Refill request memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' {0000000008 00000008 top.dcache info} handleLookup_: Lookup stage -{0000000008 00000008 top.dcache info} handleLookup_: memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' in Lookup stage -{0000000008 00000008 top.dcache info} handleLookup_: Incoming cache refill memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' -{0000000008 00000008 top.lsu info} req_inst_: Instruction: 'uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' ' Requested -{0000000008 00000008 top.dcache info} receiveMemReqFromLSU_: Received memory access request from LSU memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' +{0000000008 00000008 top.dcache info} handleLookup_: memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' in Lookup stage +{0000000008 00000008 top.dcache info} handleLookup_: Incoming cache refill memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' +{0000000008 00000008 top.lsu info} req_inst_: Instruction: 'uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' ' Requested +{0000000008 00000008 top.dcache info} receiveMemReqFromLSU_: Received memory access request from LSU memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' {0000000008 00000008 top.dcache info} mshrRequest_: Send mshr req -{0000000008 00000008 top.dcache info} arbitrateL2LsuReq_: Received LSU request memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' +{0000000008 00000008 top.dcache info} arbitrateL2LsuReq_: Received LSU request memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' {0000000009 00000009 top.dcache info} handleLookup_: Lookup stage -{0000000009 00000009 top.dcache info} handleLookup_: memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' in Lookup stage +{0000000009 00000009 top.dcache info} handleLookup_: memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' in Lookup stage {0000000009 00000009 top.dcache info} dataLookup_: DL1 DCache MISS: phyAddr=0xdeedbeef -{0000000009 00000009 top.dcache info} handleLookup_: memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' performing lookup 0 -{0000000009 00000009 top.dcache info} handleLookup_: Creating new MSHR Entry memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' +{0000000009 00000009 top.dcache info} handleLookup_: memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' performing lookup 0 +{0000000009 00000009 top.dcache info} handleLookup_: Creating new MSHR Entry memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' {0000000009 00000009 top.dcache info} handleLookup_: Load miss inst to LMQ; block address:0xdeedbee0 -{0000000009 00000009 top.lsu info} ReceiveAck_: Ack: 'memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' ' Received +{0000000009 00000009 top.lsu info} ReceiveAck_: Ack: 'memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' ' Received {0000000009 00000009 top.dcache info} handleDataRead_: Data Read stage -{0000000009 00000009 top.dcache info} handleDataRead_: memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' in read stage +{0000000009 00000009 top.dcache info} handleDataRead_: memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' in read stage {0000000009 00000009 top.dcache info} reloadCache_: DCache reload complete! {0000000009 00000009 top.dcache info} mshrRequest_: Send mshr req -{0000000009 00000009 top.dcache info} mshrRequest_: Sending mshr request when not busy memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' -{0000000010 00000010 top.next_lvl info} sinkInst_: Instruction: 'uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' ' sinked +{0000000009 00000009 top.dcache info} mshrRequest_: Sending mshr request when not busy memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' +{0000000010 00000010 top.next_lvl info} sinkInst_: Instruction: 'uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' ' sinked {0000000010 00000010 top.dcache info} handleDataRead_: Data Read stage -{0000000010 00000010 top.dcache info} handleDataRead_: memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' in read stage -{0000000010 00000010 top.lsu info} ReceiveAck_: Ack: 'memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' ' Received +{0000000010 00000010 top.dcache info} handleDataRead_: memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' in read stage +{0000000010 00000010 top.lsu info} ReceiveAck_: Ack: 'memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' ' Received {0000000010 00000010 top.dcache info} handleDeallocate_: Data Dellocate stage -{0000000010 00000010 top.dcache info} handleDeallocate_: memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' in deallocate stage -{0000000010 00000010 top.lsu info} ReceiveAck_: Ack: 'memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' ' Received -{0000000010 00000010 top.dcache info} handleDeallocate_: Removing mshr entry for memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' +{0000000010 00000010 top.dcache info} handleDeallocate_: memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' in deallocate stage +{0000000010 00000010 top.lsu info} ReceiveAck_: Ack: 'memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' ' Received +{0000000010 00000010 top.dcache info} handleDeallocate_: Removing mshr entry for memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' {0000000011 00000011 top.dcache info} handleDeallocate_: Data Dellocate stage -{0000000011 00000011 top.dcache info} handleDeallocate_: memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' in deallocate stage -{0000000011 00000011 top.dcache info} handleDeallocate_: Deallocating pipeline for memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' +{0000000011 00000011 top.dcache info} handleDeallocate_: memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' in deallocate stage +{0000000011 00000011 top.dcache info} handleDeallocate_: Deallocating pipeline for memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' {0000000011 00000011 top.dcache info} mshrRequest_: Send mshr req -{0000000015 00000015 top.dcache info} receiveRespFromL2Cache_: Received cache refill memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' -{0000000015 00000015 top.dcache info} arbitrateL2LsuReq_: Received Refill request memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' +{0000000015 00000015 top.dcache info} receiveRespFromL2Cache_: Received cache refill memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' +{0000000015 00000015 top.dcache info} arbitrateL2LsuReq_: Received Refill request memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' {0000000016 00000016 top.dcache info} handleLookup_: Lookup stage -{0000000016 00000016 top.dcache info} handleLookup_: memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' in Lookup stage -{0000000016 00000016 top.dcache info} handleLookup_: Incoming cache refill memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' +{0000000016 00000016 top.dcache info} handleLookup_: memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' in Lookup stage +{0000000016 00000016 top.dcache info} handleLookup_: Incoming cache refill memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' {0000000016 00000016 top.dcache info} mshrRequest_: Send mshr req {0000000017 00000017 top.dcache info} handleDataRead_: Data Read stage -{0000000017 00000017 top.dcache info} handleDataRead_: memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' in read stage +{0000000017 00000017 top.dcache info} handleDataRead_: memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' in read stage {0000000017 00000017 top.dcache info} reloadCache_: DCache reload complete! {0000000018 00000018 top.dcache info} handleDeallocate_: Data Dellocate stage -{0000000018 00000018 top.dcache info} handleDeallocate_: memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' in deallocate stage +{0000000018 00000018 top.dcache info} handleDeallocate_: memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' in deallocate stage diff --git a/test/core/dispatch/expected_output/big_core.out.EXPECTED b/test/core/dispatch/expected_output/big_core.out.EXPECTED index b54f664a..b6b0ad67 100644 --- a/test/core/dispatch/expected_output/big_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/big_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Oct 8 16:46:24 2024 -#Elapsed: 0.00175s +#Start: Saturday Sat Oct 19 16:01:55 2024 +#Elapsed: 0.001359s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: DIViq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq1 @@ -51,18 +51,18 @@ {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add, 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add, 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0,3] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [5,32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [7,33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard @@ -70,182 +70,182 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add, 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to iq0 of target type: INT -{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to iq1 of target type: INT -{0000000002 00000002 top.dispatch info} acceptInst: iq2: dispatching uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to iq2 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to iq1 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq2: dispatching uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to iq2 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [9,34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [11,35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [13,36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [15,37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 4 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add, 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' -{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' Bits needed:[0,3] rf: integer -{0000000003 00000003 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' Bits needed:[5,32] rf: integer +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' +{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' Bits needed:[0,3] rf: integer +{0000000003 00000003 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' Bits needed:[5,32] rf: integer {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' for 4 +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to iq0 of target type: INT -{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to iq1 of target type: INT -{0000000003 00000003 top.dispatch info} acceptInst: iq2: dispatching uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to iq2 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to iq1 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq2: dispatching uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to iq2 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [17,38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [19,39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:10 RENAMED 0 pid:0 uopid:0 'add 22,20,21' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:10 RENAMED 0 pid:0 uopid:0 'add 22,20,21' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [21,40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:11 RENAMED 0 pid:0 uopid:0 'add 24,22,23' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:11 RENAMED 0 pid:0 uopid:0 'add 24,22,23' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [23,41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [42] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 4 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add, 0x00000000 UID(20) PID(0) add, 0x00000000 UID(21) PID(0) add -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' Bits needed:[7,33] rf: integer -{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' Bits needed:[9,34] rf: integer -{0000000004 00000004 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' Bits needed:[11,35] rf: integer +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' Bits needed:[7,33] rf: integer +{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' Bits needed:[9,34] rf: integer +{0000000004 00000004 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' Bits needed:[11,35] rf: integer {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to iq0 of target type: INT -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to iq1 of target type: INT -{0000000004 00000004 top.dispatch info} acceptInst: iq2: dispatching uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to iq2 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to iq0 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to iq1 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq2: dispatching uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to iq2 of target type: INT {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:12 RENAMED 0 pid:0 uopid:0 'add 26,24,25' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:12 RENAMED 0 pid:0 uopid:0 'add 26,24,25' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [25,42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [43] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:13 RENAMED 0 pid:0 uopid:0 'add 28,26,27' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:13 RENAMED 0 pid:0 uopid:0 'add 28,26,27' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [27,43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [44] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:14 RENAMED 0 pid:0 uopid:0 'add 30,28,29' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:14 RENAMED 0 pid:0 uopid:0 'add 30,28,29' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [29,44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [45] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:15 RENAMED 0 pid:0 uopid:0 'add 0,30,31' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:15 RENAMED 0 pid:0 uopid:0 'add 0,30,31' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [45] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [31,45] for 'integer' scoreboard {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 4 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(22) PID(0) add, 0x00000000 UID(23) PID(0) add, 0x00000000 UID(24) PID(0) add, 0x00000000 UID(25) PID(0) add -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' Bits needed:[13,36] rf: integer -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' Bits needed:[15,37] rf: integer -{0000000005 00000005 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' Bits needed:[17,38] rf: integer +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' Bits needed:[13,36] rf: integer +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' Bits needed:[15,37] rf: integer +{0000000005 00000005 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' Bits needed:[17,38] rf: integer {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add, 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add -{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid:0 COMPLETED 0 pid:0 uopid:0 'add 2,0,1' -{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to exe_pipe exe2 -{0000000005 00000005 top.execute.exe2 info} insertInst: Executing: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' for 6 +{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid:0 COMPLETED 0 pid:0 uopid:0 'add 2,0,1' +{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to exe_pipe exe2 +{0000000005 00000005 top.execute.exe2 info} insertInst: Executing: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' for 6 {0000000005 00000005 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 6 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to iq0 of target type: INT +{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to iq0 of target type: INT {0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:16 RENAMED 0 pid:0 uopid:0 'add 2,0,1' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:16 RENAMED 0 pid:0 uopid:0 'add 2,0,1' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [46] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:17 RENAMED 0 pid:0 uopid:0 'add 4,2,3' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:17 RENAMED 0 pid:0 uopid:0 'add 4,2,3' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [3,46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [47] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:18 RENAMED 0 pid:0 uopid:0 'add 6,4,5' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:18 RENAMED 0 pid:0 uopid:0 'add 6,4,5' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [47] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [5,47] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [48] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:19 RENAMED 0 pid:0 uopid:0 'add 8,6,7' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:19 RENAMED 0 pid:0 uopid:0 'add 8,6,7' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [48] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [7,48] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [49] for 'integer' scoreboard {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 4 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(26) PID(0) add, 0x00000000 UID(27) PID(0) add, 0x00000000 UID(28) PID(0) add, 0x00000000 UID(29) PID(0) add -{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' Bits needed:[19,39] rf: integer +{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' Bits needed:[19,39] rf: integer {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add, 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add {0000000006 00000006 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000006 00000006 top.execute.exe2 info} executeInst_: Executed inst: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' -{0000000007 00000007 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' -{0000000007 00000007 top.execute.exe2 info} completeInst_: Completing inst: uid:1 COMPLETED 0 pid:0 uopid:0 'add 4,2,3' -{0000000007 00000007 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to exe_pipe exe4 -{0000000007 00000007 top.execute.exe4 info} insertInst: Executing: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' for 8 +{0000000006 00000006 top.execute.exe2 info} executeInst_: Executed inst: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' +{0000000007 00000007 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' +{0000000007 00000007 top.execute.exe2 info} completeInst_: Completing inst: uid:1 COMPLETED 0 pid:0 uopid:0 'add 4,2,3' +{0000000007 00000007 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to exe_pipe exe4 +{0000000007 00000007 top.execute.exe4 info} insertInst: Executing: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' for 8 {0000000007 00000007 top.dispatch info} receiveCredits_: iq2 got 1 credits, total: 6 {0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000008 00000008 top.execute.exe4 info} executeInst_: Executed inst: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' -{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' -{0000000009 00000009 top.execute.exe4 info} completeInst_: Completing inst: uid:2 COMPLETED 0 pid:0 uopid:0 'add 6,4,5' -{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to exe_pipe exe0 -{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' for 10 +{0000000008 00000008 top.execute.exe4 info} executeInst_: Executed inst: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' +{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' +{0000000009 00000009 top.execute.exe4 info} completeInst_: Completing inst: uid:2 COMPLETED 0 pid:0 uopid:0 'add 6,4,5' +{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to exe_pipe exe0 +{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' for 10 {0000000009 00000009 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000009 00000009 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' -{0000000011 00000011 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' -{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid:3 COMPLETED 0 pid:0 uopid:0 'add 8,6,7' -{0000000011 00000011 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to exe_pipe exe2 -{0000000011 00000011 top.execute.exe2 info} insertInst: Executing: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' for 12 +{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' +{0000000011 00000011 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' +{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid:3 COMPLETED 0 pid:0 uopid:0 'add 8,6,7' +{0000000011 00000011 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to exe_pipe exe2 +{0000000011 00000011 top.execute.exe2 info} insertInst: Executing: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' for 12 {0000000011 00000011 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 7 {0000000011 00000011 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000012 00000012 top.execute.exe2 info} executeInst_: Executed inst: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' -{0000000013 00000013 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' -{0000000013 00000013 top.execute.exe2 info} completeInst_: Completing inst: uid:4 COMPLETED 0 pid:0 uopid:0 'add 10,8,9' -{0000000013 00000013 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to exe_pipe exe4 -{0000000013 00000013 top.execute.exe4 info} insertInst: Executing: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' for 14 +{0000000012 00000012 top.execute.exe2 info} executeInst_: Executed inst: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' +{0000000013 00000013 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' +{0000000013 00000013 top.execute.exe2 info} completeInst_: Completing inst: uid:4 COMPLETED 0 pid:0 uopid:0 'add 10,8,9' +{0000000013 00000013 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to exe_pipe exe4 +{0000000013 00000013 top.execute.exe4 info} insertInst: Executing: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' for 14 {0000000013 00000013 top.dispatch info} receiveCredits_: iq2 got 1 credits, total: 7 {0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000014 00000014 top.execute.exe4 info} executeInst_: Executed inst: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' -{0000000015 00000015 top.execute.exe4 info} completeInst_: Completing inst: uid:5 COMPLETED 0 pid:0 uopid:0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to exe_pipe exe0 -{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' for 16 +{0000000014 00000014 top.execute.exe4 info} executeInst_: Executed inst: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' +{0000000015 00000015 top.execute.exe4 info} completeInst_: Completing inst: uid:5 COMPLETED 0 pid:0 uopid:0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to exe_pipe exe0 +{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' for 16 {0000000015 00000015 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' -{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid:6 COMPLETED 0 pid:0 uopid:0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to exe_pipe exe2 -{0000000017 00000017 top.execute.exe2 info} insertInst: Executing: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' for 18 +{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' +{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid:6 COMPLETED 0 pid:0 uopid:0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to exe_pipe exe2 +{0000000017 00000017 top.execute.exe2 info} insertInst: Executing: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' for 18 {0000000017 00000017 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 8 {0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000018 00000018 top.execute.exe2 info} executeInst_: Executed inst: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' -{0000000019 00000019 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' -{0000000019 00000019 top.execute.exe2 info} completeInst_: Completing inst: uid:7 COMPLETED 0 pid:0 uopid:0 'add 16,14,15' -{0000000019 00000019 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to exe_pipe exe4 -{0000000019 00000019 top.execute.exe4 info} insertInst: Executing: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' for 20 +{0000000018 00000018 top.execute.exe2 info} executeInst_: Executed inst: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' +{0000000019 00000019 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' +{0000000019 00000019 top.execute.exe2 info} completeInst_: Completing inst: uid:7 COMPLETED 0 pid:0 uopid:0 'add 16,14,15' +{0000000019 00000019 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to exe_pipe exe4 +{0000000019 00000019 top.execute.exe4 info} insertInst: Executing: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' for 20 {0000000019 00000019 top.dispatch info} receiveCredits_: iq2 got 1 credits, total: 8 {0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000020 00000020 top.execute.exe4 info} executeInst_: Executed inst: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' -{0000000021 00000021 top.execute.exe4 info} completeInst_: Completing inst: uid:8 COMPLETED 0 pid:0 uopid:0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to exe_pipe exe0 -{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' for 22 +{0000000020 00000020 top.execute.exe4 info} executeInst_: Executed inst: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' +{0000000021 00000021 top.execute.exe4 info} completeInst_: Completing inst: uid:8 COMPLETED 0 pid:0 uopid:0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to exe_pipe exe0 +{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' for 22 {0000000021 00000021 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' -{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid:9 COMPLETED 0 pid:0 uopid:0 'add 20,18,19' +{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' +{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid:9 COMPLETED 0 pid:0 uopid:0 'add 20,18,19' diff --git a/test/core/dispatch/expected_output/medium_core.out.EXPECTED b/test/core/dispatch/expected_output/medium_core.out.EXPECTED index b999934f..617d2ed0 100644 --- a/test/core/dispatch/expected_output/medium_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/medium_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Oct 8 16:46:24 2024 -#Elapsed: 0.001696s +#Start: Saturday Sat Oct 19 16:01:55 2024 +#Elapsed: 0.001281s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -44,18 +44,18 @@ {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add, 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add, 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0,3] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [5,32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [7,33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard @@ -63,191 +63,191 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add, 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to iq0 of target type: INT -{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to iq1 of target type: INT -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' stall: INT_BUSY +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to iq1 of target type: INT +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' stall: INT_BUSY {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [9,34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [11,35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [13,36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [15,37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 4 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add, 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' -{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' Bits needed:[0,3] rf: integer +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' +{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' Bits needed:[0,3] rf: integer {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' for 4 +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to iq0 of target type: INT -{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to iq1 of target type: INT -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' stall: INT_BUSY +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to iq1 of target type: INT +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' stall: INT_BUSY {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [17,38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [19,39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:10 RENAMED 0 pid:0 uopid:0 'add 22,20,21' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:10 RENAMED 0 pid:0 uopid:0 'add 22,20,21' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [21,40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:11 RENAMED 0 pid:0 uopid:0 'add 24,22,23' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:11 RENAMED 0 pid:0 uopid:0 'add 24,22,23' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [23,41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [42] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 4 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add, 0x00000000 UID(20) PID(0) add, 0x00000000 UID(21) PID(0) add -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' Bits needed:[5,32] rf: integer -{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' Bits needed:[7,33] rf: integer +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' Bits needed:[5,32] rf: integer +{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' Bits needed:[7,33] rf: integer {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to iq0 of target type: INT -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to iq1 of target type: INT -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' stall: INT_BUSY +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to iq0 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to iq1 of target type: INT +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' stall: INT_BUSY {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:12 RENAMED 0 pid:0 uopid:0 'add 26,24,25' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:12 RENAMED 0 pid:0 uopid:0 'add 26,24,25' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [25,42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [43] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:13 RENAMED 0 pid:0 uopid:0 'add 28,26,27' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:13 RENAMED 0 pid:0 uopid:0 'add 28,26,27' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [27,43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [44] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:14 RENAMED 0 pid:0 uopid:0 'add 30,28,29' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:14 RENAMED 0 pid:0 uopid:0 'add 30,28,29' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [29,44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [45] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:15 RENAMED 0 pid:0 uopid:0 'add 0,30,31' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:15 RENAMED 0 pid:0 uopid:0 'add 0,30,31' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [45] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [31,45] for 'integer' scoreboard {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 4 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(22) PID(0) add, 0x00000000 UID(23) PID(0) add, 0x00000000 UID(24) PID(0) add, 0x00000000 UID(25) PID(0) add -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' Bits needed:[9,34] rf: integer -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' Bits needed:[11,35] rf: integer +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' Bits needed:[9,34] rf: integer +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' Bits needed:[11,35] rf: integer {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add, 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add -{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid:0 COMPLETED 0 pid:0 uopid:0 'add 2,0,1' -{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to exe_pipe exe1 -{0000000005 00000005 top.execute.exe1 info} insertInst: Executing: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' for 6 +{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid:0 COMPLETED 0 pid:0 uopid:0 'add 2,0,1' +{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to exe_pipe exe1 +{0000000005 00000005 top.execute.exe1 info} insertInst: Executing: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' for 6 {0000000005 00000005 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 6 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to iq0 of target type: INT -{0000000005 00000005 top.dispatch info} acceptInst: iq1: dispatching uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to iq1 of target type: INT -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' stall: INT_BUSY +{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to iq0 of target type: INT +{0000000005 00000005 top.dispatch info} acceptInst: iq1: dispatching uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to iq1 of target type: INT +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' stall: INT_BUSY {0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:16 RENAMED 0 pid:0 uopid:0 'add 2,0,1' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:16 RENAMED 0 pid:0 uopid:0 'add 2,0,1' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [46] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:17 RENAMED 0 pid:0 uopid:0 'add 4,2,3' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:17 RENAMED 0 pid:0 uopid:0 'add 4,2,3' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [3,46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [47] for 'integer' scoreboard {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 2 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(26) PID(0) add, 0x00000000 UID(27) PID(0) add -{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' Bits needed:[13,36] rf: integer -{0000000006 00000006 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' Bits needed:[15,37] rf: integer +{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' Bits needed:[13,36] rf: integer +{0000000006 00000006 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' Bits needed:[15,37] rf: integer {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000006 00000006 top.execute.exe1 info} executeInst_: Executed inst: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' +{0000000006 00000006 top.execute.exe1 info} executeInst_: Executed inst: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' {0000000006 00000006 top.dispatch info} dispatchInstructions_: Num to dispatch: 2 -{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to iq0 of target type: INT -{0000000006 00000006 top.dispatch info} acceptInst: iq1: dispatching uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to iq1 of target type: INT +{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to iq0 of target type: INT +{0000000006 00000006 top.dispatch info} acceptInst: iq1: dispatching uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to iq1 of target type: INT {0000000006 00000006 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid:18 RENAMED 0 pid:0 uopid:0 'add 6,4,5' +{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid:18 RENAMED 0 pid:0 uopid:0 'add 6,4,5' {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [47] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [5,47] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [48] for 'integer' scoreboard -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid:19 RENAMED 0 pid:0 uopid:0 'add 8,6,7' +{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid:19 RENAMED 0 pid:0 uopid:0 'add 8,6,7' {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [48] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [7,48] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [49] for 'integer' scoreboard {0000000006 00000006 top.decode info} inCredits: Got credits from dut: 2 {0000000006 00000006 top.decode info} Sending group: 0x00000000 UID(28) PID(0) add, 0x00000000 UID(29) PID(0) add -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' Bits needed:[17,38] rf: integer -{0000000007 00000007 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' Bits needed:[19,39] rf: integer +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' Bits needed:[17,38] rf: integer +{0000000007 00000007 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' Bits needed:[19,39] rf: integer {0000000007 00000007 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add {0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000007 00000007 top.execute.exe1 info} completeInst_: Completing inst: uid:1 COMPLETED 0 pid:0 uopid:0 'add 4,2,3' -{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to exe_pipe exe0 -{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' for 8 +{0000000007 00000007 top.execute.exe1 info} completeInst_: Completing inst: uid:1 COMPLETED 0 pid:0 uopid:0 'add 4,2,3' +{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to exe_pipe exe0 +{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' for 8 {0000000007 00000007 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 5 {0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' -{0000000009 00000009 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' -{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid:2 COMPLETED 0 pid:0 uopid:0 'add 6,4,5' -{0000000009 00000009 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to exe_pipe exe1 -{0000000009 00000009 top.execute.exe1 info} insertInst: Executing: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' for 10 +{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' +{0000000009 00000009 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' +{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid:2 COMPLETED 0 pid:0 uopid:0 'add 6,4,5' +{0000000009 00000009 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to exe_pipe exe1 +{0000000009 00000009 top.execute.exe1 info} insertInst: Executing: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' for 10 {0000000009 00000009 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 5 {0000000009 00000009 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000010 00000010 top.execute.exe1 info} executeInst_: Executed inst: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' -{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' -{0000000011 00000011 top.execute.exe1 info} completeInst_: Completing inst: uid:3 COMPLETED 0 pid:0 uopid:0 'add 8,6,7' -{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to exe_pipe exe0 -{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' for 12 +{0000000010 00000010 top.execute.exe1 info} executeInst_: Executed inst: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' +{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' +{0000000011 00000011 top.execute.exe1 info} completeInst_: Completing inst: uid:3 COMPLETED 0 pid:0 uopid:0 'add 8,6,7' +{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to exe_pipe exe0 +{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' for 12 {0000000011 00000011 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000011 00000011 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' -{0000000013 00000013 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' -{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid:4 COMPLETED 0 pid:0 uopid:0 'add 10,8,9' -{0000000013 00000013 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to exe_pipe exe1 -{0000000013 00000013 top.execute.exe1 info} insertInst: Executing: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' for 14 +{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' +{0000000013 00000013 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' +{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid:4 COMPLETED 0 pid:0 uopid:0 'add 10,8,9' +{0000000013 00000013 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to exe_pipe exe1 +{0000000013 00000013 top.execute.exe1 info} insertInst: Executing: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' for 14 {0000000013 00000013 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 6 {0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000014 00000014 top.execute.exe1 info} executeInst_: Executed inst: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' -{0000000015 00000015 top.execute.exe1 info} completeInst_: Completing inst: uid:5 COMPLETED 0 pid:0 uopid:0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to exe_pipe exe0 -{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' for 16 +{0000000014 00000014 top.execute.exe1 info} executeInst_: Executed inst: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' +{0000000015 00000015 top.execute.exe1 info} completeInst_: Completing inst: uid:5 COMPLETED 0 pid:0 uopid:0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to exe_pipe exe0 +{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' for 16 {0000000015 00000015 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' -{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid:6 COMPLETED 0 pid:0 uopid:0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to exe_pipe exe1 -{0000000017 00000017 top.execute.exe1 info} insertInst: Executing: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' for 18 +{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' +{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid:6 COMPLETED 0 pid:0 uopid:0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to exe_pipe exe1 +{0000000017 00000017 top.execute.exe1 info} insertInst: Executing: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' for 18 {0000000017 00000017 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 7 {0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000018 00000018 top.execute.exe1 info} executeInst_: Executed inst: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' -{0000000019 00000019 top.execute.exe1 info} completeInst_: Completing inst: uid:7 COMPLETED 0 pid:0 uopid:0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to exe_pipe exe0 -{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' for 20 +{0000000018 00000018 top.execute.exe1 info} executeInst_: Executed inst: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' +{0000000019 00000019 top.execute.exe1 info} completeInst_: Completing inst: uid:7 COMPLETED 0 pid:0 uopid:0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to exe_pipe exe0 +{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' for 20 {0000000019 00000019 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' -{0000000021 00000021 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' -{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid:8 COMPLETED 0 pid:0 uopid:0 'add 18,16,17' -{0000000021 00000021 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to exe_pipe exe1 -{0000000021 00000021 top.execute.exe1 info} insertInst: Executing: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' for 22 +{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' +{0000000021 00000021 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' +{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid:8 COMPLETED 0 pid:0 uopid:0 'add 18,16,17' +{0000000021 00000021 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to exe_pipe exe1 +{0000000021 00000021 top.execute.exe1 info} insertInst: Executing: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' for 22 {0000000021 00000021 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 8 {0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000022 00000022 top.execute.exe1 info} executeInst_: Executed inst: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' -{0000000023 00000023 top.execute.exe1 info} completeInst_: Completing inst: uid:9 COMPLETED 0 pid:0 uopid:0 'add 20,18,19' +{0000000022 00000022 top.execute.exe1 info} executeInst_: Executed inst: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' +{0000000023 00000023 top.execute.exe1 info} completeInst_: Completing inst: uid:9 COMPLETED 0 pid:0 uopid:0 'add 20,18,19' diff --git a/test/core/dispatch/expected_output/small_core.out.EXPECTED b/test/core/dispatch/expected_output/small_core.out.EXPECTED index c5889fc6..f1f7eb08 100644 --- a/test/core/dispatch/expected_output/small_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/small_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Oct 8 16:46:24 2024 -#Elapsed: 0.002685s +#Start: Saturday Sat Oct 19 16:01:55 2024 +#Elapsed: 0.001895s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -38,18 +38,18 @@ {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add, 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add, 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0,3] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [5,32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [7,33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard @@ -57,218 +57,218 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add, 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to iq0 of target type: INT -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' stall: INT_BUSY +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' stall: INT_BUSY {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [9,34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [11,35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [13,36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [15,37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 4 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add, 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' for 4 +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to iq0 of target type: INT -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' stall: INT_BUSY +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' stall: INT_BUSY {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [17,38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [19,39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:10 RENAMED 0 pid:0 uopid:0 'add 22,20,21' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:10 RENAMED 0 pid:0 uopid:0 'add 22,20,21' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [21,40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:11 RENAMED 0 pid:0 uopid:0 'add 24,22,23' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:11 RENAMED 0 pid:0 uopid:0 'add 24,22,23' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [23,41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [42] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 4 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add, 0x00000000 UID(20) PID(0) add, 0x00000000 UID(21) PID(0) add -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' Bits needed:[0,3] rf: integer +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' Bits needed:[0,3] rf: integer {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to iq0 of target type: INT -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' stall: INT_BUSY +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to iq0 of target type: INT +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' stall: INT_BUSY {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:12 RENAMED 0 pid:0 uopid:0 'add 26,24,25' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:12 RENAMED 0 pid:0 uopid:0 'add 26,24,25' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [25,42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [43] for 'integer' scoreboard {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 1 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(22) PID(0) add -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' Bits needed:[5,32] rf: integer +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' Bits needed:[5,32] rf: integer {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(12) PID(0) add -{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid:0 COMPLETED 0 pid:0 uopid:0 'add 2,0,1' -{0000000005 00000005 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to exe_pipe exe0 -{0000000005 00000005 top.execute.exe0 info} insertInst: Executing: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' for 6 +{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid:0 COMPLETED 0 pid:0 uopid:0 'add 2,0,1' +{0000000005 00000005 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to exe_pipe exe0 +{0000000005 00000005 top.execute.exe0 info} insertInst: Executing: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' for 6 {0000000005 00000005 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to iq0 of target type: INT -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' stall: INT_BUSY +{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to iq0 of target type: INT +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' stall: INT_BUSY {0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:13 RENAMED 0 pid:0 uopid:0 'add 28,26,27' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:13 RENAMED 0 pid:0 uopid:0 'add 28,26,27' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [43] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [27,43] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [44] for 'integer' scoreboard {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 1 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(23) PID(0) add -{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' Bits needed:[7,33] rf: integer +{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' Bits needed:[7,33] rf: integer {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(13) PID(0) add -{0000000006 00000006 top.execute.exe0 info} executeInst_: Executed inst: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' +{0000000006 00000006 top.execute.exe0 info} executeInst_: Executed inst: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' {0000000006 00000006 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to iq0 of target type: INT -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' stall: INT_BUSY +{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to iq0 of target type: INT +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' stall: INT_BUSY {0000000006 00000006 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid:14 RENAMED 0 pid:0 uopid:0 'add 30,28,29' +{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid:14 RENAMED 0 pid:0 uopid:0 'add 30,28,29' {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [44] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [29,44] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [45] for 'integer' scoreboard {0000000006 00000006 top.decode info} inCredits: Got credits from dut: 1 {0000000006 00000006 top.decode info} Sending group: 0x00000000 UID(24) PID(0) add -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' Bits needed:[9,34] rf: integer +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' Bits needed:[9,34] rf: integer {0000000007 00000007 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(14) PID(0) add -{0000000007 00000007 top.execute.exe0 info} completeInst_: Completing inst: uid:1 COMPLETED 0 pid:0 uopid:0 'add 4,2,3' -{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to exe_pipe exe0 -{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' for 8 +{0000000007 00000007 top.execute.exe0 info} completeInst_: Completing inst: uid:1 COMPLETED 0 pid:0 uopid:0 'add 4,2,3' +{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to exe_pipe exe0 +{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' for 8 {0000000007 00000007 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000007 00000007 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000007 00000007 top.dispatch info} acceptInst: iq0: dispatching uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' -{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to iq0 of target type: INT -{0000000007 00000007 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' stall: INT_BUSY +{0000000007 00000007 top.dispatch info} acceptInst: iq0: dispatching uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' +{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to iq0 of target type: INT +{0000000007 00000007 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' stall: INT_BUSY {0000000007 00000007 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000007 00000007 top.rename info} renameInstructions_: sending inst to dispatch: uid:15 RENAMED 0 pid:0 uopid:0 'add 0,30,31' +{0000000007 00000007 top.rename info} renameInstructions_: sending inst to dispatch: uid:15 RENAMED 0 pid:0 uopid:0 'add 0,30,31' {0000000007 00000007 top.rename info} renameInstructions_: setup source register bit mask [45] for 'integer' scoreboard {0000000007 00000007 top.rename info} renameInstructions_: setup source register bit mask [31,45] for 'integer' scoreboard {0000000007 00000007 top.decode info} inCredits: Got credits from dut: 1 {0000000007 00000007 top.decode info} Sending group: 0x00000000 UID(25) PID(0) add -{0000000008 00000008 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' Bits needed:[11,35] rf: integer +{0000000008 00000008 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' Bits needed:[11,35] rf: integer {0000000008 00000008 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(15) PID(0) add -{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' +{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' {0000000008 00000008 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000008 00000008 top.dispatch info} acceptInst: iq0: dispatching uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' -{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to iq0 of target type: INT -{0000000008 00000008 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' stall: INT_BUSY +{0000000008 00000008 top.dispatch info} acceptInst: iq0: dispatching uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' +{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to iq0 of target type: INT +{0000000008 00000008 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' stall: INT_BUSY {0000000008 00000008 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000008 00000008 top.rename info} renameInstructions_: sending inst to dispatch: uid:16 RENAMED 0 pid:0 uopid:0 'add 2,0,1' +{0000000008 00000008 top.rename info} renameInstructions_: sending inst to dispatch: uid:16 RENAMED 0 pid:0 uopid:0 'add 2,0,1' {0000000008 00000008 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000008 00000008 top.rename info} renameInstructions_: setup destination register bit mask [46] for 'integer' scoreboard {0000000008 00000008 top.decode info} inCredits: Got credits from dut: 1 {0000000008 00000008 top.decode info} Sending group: 0x00000000 UID(26) PID(0) add -{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' -{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' Bits needed:[13,36] rf: integer +{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' +{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' Bits needed:[13,36] rf: integer {0000000009 00000009 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(16) PID(0) add -{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid:2 COMPLETED 0 pid:0 uopid:0 'add 6,4,5' -{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to exe_pipe exe0 -{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' for 10 +{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid:2 COMPLETED 0 pid:0 uopid:0 'add 6,4,5' +{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to exe_pipe exe0 +{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' for 10 {0000000009 00000009 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 5 {0000000009 00000009 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000009 00000009 top.dispatch info} acceptInst: iq0: dispatching uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' -{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to iq0 of target type: INT -{0000000009 00000009 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' stall: INT_BUSY +{0000000009 00000009 top.dispatch info} acceptInst: iq0: dispatching uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' +{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to iq0 of target type: INT +{0000000009 00000009 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' stall: INT_BUSY {0000000009 00000009 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000009 00000009 top.rename info} renameInstructions_: sending inst to dispatch: uid:17 RENAMED 0 pid:0 uopid:0 'add 4,2,3' +{0000000009 00000009 top.rename info} renameInstructions_: sending inst to dispatch: uid:17 RENAMED 0 pid:0 uopid:0 'add 4,2,3' {0000000009 00000009 top.rename info} renameInstructions_: setup source register bit mask [46] for 'integer' scoreboard {0000000009 00000009 top.rename info} renameInstructions_: setup source register bit mask [3,46] for 'integer' scoreboard {0000000009 00000009 top.rename info} renameInstructions_: setup destination register bit mask [47] for 'integer' scoreboard {0000000009 00000009 top.decode info} inCredits: Got credits from dut: 1 {0000000009 00000009 top.decode info} Sending group: 0x00000000 UID(27) PID(0) add -{0000000010 00000010 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' Bits needed:[15,37] rf: integer +{0000000010 00000010 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' Bits needed:[15,37] rf: integer {0000000010 00000010 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(17) PID(0) add -{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' +{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' {0000000010 00000010 top.dispatch info} dispatchInstructions_: Num to dispatch: 2 -{0000000010 00000010 top.dispatch info} acceptInst: iq0: dispatching uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' -{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to iq0 of target type: INT -{0000000010 00000010 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' stall: INT_BUSY +{0000000010 00000010 top.dispatch info} acceptInst: iq0: dispatching uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' +{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to iq0 of target type: INT +{0000000010 00000010 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' stall: INT_BUSY {0000000010 00000010 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000010 00000010 top.rename info} renameInstructions_: sending inst to dispatch: uid:18 RENAMED 0 pid:0 uopid:0 'add 6,4,5' +{0000000010 00000010 top.rename info} renameInstructions_: sending inst to dispatch: uid:18 RENAMED 0 pid:0 uopid:0 'add 6,4,5' {0000000010 00000010 top.rename info} renameInstructions_: setup source register bit mask [47] for 'integer' scoreboard {0000000010 00000010 top.rename info} renameInstructions_: setup source register bit mask [5,47] for 'integer' scoreboard {0000000010 00000010 top.rename info} renameInstructions_: setup destination register bit mask [48] for 'integer' scoreboard {0000000010 00000010 top.decode info} inCredits: Got credits from dut: 1 {0000000010 00000010 top.decode info} Sending group: 0x00000000 UID(28) PID(0) add -{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' -{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' Bits needed:[17,38] rf: integer +{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' +{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' Bits needed:[17,38] rf: integer {0000000011 00000011 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(18) PID(0) add -{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid:3 COMPLETED 0 pid:0 uopid:0 'add 8,6,7' -{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to exe_pipe exe0 -{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' for 12 +{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid:3 COMPLETED 0 pid:0 uopid:0 'add 8,6,7' +{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to exe_pipe exe0 +{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' for 12 {0000000011 00000011 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 4 {0000000011 00000011 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000011 00000011 top.dispatch info} acceptInst: iq0: dispatching uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' -{0000000011 00000011 top.dispatch info} dispatchInstructions_: Sending instruction: uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to iq0 of target type: INT +{0000000011 00000011 top.dispatch info} acceptInst: iq0: dispatching uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' +{0000000011 00000011 top.dispatch info} dispatchInstructions_: Sending instruction: uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to iq0 of target type: INT {0000000011 00000011 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000011 00000011 top.rename info} renameInstructions_: sending inst to dispatch: uid:19 RENAMED 0 pid:0 uopid:0 'add 8,6,7' +{0000000011 00000011 top.rename info} renameInstructions_: sending inst to dispatch: uid:19 RENAMED 0 pid:0 uopid:0 'add 8,6,7' {0000000011 00000011 top.rename info} renameInstructions_: setup source register bit mask [48] for 'integer' scoreboard {0000000011 00000011 top.rename info} renameInstructions_: setup source register bit mask [7,48] for 'integer' scoreboard {0000000011 00000011 top.rename info} renameInstructions_: setup destination register bit mask [49] for 'integer' scoreboard {0000000011 00000011 top.decode info} inCredits: Got credits from dut: 1 {0000000011 00000011 top.decode info} Sending group: 0x00000000 UID(29) PID(0) add -{0000000012 00000012 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' Bits needed:[19,39] rf: integer +{0000000012 00000012 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' Bits needed:[19,39] rf: integer {0000000012 00000012 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(19) PID(0) add {0000000012 00000012 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' -{0000000013 00000013 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' -{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid:4 COMPLETED 0 pid:0 uopid:0 'add 10,8,9' -{0000000013 00000013 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to exe_pipe exe0 -{0000000013 00000013 top.execute.exe0 info} insertInst: Executing: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' for 14 +{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' +{0000000013 00000013 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' +{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid:4 COMPLETED 0 pid:0 uopid:0 'add 10,8,9' +{0000000013 00000013 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to exe_pipe exe0 +{0000000013 00000013 top.execute.exe0 info} insertInst: Executing: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' for 14 {0000000013 00000013 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 4 {0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000014 00000014 top.execute.exe0 info} executeInst_: Executed inst: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' -{0000000015 00000015 top.execute.exe0 info} completeInst_: Completing inst: uid:5 COMPLETED 0 pid:0 uopid:0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to exe_pipe exe0 -{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' for 16 +{0000000014 00000014 top.execute.exe0 info} executeInst_: Executed inst: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' +{0000000015 00000015 top.execute.exe0 info} completeInst_: Completing inst: uid:5 COMPLETED 0 pid:0 uopid:0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to exe_pipe exe0 +{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' for 16 {0000000015 00000015 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 5 {0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' -{0000000017 00000017 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' -{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid:6 COMPLETED 0 pid:0 uopid:0 'add 14,12,13' -{0000000017 00000017 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to exe_pipe exe0 -{0000000017 00000017 top.execute.exe0 info} insertInst: Executing: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' for 18 +{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' +{0000000017 00000017 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' +{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid:6 COMPLETED 0 pid:0 uopid:0 'add 14,12,13' +{0000000017 00000017 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to exe_pipe exe0 +{0000000017 00000017 top.execute.exe0 info} insertInst: Executing: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' for 18 {0000000017 00000017 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000018 00000018 top.execute.exe0 info} executeInst_: Executed inst: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' -{0000000019 00000019 top.execute.exe0 info} completeInst_: Completing inst: uid:7 COMPLETED 0 pid:0 uopid:0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to exe_pipe exe0 -{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' for 20 +{0000000018 00000018 top.execute.exe0 info} executeInst_: Executed inst: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' +{0000000019 00000019 top.execute.exe0 info} completeInst_: Completing inst: uid:7 COMPLETED 0 pid:0 uopid:0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to exe_pipe exe0 +{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' for 20 {0000000019 00000019 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' -{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid:8 COMPLETED 0 pid:0 uopid:0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to exe_pipe exe0 -{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' for 22 +{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' +{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid:8 COMPLETED 0 pid:0 uopid:0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to exe_pipe exe0 +{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' for 22 {0000000021 00000021 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' -{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid:9 COMPLETED 0 pid:0 uopid:0 'add 20,18,19' +{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' +{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid:9 COMPLETED 0 pid:0 uopid:0 'add 20,18,19' diff --git a/test/core/l2cache/expected_output/hit_case.out.EXPECTED b/test/core/l2cache/expected_output/hit_case.out.EXPECTED index 94443f92..9d54cecf 100644 --- a/test/core/l2cache/expected_output/hit_case.out.EXPECTED +++ b/test/core/l2cache/expected_output/hit_case.out.EXPECTED @@ -3,43 +3,43 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Oct 8 16:48:48 2024 -#Elapsed: 0.00378s +#Start: Saturday Sat Oct 19 15:35:23 2024 +#Elapsed: 0.002228s {0000000000 00000000 top.l2cache info} L2Cache: L2Cache construct: #4294967295 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to ICache : 8 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to DCache : 8 {0000000000 00000000 top.biu info} sendInitialCredits_: Sending initial credits to L2Cache : 32 -{0000000000 00000000 top.icache info} ReceiveAck_: Ack: '8' Received -{0000000000 00000000 top.dcache info} ReceiveAck_: Ack: '8' Received -{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Requested -{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Requested -{0000000001 00000001 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 +{0000000000 00000000 top.icache info} ReceiveCredits_: Ack: '8' Received +{0000000000 00000000 top.dcache info} ReceiveCredits_: Ack: '8' Received +{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' ' Requested +{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' ' Requested +{0000000001 00000001 top.l2cache info} getCreditsFromBIU_: Credits received from BIU on the port : Current BIU credit available = 32 {0000000001 00000001 top.l2cache info} getReqFromDCache_: Request received from DCache on the port {0000000001 00000001 top.l2cache info} appendDCacheReqQueue_: Append DCache->L2Cache request queue! {0000000001 00000001 top.l2cache info} getReqFromICache_: Request received from ICache on the port {0000000001 00000001 top.l2cache info} appendICacheReqQueue_: Append ICache->L2Cache request queue! {0000000001 00000001 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - ICache {0000000001 00000001 top.l2cache info} create_Req_: ICache request is sent to Pipeline_req_Q! -{0000000002 00000002 top.icache info} ReceiveAck_: Ack: '8' Received -{0000000002 00000002 top.l2cache info} handle_L2Cache_ICache_Ack_: L2Cache->ICache : Ack is sent. +{0000000001 00000001 top.l2cache info} create_Req_: L2Cache->ICache : Credit is sent. +{0000000002 00000002 top.icache info} ReceiveCredits_: Ack: '1' Received {0000000002 00000002 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : ICACHE {0000000002 00000002 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - DCache {0000000002 00000002 top.l2cache info} create_Req_: DCache request is sent to Pipeline_req_Q! -{0000000003 00000003 top.dcache info} ReceiveAck_: Ack: '8' Received -{0000000003 00000003 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. +{0000000002 00000002 top.l2cache info} create_Req_: L2Cache->DCache : Credit is sent. +{0000000003 00000003 top.dcache info} ReceiveCredits_: Ack: '1' Received {0000000003 00000003 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000011 00000011 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000012 00000012 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000012 00000012 top.l2cache info} appendBIUReqQueue_: Append L2Cache->BIU req queue {0000000012 00000012 top.l2cache info} handle_L2Cache_BIU_Req_: L2Cache Request sent to BIU : Current BIU credit available = 31 -{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' sinked -{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' ' sinked +{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ -{0000000024 00000024 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 +{0000000024 00000024 top.l2cache info} getCreditsFromBIU_: Credits received from BIU on the port : Current BIU credit available = 32 {0000000034 00000034 top.l2cache info} getRespFromBIU_: Response received from BIU on the port {0000000034 00000034 top.l2cache info} appendBIURespQueue_: Append BIU->L2Cache resp queue! {0000000034 00000034 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU @@ -48,44 +48,44 @@ {0000000035 00000035 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU {0000000035 00000035 top.l2cache info} create_Req_: Request found in miss_pending_buffer_ with SrcUnit : DCACHE {0000000036 00000036 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : BIU -{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000044 00000044 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef {0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Reload Complete: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000045 00000045 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000045 00000045 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000045 00000045 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! -{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Received -{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' ' Received +{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000046 00000046 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000046 00000046 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! -{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Received -{0000000050 00000050 top.dcache info} req_inst_: Instruction: 'uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' ' Requested -{0000000050 00000050 top.icache info} req_inst_: Instruction: 'uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' ' Requested +{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' ' Received +{0000000050 00000050 top.dcache info} req_inst_: Instruction: 'uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3,4' ' Requested +{0000000050 00000050 top.icache info} req_inst_: Instruction: 'uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3,4' ' Requested {0000000051 00000051 top.l2cache info} getReqFromDCache_: Request received from DCache on the port {0000000051 00000051 top.l2cache info} appendDCacheReqQueue_: Append DCache->L2Cache request queue! {0000000051 00000051 top.l2cache info} getReqFromICache_: Request received from ICache on the port {0000000051 00000051 top.l2cache info} appendICacheReqQueue_: Append ICache->L2Cache request queue! {0000000051 00000051 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - ICache {0000000051 00000051 top.l2cache info} create_Req_: ICache request is sent to Pipeline_req_Q! -{0000000052 00000052 top.icache info} ReceiveAck_: Ack: '8' Received -{0000000052 00000052 top.l2cache info} handle_L2Cache_ICache_Ack_: L2Cache->ICache : Ack is sent. +{0000000051 00000051 top.l2cache info} create_Req_: L2Cache->ICache : Credit is sent. +{0000000052 00000052 top.icache info} ReceiveCredits_: Ack: '1' Received {0000000052 00000052 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : ICACHE {0000000052 00000052 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - DCache {0000000052 00000052 top.l2cache info} create_Req_: DCache request is sent to Pipeline_req_Q! -{0000000053 00000053 top.dcache info} ReceiveAck_: Ack: '8' Received -{0000000053 00000053 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. +{0000000052 00000052 top.l2cache info} create_Req_: L2Cache->DCache : Credit is sent. +{0000000053 00000053 top.dcache info} ReceiveCredits_: Ack: '1' Received {0000000053 00000053 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000061 00000061 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' +{0000000061 00000061 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3,4' {0000000061 00000061 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000062 00000062 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' +{0000000062 00000062 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3,4' {0000000062 00000062 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000062 00000062 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' +{0000000062 00000062 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3,4' {0000000062 00000062 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000062 00000062 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! -{0000000063 00000063 top.icache info} ReceiveInst_: Instruction: 'uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' ' Received -{0000000063 00000063 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' +{0000000063 00000063 top.icache info} ReceiveInst_: Instruction: 'uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3,4' ' Received +{0000000063 00000063 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3,4' {0000000063 00000063 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000063 00000063 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! -{0000000064 00000064 top.dcache info} ReceiveInst_: Instruction: 'uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' ' Received +{0000000064 00000064 top.dcache info} ReceiveInst_: Instruction: 'uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3,4' ' Received diff --git a/test/core/l2cache/expected_output/single_access.out.EXPECTED b/test/core/l2cache/expected_output/single_access.out.EXPECTED index 9aa80273..0305e07a 100644 --- a/test/core/l2cache/expected_output/single_access.out.EXPECTED +++ b/test/core/l2cache/expected_output/single_access.out.EXPECTED @@ -3,43 +3,43 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Oct 8 16:48:48 2024 -#Elapsed: 0.00446s +#Start: Saturday Sat Oct 19 15:35:23 2024 +#Elapsed: 0.00223s {0000000000 00000000 top.l2cache info} L2Cache: L2Cache construct: #4294967295 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to ICache : 8 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to DCache : 8 {0000000000 00000000 top.biu info} sendInitialCredits_: Sending initial credits to L2Cache : 32 -{0000000000 00000000 top.icache info} ReceiveAck_: Ack: '8' Received -{0000000000 00000000 top.dcache info} ReceiveAck_: Ack: '8' Received -{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Requested -{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Requested -{0000000001 00000001 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 +{0000000000 00000000 top.icache info} ReceiveCredits_: Ack: '8' Received +{0000000000 00000000 top.dcache info} ReceiveCredits_: Ack: '8' Received +{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' ' Requested +{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' ' Requested +{0000000001 00000001 top.l2cache info} getCreditsFromBIU_: Credits received from BIU on the port : Current BIU credit available = 32 {0000000001 00000001 top.l2cache info} getReqFromDCache_: Request received from DCache on the port {0000000001 00000001 top.l2cache info} appendDCacheReqQueue_: Append DCache->L2Cache request queue! {0000000001 00000001 top.l2cache info} getReqFromICache_: Request received from ICache on the port {0000000001 00000001 top.l2cache info} appendICacheReqQueue_: Append ICache->L2Cache request queue! {0000000001 00000001 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - ICache {0000000001 00000001 top.l2cache info} create_Req_: ICache request is sent to Pipeline_req_Q! -{0000000002 00000002 top.icache info} ReceiveAck_: Ack: '8' Received -{0000000002 00000002 top.l2cache info} handle_L2Cache_ICache_Ack_: L2Cache->ICache : Ack is sent. +{0000000001 00000001 top.l2cache info} create_Req_: L2Cache->ICache : Credit is sent. +{0000000002 00000002 top.icache info} ReceiveCredits_: Ack: '1' Received {0000000002 00000002 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : ICACHE {0000000002 00000002 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - DCache {0000000002 00000002 top.l2cache info} create_Req_: DCache request is sent to Pipeline_req_Q! -{0000000003 00000003 top.dcache info} ReceiveAck_: Ack: '8' Received -{0000000003 00000003 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. +{0000000002 00000002 top.l2cache info} create_Req_: L2Cache->DCache : Credit is sent. +{0000000003 00000003 top.dcache info} ReceiveCredits_: Ack: '1' Received {0000000003 00000003 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000011 00000011 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000012 00000012 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000012 00000012 top.l2cache info} appendBIUReqQueue_: Append L2Cache->BIU req queue {0000000012 00000012 top.l2cache info} handle_L2Cache_BIU_Req_: L2Cache Request sent to BIU : Current BIU credit available = 31 -{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' sinked -{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' ' sinked +{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ -{0000000024 00000024 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 +{0000000024 00000024 top.l2cache info} getCreditsFromBIU_: Credits received from BIU on the port : Current BIU credit available = 32 {0000000034 00000034 top.l2cache info} getRespFromBIU_: Response received from BIU on the port {0000000034 00000034 top.l2cache info} appendBIURespQueue_: Append BIU->L2Cache resp queue! {0000000034 00000034 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU @@ -48,16 +48,16 @@ {0000000035 00000035 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU {0000000035 00000035 top.l2cache info} create_Req_: Request found in miss_pending_buffer_ with SrcUnit : DCACHE {0000000036 00000036 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : BIU -{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000044 00000044 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef {0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Reload Complete: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000045 00000045 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000045 00000045 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000045 00000045 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! -{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Received -{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' ' Received +{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000046 00000046 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000046 00000046 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! -{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Received +{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' ' Received diff --git a/test/core/rename/expected_output/big_core.out.EXPECTED b/test/core/rename/expected_output/big_core.out.EXPECTED index 02c33544..7a820eb1 100644 --- a/test/core/rename/expected_output/big_core.out.EXPECTED +++ b/test/core/rename/expected_output/big_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Oct 8 16:47:17 2024 -#Elapsed: 0.002245s +#Start: Saturday Sat Oct 19 16:27:18 2024 +#Elapsed: 0.002659s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: DIViq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq1 @@ -51,7 +51,7 @@ {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -59,43 +59,43 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq1 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2 DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq1 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:4 uopid:0 'sub 14,13,12' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:4 uopid:0 'sub 14,13,12' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard diff --git a/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED b/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED index f98a7fc0..f2a7c9d7 100644 --- a/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED +++ b/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Oct 8 16:47:54 2024 -#Elapsed: 0.003636s +#Start: Saturday Sat Oct 19 16:27:18 2024 +#Elapsed: 0.003002s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: DIViq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq1 @@ -51,7 +51,7 @@ {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -59,39 +59,39 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq1 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2 DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq1 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NO_RENAMES diff --git a/test/core/rename/expected_output/medium_core.out.EXPECTED b/test/core/rename/expected_output/medium_core.out.EXPECTED index 710dddf4..efdddaf0 100644 --- a/test/core/rename/expected_output/medium_core.out.EXPECTED +++ b/test/core/rename/expected_output/medium_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Oct 8 16:47:05 2024 -#Elapsed: 0.003742s +#Start: Saturday Sat Oct 19 16:27:18 2024 +#Elapsed: 0.002592s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -44,7 +44,7 @@ {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -52,43 +52,43 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq0 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2 DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq0 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:4 uopid:0 'sub 14,13,12' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:4 uopid:0 'sub 14,13,12' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard diff --git a/test/core/rename/expected_output/small_core.out.EXPECTED b/test/core/rename/expected_output/small_core.out.EXPECTED index 36d8a20b..7f7f3329 100644 --- a/test/core/rename/expected_output/small_core.out.EXPECTED +++ b/test/core/rename/expected_output/small_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Oct 8 16:47:26 2024 -#Elapsed: 0.003386s +#Start: Saturday Sat Oct 19 16:27:18 2024 +#Elapsed: 0.002441s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -38,7 +38,7 @@ {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -46,43 +46,43 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq0 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2 DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq0 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:4 uopid:0 'sub 14,13,12' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:4 uopid:0 'sub 14,13,12' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard From e73e93adac112bb8c4c347deceb28bac9d450a1f Mon Sep 17 00:00:00 2001 From: Shobhit Date: Mon, 21 Oct 2024 19:08:46 +0530 Subject: [PATCH 13/14] Remove generated log files --- test/core/Testing/Temporary/LastTest.log | 3 --- test/core/l2cache/Testing/Temporary/LastTest.log | 3 --- 2 files changed, 6 deletions(-) delete mode 100644 test/core/Testing/Temporary/LastTest.log delete mode 100644 test/core/l2cache/Testing/Temporary/LastTest.log diff --git a/test/core/Testing/Temporary/LastTest.log b/test/core/Testing/Temporary/LastTest.log deleted file mode 100644 index 8e504756..00000000 --- a/test/core/Testing/Temporary/LastTest.log +++ /dev/null @@ -1,3 +0,0 @@ -Start testing: Sep 23 23:54 IST ----------------------------------------------------------- -End testing: Sep 23 23:54 IST diff --git a/test/core/l2cache/Testing/Temporary/LastTest.log b/test/core/l2cache/Testing/Temporary/LastTest.log deleted file mode 100644 index 8e504756..00000000 --- a/test/core/l2cache/Testing/Temporary/LastTest.log +++ /dev/null @@ -1,3 +0,0 @@ -Start testing: Sep 23 23:54 IST ----------------------------------------------------------- -End testing: Sep 23 23:54 IST From f0b0f057c9c3448cd43e7ba7c42547e2598428ac Mon Sep 17 00:00:00 2001 From: Shobhit Date: Thu, 31 Oct 2024 06:31:26 +0530 Subject: [PATCH 14/14] Revert stflib to be consistent with upstream branch --- stf_lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/stf_lib b/stf_lib index 83bb798e..b874cc0c 160000 --- a/stf_lib +++ b/stf_lib @@ -1 +1 @@ -Subproject commit 83bb798e0e6b009b99fc510dca7f3d8f740d0445 +Subproject commit b874cc0c8dc6a7e95fe00c2f9cd8e4504270d395