From ac52ca05359c24edb433f6312d7e583e6108ff02 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christoph=20M=C3=BCllner?= Date: Tue, 16 Jan 2024 22:11:00 +0100 Subject: [PATCH 1/8] generator.py: Drop toint() of integer value MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The recently introduced toint() function does not accept arguments of type int and will trigger an exception in this case. This leads to an always crashing code path in generator.py, where rm_dict[] maps the rounding mode string to an integer, that is then passed to toint(). There are several ways to address this (e.g. mapping to a string, or making toint() more robust), but dropping the call to toint() is obviously the right thing to do. Signed-off-by: Christoph Müllner --- riscv_ctg/generator.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv_ctg/generator.py b/riscv_ctg/generator.py index d666b408..05892d0b 100644 --- a/riscv_ctg/generator.py +++ b/riscv_ctg/generator.py @@ -827,7 +827,7 @@ def eval_inst_coverage(coverpoints,instr): else: var_dict['imm_val'] = toint(instr['imm_val']) elif key == 'rm_val': - var_dict['rm_val'] = toint(rm_dict[instr['rm_val']]) + var_dict['rm_val'] = rm_dict[instr['rm_val']] else: var_dict[key] = toint(instr[key]) for key in self.op_vars: From 2ad9ab9536d3fad061a7e0c329829cd86bca2c12 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christoph=20M=C3=BCllner?= Date: Tue, 28 Mar 2023 11:26:18 +0200 Subject: [PATCH 2/8] Add support for the Zfa ISA extension MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch introduces the RISC-V Zfa extension, which introduces additional floating-point extensions: * fli (load-immediate) with pre-defined immediates * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) * fround/froundmx (round to integer) * fcvtmod.w.d (Modular Convert-to-Integer) * fmv* to access high bits of float register bigger than XLEN * Quiet comparison instructions (fleq/fltq) Zfa defines its instructions in combination with the following extensions: * single-precision floating-point (F) * double-precision floating-point (D) * quad-precision floating-point (Q) * half-precision floating-point (Zfh) Since riscv-ctg does not support the RISC-V quad-precision floating-point ISA extension (Q) as well as the RISC-V half-precision floating-point ISA extension (Zfh), this patch does not include the instructions that depend on these extensions. All other instructions are included in this patch. The instruction descriptions (simple_cgfs/zfa/*) use different instructions as parameter for the coverpoint generator functions (e.g. fleq.s uses "fle.s") to circumvent documented limitations of these generator functions. Technically there is no reason to adjust generator.py. All required information could be extracted from instruction descriptions. However, that is not the case, and the file also includes its own hard-coded assumptions, which have to be adjusted as well. The Zfa specification can be found here: https://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex Signed-off-by: Christoph Müllner --- riscv_ctg/data/fd.yaml | 410 ++++++++++++++++++++++++++++++++ riscv_ctg/env/arch_test.h | 13 +- riscv_ctg/generator.py | 34 ++- sample_cgfs/zfa/fcvtmod.w.d.cgf | 92 +++++++ sample_cgfs/zfa/fleq.d.cgf | 35 +++ sample_cgfs/zfa/fleq.s.cgf | 35 +++ sample_cgfs/zfa/fltq.d.cgf | 35 +++ sample_cgfs/zfa/fltq.s.cgf | 35 +++ sample_cgfs/zfa/fmaxm.d.cgf | 35 +++ sample_cgfs/zfa/fmaxm.s.cgf | 35 +++ sample_cgfs/zfa/fminm.d.cgf | 35 +++ sample_cgfs/zfa/fminm.s.cgf | 35 +++ sample_cgfs/zfa/fmvh.x.d.cgf | 92 +++++++ sample_cgfs/zfa/fmvp.d.x.cgf | 33 +++ sample_cgfs/zfa/fround.d.cgf | 16 ++ sample_cgfs/zfa/fround.s.cgf | 16 ++ sample_cgfs/zfa/froundnx.d.cgf | 16 ++ sample_cgfs/zfa/froundnx.s.cgf | 16 ++ 18 files changed, 1013 insertions(+), 5 deletions(-) create mode 100644 sample_cgfs/zfa/fcvtmod.w.d.cgf create mode 100644 sample_cgfs/zfa/fleq.d.cgf create mode 100644 sample_cgfs/zfa/fleq.s.cgf create mode 100644 sample_cgfs/zfa/fltq.d.cgf create mode 100644 sample_cgfs/zfa/fltq.s.cgf create mode 100644 sample_cgfs/zfa/fmaxm.d.cgf create mode 100644 sample_cgfs/zfa/fmaxm.s.cgf create mode 100644 sample_cgfs/zfa/fminm.d.cgf create mode 100644 sample_cgfs/zfa/fminm.s.cgf create mode 100644 sample_cgfs/zfa/fmvh.x.d.cgf create mode 100644 sample_cgfs/zfa/fmvp.d.x.cgf create mode 100644 sample_cgfs/zfa/fround.d.cgf create mode 100644 sample_cgfs/zfa/fround.s.cgf create mode 100644 sample_cgfs/zfa/froundnx.d.cgf create mode 100644 sample_cgfs/zfa/froundnx.s.cgf diff --git a/riscv_ctg/data/fd.yaml b/riscv_ctg/data/fd.yaml index 4a6e60ab..8cdc83b8 100644 --- a/riscv_ctg/data/fd.yaml +++ b/riscv_ctg/data/fd.yaml @@ -1709,3 +1709,413 @@ fcvt.s.lu: fcsr_val: $fcsr*/ TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) +# +# Zfa extension +# + +fminm.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfa + - IFD_Zicsr_Zfa + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fminm.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfa + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmaxm.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfa + - IFD_Zicsr_Zfa + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmaxm.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfa + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fround.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfa + - IFD_Zicsr_Zfa + flen: [32,64] + std_op: + formattype: 'fsrformat' + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + rs1_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fround.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfa + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +froundnx.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfa + - IFD_Zicsr_Zfa + flen: [32,64] + std_op: + formattype: 'fsrformat' + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + rs1_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +froundnx.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfa + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmvh.x.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32] + isa: + - IFD_Zicsr_Zfa + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmvh.d.x: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: '4' + val_template: "'.word $val;'" + load_instr: "lw" + xlen: [32] + isa: + - IFD_Zicsr_Zfa + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIOIO_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvtmod.w.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfa + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fltq.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfa + - IFD_Zicsr_Zfa + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fltq.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfa + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fleq.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfa + - IFD_Zicsr_Zfa + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fleq.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfa + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) diff --git a/riscv_ctg/env/arch_test.h b/riscv_ctg/env/arch_test.h index 98f3f9ea..eb4cb3e3 100644 --- a/riscv_ctg/env/arch_test.h +++ b/riscv_ctg/env/arch_test.h @@ -1037,7 +1037,7 @@ RVTEST_SIGUPD_F(swreg,destreg,flagreg) csrr flagreg, fcsr ; \ ) -//Tests for floating-point instructions with a single register operand and integer operand register +//Tests for floating-point instructions with one GPR operand and a single FPR result //This variant does not take the rm field and set it while writing the instruction #define TEST_FPIO_OP_NRM( inst, destreg, freg, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg, load_instr) \ TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ @@ -1047,6 +1047,17 @@ RVTEST_SIGUPD_F(swreg,destreg,flagreg) csrr flagreg, fcsr; \ ) +//Tests for floating-point instructions with two GPR operands and a single FPR result +//This variant does not take the rm field and set it while writing the instruction +#define TEST_FPIOIO_OP_NRM(inst, destreg, freg1, freg2, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg, load_instr) \ + TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(load_instr, valaddr_reg, freg1, val_offset, testreg); \ + LOAD_MEM_VAL(load_instr, valaddr_reg, freg2, (val_offset+FREGWIDTH), testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg; \ + csrr flagreg, fcsr; \ + ) + //Tests for instructions with register-register-immediate operands #define TEST_RRI_OP(inst, destreg, reg1, reg2, imm, correctval, val1, val2, swreg, offset, testreg) \ TEST_CASE(testreg, destreg, correctval, swreg, offset, \ diff --git a/riscv_ctg/generator.py b/riscv_ctg/generator.py index 05892d0b..5bf34f68 100644 --- a/riscv_ctg/generator.py +++ b/riscv_ctg/generator.py @@ -14,13 +14,32 @@ import itertools import re +# F one_operand_finstructions = ["fsqrt.s","fmv.x.w","fcvt.wu.s","fcvt.w.s","fclass.s","fcvt.l.s","fcvt.lu.s","fcvt.s.l","fcvt.s.lu"] two_operand_finstructions = ["fadd.s","fsub.s","fmul.s","fdiv.s","fmax.s","fmin.s","feq.s","flt.s","fle.s","fsgnj.s","fsgnjn.s","fsgnjx.s"] three_operand_finstructions = ["fmadd.s","fmsub.s","fnmadd.s","fnmsub.s"] +# Zfa/F: +one_operand_finstructions += ["fround.s", "froundnx.s", "fcvtmod.w.d","fmvh.x.d"] +two_operand_finstructions += ["fmaxm.s", "fminm.s", "fmvp.d.x", "fleq.s", "fltq.s"] +# D one_operand_dinstructions = ["fsqrt.d","fclass.d","fcvt.w.d","fcvt.wu.d","fcvt.d.w","fcvt.d.wu","fcvt.d.s","fcvt.s.d"] two_operand_dinstructions = ["fadd.d","fsub.d","fmul.d","fdiv.d","fmax.d","fmin.d","feq.d","flt.d","fle.d","fsgnj.d","fsgnjn.d","fsgnjx.d"] three_operand_dinstructions = ["fmadd.d","fmsub.d","fnmadd.d","fnmsub.d"] +# Zfa/D: +one_operand_dinstructions += ["fround.d", "froundnx.d"] +two_operand_dinstructions += ["fmaxm.d", "fminm.d", "fleq.d", "fltq.d"] + + +def is_fp_instruction(insn): + ''' + Takes an instruction string (e.g. 'fadd.s') and returns True if it is a FP instruction. + The function is compatible with all existing and future RISC-V ISA extensions. + + :param insn: String representing an instruction (e.g. 'fadd.s', 'lw') + ''' + return type(insn) == str and insn.lower()[0] == 'f' + from riscv_ctg.dsp_function import * twos_xlen = lambda x: twos(x,xlen) @@ -32,9 +51,10 @@ def toint(x: str): return int(x) def get_rm(opcode): - if any([x in opcode for x in - ['fsgnj','fle','flt','feq','fclass','fmv','flw','fsw','fld','fsd','fmin','fmax', - 'fcvt.d.s', 'fcvt.d.w','fcvt.d.wu']]): + insns = ['fsgnj','fle','flt','feq','fclass','fmv','flw','fsw','fld','fsd','fmin','fmax', + 'fcvt.d.s', 'fcvt.d.w','fcvt.d.wu'] + insns += ['fminm', 'fmaxm'] + if any([x in opcode for x in insns]): return [] else: return ['rm_val'] @@ -833,7 +853,13 @@ def eval_inst_coverage(coverpoints,instr): for key in self.op_vars: var_dict[key] = instr[key] - instr_obj = instructionObject(None, instr['inst'], None) + insn = instr['inst'] + # instructionObject() has an outdated list of instructions. + # Let's make it support all FP instructions until this is fixed. + # See https://github.com/riscv-software-src/riscv-isac/issues/69 + if (is_fp_instruction(insn)): + insn = "fadd.s" + instr_obj = instructionObject(None, insn, None) ext_specific_vars = instr_obj.evaluate_instr_var("ext_specific_vars", {**var_dict, 'flen': self.flen, 'iflen': self.iflen}, None, {'fcsr': hex(var_dict.get('fcsr', 0))}) if ext_specific_vars is not None: var_dict.update(ext_specific_vars) diff --git a/sample_cgfs/zfa/fcvtmod.w.d.cgf b/sample_cgfs/zfa/fcvtmod.w.d.cgf new file mode 100644 index 00000000..6d83fdca --- /dev/null +++ b/sample_cgfs/zfa/fcvtmod.w.d.cgf @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fcvtmod.w.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fcvtmod.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen, 64, "fcvt.w.d", 1)': 0 + +fcvtmod.w.d_b22: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fcvtmod.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen, 64, "fcvt.w.d", 1)': 0 + +fcvtmod.w.d_b23: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fcvtmod.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen, 64, "fcvt.w.d", 1)': 0 + +fcvtmod.w.d_b24: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fcvtmod.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen, 64, "fcvt.w.d", 1)': 0 + +fcvtmod.w.d_b27: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fcvtmod.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen, 64, "fcvt.w.d", 1)': 0 + +fcvtmod.w.d_b28: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fcvtmod.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen, 64, "fcvt.w.d", 1)': 0 + +fcvtmod.w.d_b29: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fcvtmod.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen, 64, "fcvt.w.d", 1)': 0 diff --git a/sample_cgfs/zfa/fleq.d.cgf b/sample_cgfs/zfa/fleq.d.cgf new file mode 100644 index 00000000..392b7e31 --- /dev/null +++ b/sample_cgfs/zfa/fleq.d.cgf @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fleq.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fleq.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 64, "fle.d", 2)': 0 + +fleq.d_b19: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fleq.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 64, "fle.d", 2)': 0 diff --git a/sample_cgfs/zfa/fleq.s.cgf b/sample_cgfs/zfa/fleq.s.cgf new file mode 100644 index 00000000..518ff63d --- /dev/null +++ b/sample_cgfs/zfa/fleq.s.cgf @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fleq_b1: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fleq.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 32, "fle.s", 2)': 0 + +fleq_b19: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fleq.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 32, "fle.s", 2)': 0 diff --git a/sample_cgfs/zfa/fltq.d.cgf b/sample_cgfs/zfa/fltq.d.cgf new file mode 100644 index 00000000..1bc2c082 --- /dev/null +++ b/sample_cgfs/zfa/fltq.d.cgf @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fltq.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fltq.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 64, "flt.d", 2)': 0 + +fltq.d_b19: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fltq.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 64, "flt.d", 2)': 0 diff --git a/sample_cgfs/zfa/fltq.s.cgf b/sample_cgfs/zfa/fltq.s.cgf new file mode 100644 index 00000000..8449a73a --- /dev/null +++ b/sample_cgfs/zfa/fltq.s.cgf @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fltq_b1: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fltq.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 32, "flt.s", 2)': 0 + +fltq_b19: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fltq.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 32, "flt.s", 2)': 0 diff --git a/sample_cgfs/zfa/fmaxm.d.cgf b/sample_cgfs/zfa/fmaxm.d.cgf new file mode 100644 index 00000000..1538ea4e --- /dev/null +++ b/sample_cgfs/zfa/fmaxm.d.cgf @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fmaxm.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fmaxm.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 64, "fmax.d", 2)': 0 + +fmaxm.d_b19: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fmaxm.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 64, "fmax.d", 2)': 0 diff --git a/sample_cgfs/zfa/fmaxm.s.cgf b/sample_cgfs/zfa/fmaxm.s.cgf new file mode 100644 index 00000000..08d65acc --- /dev/null +++ b/sample_cgfs/zfa/fmaxm.s.cgf @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fmaxm_b1: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fmaxm.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 32, "fmax.s", 2)': 0 + +fmaxm_b19: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fmaxm.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 32, "fmax.s", 2)': 0 diff --git a/sample_cgfs/zfa/fminm.d.cgf b/sample_cgfs/zfa/fminm.d.cgf new file mode 100644 index 00000000..9f559c81 --- /dev/null +++ b/sample_cgfs/zfa/fminm.d.cgf @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fminm.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fminm.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 64, "fmin.d", 2)': 0 + +fminm.d_b19: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fminm.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 64, "fmin.d", 2)': 0 diff --git a/sample_cgfs/zfa/fminm.s.cgf b/sample_cgfs/zfa/fminm.s.cgf new file mode 100644 index 00000000..0c53416f --- /dev/null +++ b/sample_cgfs/zfa/fminm.s.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fminm_b1: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fminm.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 32, "fmin.s", 2)': 0 + +fminm_b19: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fminm.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 32, "fmin.s", 2)': 0 diff --git a/sample_cgfs/zfa/fmvh.x.d.cgf b/sample_cgfs/zfa/fmvh.x.d.cgf new file mode 100644 index 00000000..f3eb4fdf --- /dev/null +++ b/sample_cgfs/zfa/fmvh.x.d.cgf @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fmvh.x.d_b1: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvh.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fmv.x.d", 1)': 0 + +fmvh.x.d_b22: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvh.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,64, "fmv.x.d", 1)': 0 + +fmvh.x.d_b23: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvh.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,64, "fmv.x.d", 1)': 0 + +fmvh.x.d_b24: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvh.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,64, "fmv.x.d", 1)': 0 + +fmvh.x.d_b27: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvh.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,64, "fmv.x.d", 1)': 0 + +fmvh.x.d_b28: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvh.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,64, "fmv.x.d", 1)': 0 + +fmvh.x.d_b29: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvh.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,64, "fmv.x.d", 1)': 0 diff --git a/sample_cgfs/zfa/fmvp.d.x.cgf b/sample_cgfs/zfa/fmvp.d.x.cgf new file mode 100644 index 00000000..85633d60 --- /dev/null +++ b/sample_cgfs/zfa/fmvp.d.x.cgf @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fmvp.d.x_b25: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvp.d.x: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen, 64, "fmv.d.x", 2)': 0 + +fmvp.d.x_b26: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvp.d.x: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b26(64, "fmv.d.x", 2)': 0 + + diff --git a/sample_cgfs/zfa/fround.d.cgf b/sample_cgfs/zfa/fround.d.cgf new file mode 100644 index 00000000..671392d1 --- /dev/null +++ b/sample_cgfs/zfa/fround.d.cgf @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fround.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fround.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 64, "fsqrt.d", 1)': 0 diff --git a/sample_cgfs/zfa/fround.s.cgf b/sample_cgfs/zfa/fround.s.cgf new file mode 100644 index 00000000..629fea2c --- /dev/null +++ b/sample_cgfs/zfa/fround.s.cgf @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fround_b1: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fround.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 32, "fsqrt.s", 1)': 0 diff --git a/sample_cgfs/zfa/froundnx.d.cgf b/sample_cgfs/zfa/froundnx.d.cgf new file mode 100644 index 00000000..82184436 --- /dev/null +++ b/sample_cgfs/zfa/froundnx.d.cgf @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: BSD-3-Clause + +froundns.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + froundns.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 64, "fsqrt.d", 1)': 0 diff --git a/sample_cgfs/zfa/froundnx.s.cgf b/sample_cgfs/zfa/froundnx.s.cgf new file mode 100644 index 00000000..c2ebe8d5 --- /dev/null +++ b/sample_cgfs/zfa/froundnx.s.cgf @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: BSD-3-Clause + +froundns_b1: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + froundns.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 32, "fsqrt.s", 1)': 0 From 6f9e458f102aa562001ddf0159305140aca45d8a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christoph=20M=C3=BCllner?= Date: Wed, 12 Apr 2023 10:50:20 +0200 Subject: [PATCH 3/8] zfa: Add cgf for fli* instructions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is not much infrastucture support for the fli* instructions. Let's add a cgf that defines the instruction's covergroup with the existing infrastructure support. Signed-off-by: Christoph Müllner --- sample_cgfs/zfa/fli.d.cgf | 9 +++++++++ sample_cgfs/zfa/fli.s.cgf | 9 +++++++++ 2 files changed, 18 insertions(+) create mode 100644 sample_cgfs/zfa/fli.d.cgf create mode 100644 sample_cgfs/zfa/fli.s.cgf diff --git a/sample_cgfs/zfa/fli.d.cgf b/sample_cgfs/zfa/fli.d.cgf new file mode 100644 index 00000000..dea19ac2 --- /dev/null +++ b/sample_cgfs/zfa/fli.d.cgf @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fli.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fli.d: 0 + rd: + <<: *all_fregs diff --git a/sample_cgfs/zfa/fli.s.cgf b/sample_cgfs/zfa/fli.s.cgf new file mode 100644 index 00000000..d16cc2c2 --- /dev/null +++ b/sample_cgfs/zfa/fli.s.cgf @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fli_b1: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fli.s: 0 + rd: + <<: *all_fregs From c42b48ed103d1b8d0676a553cfa39fd7046173d0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christoph=20M=C3=BCllner?= Date: Mon, 22 May 2023 14:03:23 +0200 Subject: [PATCH 4/8] data/fd: fcvtmod: Restrict rounding mode to 'rtz' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The specification of fcvtmod requires a rounding mode of 'rtz'. Let's restrict the generated test cases accordingly. Signed-off-by: Christoph Müllner --- riscv_ctg/data/fd.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv_ctg/data/fd.yaml b/riscv_ctg/data/fd.yaml index 8cdc83b8..700e00ee 100644 --- a/riscv_ctg/data/fd.yaml +++ b/riscv_ctg/data/fd.yaml @@ -2001,7 +2001,7 @@ fcvtmod.w.d: isa: - IFD_Zicsr_Zfa flen: [64] - rm_val_data: '[7,0,1,2,3,4]' + rm_val_data: '[1]' fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' std_op: formattype: 'fsrformat' From d0ba31194d41ea14f9b2cee9df80b53363f9ce53 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christoph=20M=C3=BCllner?= Date: Tue, 16 Jan 2024 23:39:57 +0100 Subject: [PATCH 5/8] froundnx: Fix type in mnemonics name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes a typo in the mnemonics name which prevents the creation of froundnx test cases. Signed-off-by: Christoph Müllner --- sample_cgfs/zfa/froundnx.d.cgf | 4 ++-- sample_cgfs/zfa/froundnx.s.cgf | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/sample_cgfs/zfa/froundnx.d.cgf b/sample_cgfs/zfa/froundnx.d.cgf index 82184436..6fe670b7 100644 --- a/sample_cgfs/zfa/froundnx.d.cgf +++ b/sample_cgfs/zfa/froundnx.d.cgf @@ -1,10 +1,10 @@ # SPDX-License-Identifier: BSD-3-Clause -froundns.d_b1: +froundnx.d_b1: config: - check ISA:=regex(.*I.*D.*Zfa.*) mnemonics: - froundns.d: 0 + froundnx.d: 0 rs1: <<: *all_fregs rd: diff --git a/sample_cgfs/zfa/froundnx.s.cgf b/sample_cgfs/zfa/froundnx.s.cgf index c2ebe8d5..9bcdef9a 100644 --- a/sample_cgfs/zfa/froundnx.s.cgf +++ b/sample_cgfs/zfa/froundnx.s.cgf @@ -1,10 +1,10 @@ # SPDX-License-Identifier: BSD-3-Clause -froundns_b1: +froundnx_b1: config: - check ISA:=regex(.*I.*F.*Zfa.*) mnemonics: - froundns.s: 0 + froundnx.s: 0 rs1: <<: *all_fregs rd: From 2ecac673f045724b7fc4f5b13e8b57412689f865 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christoph=20M=C3=BCllner?= Date: Wed, 6 Mar 2024 22:40:25 +0100 Subject: [PATCH 6/8] fmvp.d.x: Fix type in instruction definition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A typo in the instruction definition prevented the creation of fmvp.d.x test cases. Let's fix that. Signed-off-by: Christoph Müllner --- riscv_ctg/data/fd.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv_ctg/data/fd.yaml b/riscv_ctg/data/fd.yaml index 700e00ee..c8de3bfc 100644 --- a/riscv_ctg/data/fd.yaml +++ b/riscv_ctg/data/fd.yaml @@ -1962,7 +1962,7 @@ fmvh.x.d: fcsr_val:$fcsr*/ TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) -fmvh.d.x: +fmvp.d.x: sig: stride: 2 sz: 'SIGALIGN' From 315be48518b3445a20c9b051056930b7188b0348 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christoph=20M=C3=BCllner?= Date: Tue, 2 Apr 2024 10:09:22 +0200 Subject: [PATCH 7/8] data/fd: fcvtmod: Restrict rounding mode to 'rtz' (again) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The specification of fcvtmod requires a rounding mode of 'rtz'. Recently we have added a commit to restrict the rounding modes accoringly. However, that turned out to be unsufficient. Therefore, this patch directly sets the rounding mode to 'rtz'. As a result this patch only generates 'rtz' test cases. Signed-off-by: Christoph Müllner --- riscv_ctg/data/fd.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv_ctg/data/fd.yaml b/riscv_ctg/data/fd.yaml index c8de3bfc..2235c957 100644 --- a/riscv_ctg/data/fd.yaml +++ b/riscv_ctg/data/fd.yaml @@ -2010,9 +2010,9 @@ fcvtmod.w.d: template: |- // $comment /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; - val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + val_offset:$val_offset; rmval:rtz; correctval:??; testreg:$testreg; fcsr_val:$fcsr*/ - TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + TEST_FPID_OP($inst, $rd, $rs1, rtz, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) fltq.s: sig: From 0e10075c24adc004b2f2713565339d80f934376b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christoph=20M=C3=BCllner?= Date: Wed, 6 Mar 2024 22:43:35 +0100 Subject: [PATCH 8/8] Bump version to 0.12.2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Bump the CTG version to 0.12.2. Signed-off-by: Christoph Müllner --- CHANGELOG.md | 3 +++ riscv_ctg/__init__.py | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index a208451c..71683e36 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -6,6 +6,9 @@ Please note the header `WIP-DEV` is to always remain indicating the changes done Only when a release to the main branch is done, the contents of the WIP-DEV are put under a versioned header while the `WIP-DEV` is left empty +## [0.12.2] - 2024-03-06 +- Add Zfa support. + ## [0.12.1] - 2024-02-27 - Fix test.yml diff --git a/riscv_ctg/__init__.py b/riscv_ctg/__init__.py index 2862388f..29adebcf 100644 --- a/riscv_ctg/__init__.py +++ b/riscv_ctg/__init__.py @@ -4,4 +4,4 @@ __author__ = """InCore Semiconductors Pvt Ltd""" __email__ = 'incorebot@gmail.com' -__version__ = '0.12.1' +__version__ = '0.12.2'