From 91bc5301d01d9da7005e23c23c9be230dea9cecd Mon Sep 17 00:00:00 2001
From: Taichi Ishitani <taichi730@gmail.com>
Date: Fri, 4 Aug 2023 09:47:57 +0900
Subject: [PATCH] divide file list

---
 compile.rb          | 31 ++-----------------------------
 compile_apb.rb      |  4 ++++
 compile_axi4lite.rb |  5 +++++
 compile_core.rb     | 20 ++++++++++++++++++++
 compile_wishbone.rb |  4 ++++
 5 files changed, 35 insertions(+), 29 deletions(-)
 create mode 100644 compile_apb.rb
 create mode 100644 compile_axi4lite.rb
 create mode 100644 compile_core.rb
 create mode 100644 compile_wishbone.rb

diff --git a/compile.rb b/compile.rb
index e6dfad3..16b0ff4 100644
--- a/compile.rb
+++ b/compile.rb
@@ -1,30 +1,3 @@
-if macro_defined? :RGGEN_ENABLE_BACKDOOR
-  file_list 'compile_backdoor.rb', from: :current
+['apb', 'axi4lite', 'wishbone'].each do |protocol|
+  file_list "compile_#{protocol}.rb", from: :current
 end
-
-[
-  'rggen_rtl_pkg.sv',
-  'rggen_or_reducer.sv',
-  'rggen_mux.sv',
-  'rggen_bit_field_if.sv',
-  'rggen_bit_field.sv',
-  'rggen_bit_field_w01trg.sv',
-  'rggen_register_if.sv',
-  'rggen_address_decoder.sv',
-  'rggen_register_common.sv',
-  'rggen_default_register.sv',
-  'rggen_external_register.sv',
-  'rggen_indirect_register.sv',
-  'rggen_bus_if.sv',
-  'rggen_adapter_common.sv',
-  'rggen_apb_if.sv',
-  'rggen_apb_adapter.sv',
-  'rggen_apb_bridge.sv',
-  'rggen_axi4lite_if.sv',
-  'rggen_axi4lite_skid_buffer.sv',
-  'rggen_axi4lite_adapter.sv',
-  'rggen_axi4lite_bridge.sv',
-  'rggen_wishbone_if.sv',
-  'rggen_wishbone_adapter.sv',
-  'rggen_wishbone_bridge.sv'
-].each { |file| source_file file }
diff --git a/compile_apb.rb b/compile_apb.rb
new file mode 100644
index 0000000..32e46a7
--- /dev/null
+++ b/compile_apb.rb
@@ -0,0 +1,4 @@
+file_list   'compile_core.rb', from: :current
+source_file 'rggen_apb_if.sv'
+source_file 'rggen_apb_adapter.sv'
+source_file 'rggen_apb_bridge.sv'
diff --git a/compile_axi4lite.rb b/compile_axi4lite.rb
new file mode 100644
index 0000000..224f992
--- /dev/null
+++ b/compile_axi4lite.rb
@@ -0,0 +1,5 @@
+file_list   'compile_core.rb', from: :current
+source_file 'rggen_axi4lite_if.sv'
+source_file 'rggen_axi4lite_skid_buffer.sv'
+source_file 'rggen_axi4lite_adapter.sv'
+source_file 'rggen_axi4lite_bridge.sv'
diff --git a/compile_core.rb b/compile_core.rb
new file mode 100644
index 0000000..b4dfe86
--- /dev/null
+++ b/compile_core.rb
@@ -0,0 +1,20 @@
+if macro_defined? :RGGEN_ENABLE_BACKDOOR
+  file_list 'compile_backdoor.rb', from: :current
+end
+
+[
+  'rggen_rtl_pkg.sv',
+  'rggen_or_reducer.sv',
+  'rggen_mux.sv',
+  'rggen_bit_field_if.sv',
+  'rggen_bit_field.sv',
+  'rggen_bit_field_w01trg.sv',
+  'rggen_register_if.sv',
+  'rggen_address_decoder.sv',
+  'rggen_register_common.sv',
+  'rggen_default_register.sv',
+  'rggen_external_register.sv',
+  'rggen_indirect_register.sv',
+  'rggen_bus_if.sv',
+  'rggen_adapter_common.sv'
+].each { |file| source_file file }
diff --git a/compile_wishbone.rb b/compile_wishbone.rb
new file mode 100644
index 0000000..a7e15c9
--- /dev/null
+++ b/compile_wishbone.rb
@@ -0,0 +1,4 @@
+file_list   'compile_core.rb', from: :current
+source_file 'rggen_wishbone_if.sv'
+source_file 'rggen_wishbone_adapter.sv'
+source_file 'rggen_wishbone_bridge.sv'