From d26ef01e6e32a4af8bd26f78fec681027b906afa Mon Sep 17 00:00:00 2001
From: Taichi Ishitani <taichi730@gmail.com>
Date: Wed, 26 Apr 2023 22:38:49 +0900
Subject: [PATCH] support bit field label (#8, rggen/rggen#126)

---
 lib/rggen/c_header/bit_field/c_header.rb      |  9 +++++
 .../rggen/c_header/bit_field/c_header_spec.rb | 37 ++++++++++++++++---
 2 files changed, 40 insertions(+), 6 deletions(-)

diff --git a/lib/rggen/c_header/bit_field/c_header.rb b/lib/rggen/c_header/bit_field/c_header.rb
index 3f69d2f..fc6e37a 100644
--- a/lib/rggen/c_header/bit_field/c_header.rb
+++ b/lib/rggen/c_header/bit_field/c_header.rb
@@ -6,6 +6,7 @@
       define_macro("#{full_name}_bit_width", width)
       define_macro("#{full_name}_bit_mask", mask)
       define_offset_macro
+      define_label_macros
     end
 
     private
@@ -27,5 +28,13 @@ def define_offset_macro
         define_macro("#{full_name}_bit_offset", bit_field.lsb)
       end
     end
+
+    def define_label_macros
+      bit_field.labels.each do |label|
+        name = "#{full_name}_#{label.name}"
+        value = hex(label.value, bit_field.width)
+        define_macro(name, value)
+      end
+    end
   end
 end
diff --git a/spec/rggen/c_header/bit_field/c_header_spec.rb b/spec/rggen/c_header/bit_field/c_header_spec.rb
index 04f7109..32a3ad9 100644
--- a/spec/rggen/c_header/bit_field/c_header_spec.rb
+++ b/spec/rggen/c_header/bit_field/c_header_spec.rb
@@ -10,7 +10,7 @@
     RgGen.enable(:register_file, [:name, :offset_address, :size])
     RgGen.enable(:register, [:name, :offset_address, :size, :type])
     RgGen.enable(:register, :type, [:external, :indirect])
-    RgGen.enable(:bit_field, [:name, :bit_assignment, :type, :initial_value, :reference])
+    RgGen.enable(:bit_field, [:name, :bit_assignment, :type, :initial_value, :reference, :labels])
     RgGen.enable(:bit_field, :type, [:rw])
     RgGen.enable(:bit_field, :c_header)
   end
@@ -30,7 +30,17 @@
 
         register do
           name 'register_1'
-          bit_field { bit_assignment lsb: 0, width: 64; type :rw; initial_value 0 }
+          bit_field {
+            bit_assignment lsb: 0, width: 64
+            type :rw
+            initial_value 0
+            labels [
+              { name: 'FOO', value: 0 },
+              { name: 'BAR', value: 2**16 - 1 },
+              { name: 'BAZ', value: 2**32 - 1 },
+              { name: 'QUX', value: 2**64 - 1 }
+            ]
+          }
         end
 
         register do
@@ -66,7 +76,16 @@
             register do
               name 'register_4_2_1'
               size [2, 2]
-              bit_field { name 'bit_field_0'; bit_assignment lsb:  0, width:  1; type :rw; initial_value 0 }
+              bit_field {
+                name 'bit_field_0'
+                bit_assignment lsb:  0, width:  1
+                type :rw
+                initial_value 0
+                labels [
+                  { name: 'FIZZ', value: 0 },
+                  { name: 'BUZZ', value: 1 }
+                ]
+              }
             end
           end
         end
@@ -74,7 +93,7 @@
       c_header.bit_fields
     end
 
-    it 'ビット幅/ビットマスク/ビット位置を示すマクロが定義される' do
+    it 'ビット幅/ビットマスク/ビット位置/ラベルを示すマクロが定義される' do
       expect(c_header[0].macro_definitions).to match([
         match_macro_definition('BLOCK_0_REGISTER_0_BIT_FIELD_0_BIT_WIDTH', 1),
         match_macro_definition('BLOCK_0_REGISTER_0_BIT_FIELD_0_BIT_MASK',  '0x1'),
@@ -96,7 +115,11 @@
       expect(c_header[3].macro_definitions).to match([
         match_macro_definition('BLOCK_0_REGISTER_1_BIT_WIDTH', 64),
         match_macro_definition('BLOCK_0_REGISTER_1_BIT_MASK', '0xffffffffffffffff'),
-        match_macro_definition('BLOCK_0_REGISTER_1_BIT_OFFSET', 0)
+        match_macro_definition('BLOCK_0_REGISTER_1_BIT_OFFSET', 0),
+        match_macro_definition('BLOCK_0_REGISTER_1_FOO', '0x0000000000000000'),
+        match_macro_definition('BLOCK_0_REGISTER_1_BAR', '0x000000000000ffff'),
+        match_macro_definition('BLOCK_0_REGISTER_1_BAZ', '0x00000000ffffffff'),
+        match_macro_definition('BLOCK_0_REGISTER_1_QUX', '0xffffffffffffffff')
       ])
 
       expect(c_header[4].macro_definitions).to match([
@@ -144,7 +167,9 @@
       expect(c_header[10].macro_definitions).to match([
         match_macro_definition('BLOCK_0_REGISTER_FILE_4_REGISTER_FILE_4_2_REGISTER_4_2_1_BIT_FIELD_0_BIT_WIDTH', 1),
         match_macro_definition('BLOCK_0_REGISTER_FILE_4_REGISTER_FILE_4_2_REGISTER_4_2_1_BIT_FIELD_0_BIT_MASK', '0x1'),
-        match_macro_definition('BLOCK_0_REGISTER_FILE_4_REGISTER_FILE_4_2_REGISTER_4_2_1_BIT_FIELD_0_BIT_OFFSET', 0)
+        match_macro_definition('BLOCK_0_REGISTER_FILE_4_REGISTER_FILE_4_2_REGISTER_4_2_1_BIT_FIELD_0_BIT_OFFSET', 0),
+        match_macro_definition('BLOCK_0_REGISTER_FILE_4_REGISTER_FILE_4_2_REGISTER_4_2_1_BIT_FIELD_0_FIZZ', '0x0'),
+        match_macro_definition('BLOCK_0_REGISTER_FILE_4_REGISTER_FILE_4_2_REGISTER_4_2_1_BIT_FIELD_0_BUZZ', '0x1')
       ])
     end
   end