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    27 repositories

    • zephyr

      Public
      Public fork of Zephyr, with the code imported from zephyr_private
      C
      •
      Apache License 2.0
      •6.7k•0•0•2•Updated Nov 29, 2024Nov 29, 2024

    • tinyclunx33_zephyr_example

      Public
      Zephyr running on the tinyCLUNX33 SoM
      C
      •1•2•0•0•Updated Nov 29, 2024Nov 29, 2024

    • pico2-ice

      Public
      MIT License
      •2•2•0•0•Updated Nov 25, 2024Nov 25, 2024

    • pico-ice-sdk

      Public
      Firmware and software support for the pico-ice board
      C
      •
      MIT License
      •14•49•5•2•Updated Nov 24, 2024Nov 24, 2024

    • tinyclunx33_public

      Public
      Documentation for the tinyNX33U SoM and related boards
      Verilog
      •
      Other
      •4•6•4•0•Updated Nov 13, 2024Nov 13, 2024

    • pico-ice

      Public
      Raspberry Pi PICO board + Lattice iCE40 FPGA's
      HTML
      •
      MIT License
      •25•154•3•1•Updated Nov 2, 2024Nov 2, 2024

    • remote_sensing

      Public
      C++
      •0•0•0•0•Updated Jul 12, 2024Jul 12, 2024

    • uf2-utils

      Public
      C
      •
      MIT License
      •1•0•0•0•Updated Jul 11, 2024Jul 11, 2024

    • UPduino-v3.0

      Public
      UPduino 3.0: new 4 layer layout, various other improvements
      HTML
      •
      MIT License
      •39•329•18•1•Updated Jul 6, 2024Jul 6, 2024

    • litex-boards

      Public
      LiteX boards files
      Python
      •
      BSD 2-Clause "Simplified" License
      •289•2•0•1•Updated Jun 26, 2024Jun 26, 2024

    • fpv_hacking

      Public
      Hacking FPV cameras
      MIT License
      •0•0•0•0•Updated Jun 1, 2023Jun 1, 2023

    • pico-ice-lightbox

      Public
      C
      •
      MIT License
      •0•0•0•0•Updated Mar 22, 2023Mar 22, 2023

    • pico-ice-rtl

      Public
      FPGA RTL code for the pico-ice board
      MIT License
      •0•1•0•0•Updated Dec 2, 2022Dec 2, 2022

    • tinyVision_sensai

      Public
      Making Lattice SensAI work properly on tinyVision products
      Verilog
      •
      Other
      •4•10•1•15•Updated Nov 22, 2022Nov 22, 2022

    • Hands-on-FPGA-class

      Public
      SystemVerilog
      •8•42•0•0•Updated Sep 22, 2022Sep 22, 2022

    • tvai-blogs

      Public
      tinyVision blogs on Github pages
      HTML
      •
      MIT License
      •0•0•0•0•Updated Jan 2, 2022Jan 2, 2022

    • himax_adapter

      Public
      UPduino Himax adapter
      MIT License
      •1•0•0•0•Updated Oct 23, 2021Oct 23, 2021

    • Vision-FPGA-SoM

      Public
      tinyVision.ai Vision & Sensor FPGA System on Module
      Verilog
      •
      MIT License
      •12•44•0•0•Updated Jun 23, 2021Jun 23, 2021

    • spi_slave

      Public
      SPI Slave for the UPduino and other FPGA's, includes a SPI Slave to 32 bit Wishbone master core.
      SystemVerilog
      •
      Other
      •2•2•0•0•Updated Mar 3, 2021Mar 3, 2021

    • ice40_power

      Public
      Power analysis of the ICE40UP5K-SG48 devices
      fpgapowerverilogice40lattice-fpga
      Verilog
      •
      MIT License
      •3•22•0•0•Updated Sep 26, 2020Sep 26, 2020

    • upmicro

      Public
      MIT License
      •1•4•0•0•Updated Sep 4, 2020Sep 4, 2020

    • ARMistiCE

      Public
      ARM + iCE40 open source compute platform
      Apache License 2.0
      •0•3•1•0•Updated Apr 7, 2020Apr 7, 2020

    • UPduino-v2.1

      Public
      UPduino
      Verilog
      •
      MIT License
      •8•26•3•0•Updated Mar 30, 2020Mar 30, 2020

    • apio

      Public
      🌱 Open source ecosystem for open FPGA boards
      Python
      •
      GNU General Public License v2.0
      •139•1•0•0•Updated Mar 30, 2020Mar 30, 2020

    • TinyFPGA-Bootloader

      Public
      An open source USB bootloader for FPGAs
      AGS Script
      •
      Apache License 2.0
      •94•1•0•0•Updated Jan 14, 2020Jan 14, 2020

    • tinyVision.ai-landing

      Public
      Landing page for tinyVision.ai Inc.
      HTML
      •
      MIT License
      •1.2k•0•0•0•Updated Aug 14, 2019Aug 14, 2019

    • wb_bfm

      Public
      Wishbone Bus Functional Model
      Verilog
      •5•2•0•0•Updated Apr 27, 2017Apr 27, 2017