Merge pull request #1087 from openhwgroup/main

Update fetch buffer branch from main
openhwgroup · Nov 12, 2024 · 6151cf0 · 6151cf0
2 parents c17e15e + 848c5fe
commit 6151cf0
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Showing 13 changed files with 47 additions and 148 deletions.
diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh
@@ -276,7 +276,7 @@ cd "$RISCV"
 # Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension.
 if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2"; then
     cd "$RISCV"/riscv-gnu-toolchain
-    git reset --hard && git clean -f && git checkout master && git pull
+    git reset --hard && git clean -f && git checkout master && git pull && git submodule update
     ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
     make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
     if [ "$clean" ]; then
@@ -324,8 +324,7 @@ STATUS="qemu"
 cd "$RISCV"
 if git_check "qemu" "https://github.com/qemu/qemu" "$RISCV/include/qemu-plugin.h"; then
     cd "$RISCV"/qemu
-    git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules -j "${NUM_THREADS}"
-    git submodule update --init --recursive
+    git reset --hard && git clean -f && git checkout master && git pull
     ./configure --target-list=riscv64-softmmu --prefix="$RISCV"
     make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]
     make install 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ]

diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh
@@ -10,13 +10,6 @@
 `include "RV32M_coverage.svh"
 `include "RV32F_coverage.svh"
 `include "RV32D_coverage.svh"
-`include "RV32Zba_coverage.svh"
-`include "RV32Zbb_coverage.svh"
-`include "RV32Zbc_coverage.svh"
-`include "RV32Zbs_coverage.svh"
-`include "RV32Zbkb_coverage.svh"
-`include "RV32Zbkc_coverage.svh"
-`include "RV32Zbkx_coverage.svh"
 `include "RV32ZfaF_coverage.svh"
 `include "RV32ZfaD_coverage.svh"
 `include "RV32ZfaZfh_coverage.svh"
@@ -29,11 +22,6 @@
 `include "RV32ZcbZbb_coverage.svh"
 `include "RV32Zcf_coverage.svh"
 `include "RV32Zcd_coverage.svh"
-`include "RV32Zaamo_coverage.svh"
-`include "RV32Zalrsc_coverage.svh"
-`include "RV32Zknd_coverage.svh"
-`include "RV32Zkne_coverage.svh"
-`include "RV32Zknh_coverage.svh"
 
 // Privileged extensions
 `include "ZicsrM_coverage.svh"

diff --git a/config/rv32gc/imperas.ic b/config/rv32gc/imperas.ic
@@ -71,6 +71,7 @@
 
 --override no_pseudo_inst=T # For code coverage, don't produce pseudoinstructions
 
+--override show_c_prefix=T  # Show "c." with compressed instructions
 
 # mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
 #--override cpu/ecode_mask=0x8000000F  # for RV32

diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh
@@ -10,16 +10,9 @@
 `include "RV64M_coverage.svh"
 `include "RV64F_coverage.svh"
 `include "RV64D_coverage.svh"
-`include "RV64Zba_coverage.svh"
-`include "RV64Zbb_coverage.svh"
-`include "RV64Zbc_coverage.svh"
-`include "RV64Zbs_coverage.svh"
-`include "RV64Zbkb_coverage.svh"
-`include "RV64Zbkc_coverage.svh"
-`include "RV64Zbkx_coverage.svh"
 `include "RV64ZfaF_coverage.svh"
-`include "RV32ZfaD_coverage.svh"
-`include "RV32ZfaZfh_coverage.svh"
+`include "RV64ZfaD_coverage.svh"
+`include "RV64ZfaZfh_coverage.svh"
 `include "RV64ZfhD_coverage.svh"
 `include "RV64Zfh_coverage.svh"
 `include "RV64Zicond_coverage.svh"
@@ -29,18 +22,6 @@
 `include "RV64ZcbZbb_coverage.svh"
 `include "RV64ZcbZba_coverage.svh"
 `include "RV64Zcd_coverage.svh"
-`include "RV64Zaamo_coverage.svh"
-`include "RV64Zalrsc_coverage.svh"
-`include "RV64Zknd_coverage.svh"
-`include "RV64Zkne_coverage.svh"
-`include "RV64Zknh_coverage.svh"
-
-
-
-
-
-
-
 
 // Privileged extensions
 `include "RV64VM_coverage.svh"

diff --git a/config/rv64gc/imperas.ic b/config/rv64gc/imperas.ic
@@ -70,6 +70,9 @@
 # For code coverage, don't produce pseudoinstructions
 --override no_pseudo_inst=T 
 
+# Show "c." with compressed instructions 
+--override show_c_prefix=T
+
 # nonratified mnosie register not implemented
 --override cpu/mnoise_undefined=T
 

diff --git a/linux/Makefile b/linux/Makefile
@@ -60,7 +60,7 @@ install: check_write_permissions check_environment
 
 dumptvs: check_write_permissions check_environment
 	$(SUDO) mkdir -p $(RISCV)/linux-testvectors
-	cd testvector-generation; ./genInitMem.sh
+	./genInitMem.sh
 	@echo "Testvectors successfully generated."
 
 generate: $(DTB) $(IMAGES)

diff --git a/linux/bootmem.txt b/linux/bootmem.txt
diff --git a/linux/testvector-generation/genInitMem.sh → linux/genInitMem.sh b/linux/testvector-generation/genInitMem.sh → linux/genInitMem.sh
@@ -46,9 +46,12 @@ echo "Launching QEMU in replay mode!"
 -ex "q"
 
 echo "Changing Endianness"
-make fixBinMem
-./fixBinMem "$rawRamFile" "$ramFile"
-./fixBinMem "$rawBootmemFile" "$bootmemFile"
+# Extend files to 8 byte multiple
+truncate -s %8 "$rawRamFile"
+truncate -s %8 "$rawBootmemFile"
+# Reverse bytes
+objcopy --reverse-bytes=8 -F binary "$rawRamFile" "$ramFile"
+objcopy --reverse-bytes=8 -F binary "$rawBootmemFile" "$bootmemFile"
 rm -f "$rawRamFile" "$rawBootmemFile" "$rawUntrimmedBootmemFile"
 
 echo "genInitMem.sh completed!"

diff --git a/linux/testvector-generation/Makefile b/linux/testvector-generation/Makefile
diff --git a/linux/testvector-generation/fixBinMem.c b/linux/testvector-generation/fixBinMem.c
diff --git a/sim/verilator/Makefile b/sim/verilator/Makefile
@@ -6,7 +6,7 @@ SHELL := /bin/bash
 .PHONY: profile run questa clean
 
 # verilator configurations
-OPT=
+OPT=--assert
 PARAMS?=--no-trace-top
 NONPROF?=--stats
 VERILATOR_DIR=${WALLY}/sim/verilator

diff --git a/src/fpu/postproc/postprocess.sv b/src/fpu/postproc/postprocess.sv
@@ -46,14 +46,14 @@ module postprocess import cvw::*;  #(parameter cvw_t P) (
   input logic  [P.NE+1:0]                  FmaSe,               // the sum's exponent
   input logic  [P.FMALEN-1:0]              FmaSm,               // the positive sum
   input logic                              FmaASticky,          // sticky bit that is calculated during alignment
-  input logic  [$clog2(P.FMALEN+1)-1:0]      FmaSCnt,             // the normalization shift count
+  input logic  [$clog2(P.FMALEN+1)-1:0]    FmaSCnt,             // the normalization shift count
   //divide signals
   input logic                              DivSticky,           // divider sticky bit
   input logic  [P.NE+1:0]                  DivUe,               // divsqrt exponent
   input logic  [P.DIVb:0]                  DivUm,               // divsqrt significand
   // conversion signals
   input logic                              CvtCs,               // the result's sign
-  input logic  [P.NE:0]                    CvtCe,               // the calculated expoent
+  input logic  [P.NE:0]                    CvtCe,               // the calculated exponent
   input logic                              CvtResSubnormUf,     // the convert result is subnormal or underflows
   input logic  [P.LOGCVTLEN-1:0]           CvtShiftAmt,         // how much to shift by
   input logic                              ToInt,               // is fp->int (since it's writting to the integer register)

diff --git a/src/uncore/spi_controller.sv b/src/uncore/spi_controller.sv
@@ -75,7 +75,6 @@ module spi_controller (
   logic ShiftEdgePulse;
   logic SampleEdgePulse;
   logic EndOfFramePulse;
-  logic PhaseOneOffset;
 
   // Frame stuff
   logic [3:0] BitNum;
@@ -93,6 +92,7 @@ module spi_controller (
   logic [7:0] sckcs;
   logic [7:0] intercs;
   logic [7:0] interxfr;
+  logic       Phase;
 
   logic       HasCSSCK;
   logic       HasSCKCS;
@@ -109,7 +109,6 @@ module spi_controller (
 
   logic       DelayIsNext;
   logic       DelayState;       
-
   // Convenient Delay Reg Names
   assign cssck = Delay0[7:0];
   assign sckcs = Delay0[15:8];
@@ -142,6 +141,7 @@ module spi_controller (
 
   assign ContinueTransmit = ~TransmitFIFOEmpty & EndOfFrame;
   assign EndTransmission = TransmitFIFOEmpty & EndOfFrame;
+  assign Phase = SckMode[0];
 
   always_ff @(posedge PCLK) begin
     if (~PRESETn) begin
@@ -152,7 +152,7 @@ module spi_controller (
       DelayCounter <= 0;
     end else begin
       // SCK logic for delay times  
-      if (TransmitStart) begin
+      if (TransmitStart & ~DelayState) begin
         SCK <= 0;
       end else if (SCLKenable) begin
         SCK <= ~SCK;
@@ -161,19 +161,21 @@ module spi_controller (
       // Counter for all four delay types
       if (DelayState & SCK & SCLKenable) begin
         DelayCounter <= DelayCounter + 8'd1;
-      end else if (SCLKenable & EndOfDelay) begin
+      end else if ((SCLKenable & EndOfDelay) | Transmitting) begin
         DelayCounter <= 8'd0;
       end
 
       // SPICLK Logic
-      if (TransmitStart) begin
+
+      if (TransmitStart & ~DelayState) begin
         SPICLK <= SckMode[1];
-      end else if (SCLKenable & Transmitting) begin
-        SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1];
+      end else if (SCLKenable) begin
+        if (Phase & (NextState == TRANSMIT)) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1];
+        else if (Transmitting) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1];
       end
 
       // Reset divider 
-      if (SCLKenable | TransmitStart | ResetSCLKenable) begin
+      if (SCLKenable | (TransmitStart & ~DelayState) | ResetSCLKenable) begin
         DivCounter <= 12'b0;
       end else begin
         DivCounter <= DivCounter + 12'd1;
@@ -208,35 +210,18 @@ module spi_controller (
   always_ff @(posedge ~PCLK) begin
     if (~PRESETn | TransmitStart) begin
       ShiftEdge <= 0;
-      PhaseOneOffset <= 0;
       SampleEdge <= 0;
       EndOfFrame <= 0;
-      end else begin
-        PhaseOneOffset <= (PhaseOneOffset == 0) ? Transmitting & SCLKenable : ~EndOfFrame;
-        case(SckMode)
-        2'b00: begin
-          ShiftEdge <= SPICLK & ShiftEdgePulse;
-          SampleEdge <= ~SPICLK & SampleEdgePulse;
-          EndOfFrame <= SPICLK & EndOfFramePulse;
-        end
-        2'b01: begin
-          ShiftEdge <= ~SPICLK & ShiftEdgePulse & PhaseOneOffset;
-          SampleEdge <= SPICLK & SampleEdgePulse;
-          EndOfFrame <= ~SPICLK & EndOfFramePulse;
-        end
-        2'b10: begin
+      end else if (^SckMode) begin
           ShiftEdge <= ~SPICLK & ShiftEdgePulse;
           SampleEdge <= SPICLK & SampleEdgePulse;
           EndOfFrame <= ~SPICLK & EndOfFramePulse;
-        end
-        2'b11: begin
-          ShiftEdge <= SPICLK & ShiftEdgePulse & PhaseOneOffset;
+      end else begin 
+          ShiftEdge <= SPICLK & ShiftEdgePulse;
           SampleEdge <= ~SPICLK & SampleEdgePulse;
           EndOfFrame <= SPICLK & EndOfFramePulse;
-        end
-      endcase
-    end
-  end
+      end 
+    end 
 
   // Logic for continuing to transmit through Delay states after end of frame
   assign NextEndDelay = NextState == SCKCS | NextState == INTERCS | NextState == INTERXFR;
@@ -263,33 +248,27 @@ module spi_controller (
       TRANSMIT: begin // TRANSMIT case --------------------------------
         case(CSMode)
           AUTOMODE: begin  
-            if (EndTransmission) NextState = INACTIVE;
-            else if (EndOfFrame) NextState = SCKCS;
+            if (EndTransmission & ~HasSCKCS) NextState = INACTIVE;
+            else if (EndOfFrame & HasSCKCS) NextState = SCKCS;
+            else if (EndOfFrame & ~HasSCKCS) NextState = INTERCS;
             else NextState = TRANSMIT;
           end
           HOLDMODE: begin  
-            if (EndTransmission) NextState = HOLD;  
-            else if (ContinueTransmit & HasINTERXFR) NextState = INTERXFR;
+            if (EndOfFrame & HasINTERXFR) NextState = INTERXFR;
+            else if (EndTransmission) NextState = HOLD;
             else NextState = TRANSMIT;
           end
           OFFMODE: begin
-            if (EndTransmission) NextState = INACTIVE;
-            else if (ContinueTransmit & HasINTERXFR) NextState = INTERXFR;
+            if (EndOfFrame & HasINTERXFR) NextState = INTERXFR;
+            else if (EndTransmission) NextState = HOLD;
             else NextState = TRANSMIT;
           end
           default: NextState = TRANSMIT;
         endcase
       end
       SCKCS: begin // SCKCS case --------------------------------------
         if (EndOfSCKCS) begin
-          if (~TransmitRegLoaded) begin
-            // if (CSMode == AUTOMODE) NextState = INACTIVE;
-            if (CSMode == HOLDMODE) NextState = HOLD;
-            else NextState = INACTIVE;
-          end else begin
-            if (HasINTERCS) NextState = INTERCS;
-            else NextState = TRANSMIT;
-          end
+          NextState = INTERCS;
         end else begin
           NextState = SCKCS;
         end
@@ -303,15 +282,18 @@ module spi_controller (
       end
       INTERCS: begin // INTERCS case ----------------------------------
         if (EndOfINTERCS) begin
-          if (HasCSSCK) NextState = CSSCK;
-          else NextState = TRANSMIT;
+          if (TransmitRegLoaded) begin
+            if (HasCSSCK) NextState = CSSCK;
+            else NextState = TRANSMIT;
+          end else NextState = INACTIVE;
         end else begin
           NextState = INTERCS;  
         end
       end
       INTERXFR: begin // INTERXFR case --------------------------------
         if (EndOfINTERXFR) begin
-          NextState = TRANSMIT;
+          if (TransmitRegLoaded)  NextState = TRANSMIT;
+          else NextState = HOLD;
         end else begin
           NextState = INTERXFR;  
         end