Merge branch 'master' into doc_irq

openhwgroup · Nov 21, 2024 · ef0f4a2 · ef0f4a2
2 parents 68f4bdc + c389382
commit ef0f4a2
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diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -181,9 +181,13 @@ smoke-bench:
     DASHBOARD_JOB_CATEGORY: "Performance"
     SPIKE_TANDEM: 1
     BENCH: "dhrystone"
+  parallel:
+    matrix:
+      - DV_TARGET: "cv32a60x"
+      - DV_TARGET: "cv32a65x"
   script:
     - bash verif/regress/"$BENCH"_smoke.sh --no-print
-    - python3 .gitlab-ci/scripts/report_benchmark.py --"$BENCH"_cv32a65x verif/sim/out_*/vcs-uvm_sim/"$BENCH"_main.*.log
+    - python3 .gitlab-ci/scripts/report_benchmark.py --"$BENCH"_"$DV_TARGET" verif/sim/out_*/vcs-uvm_sim/"$BENCH"_main.*.log
 
 smoke-hwconfig:
   extends:
@@ -324,16 +328,16 @@ benchmarks:
     matrix:
       - BENCH: "dhrystone"
         ISSUE: "single"
-        DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"]
+        DV_HWCONFIG_OPTS: ["cv32a60x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"]
       - BENCH: "dhrystone"
         ISSUE: "dual"
-        DV_HWCONFIG_OPTS: ["cv32a65x SuperscalarEn=1 IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"]
+        DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"]
       - BENCH: "coremark"
         ISSUE: "single"
-        DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"]
+        DV_HWCONFIG_OPTS: ["cv32a60x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"]
       - BENCH: "coremark"
         ISSUE: "dual"
-        DV_HWCONFIG_OPTS: ["cv32a65x SuperscalarEn=1 IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"]
+        DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"]
   script:
     - bash verif/regress/"$BENCH".sh
     - python3 .gitlab-ci/scripts/report_benchmark.py --"$BENCH"_"$ISSUE" verif/sim/out_*/vcs-uvm_sim/"$BENCH"_main.*.log
@@ -376,7 +380,6 @@ riscv-tests-v:
     DV_SIMULATORS: "vcs-testharness,spike"
     DV_TARGET: cv64a6_imafdc_sv39
     DV_TESTLISTS: "../tests/testlist_riscv-tests-$DV_TARGET-v.yaml"
-    SPIKE_TANDEM: 1
   script: source verif/regress/dv-riscv-tests.sh
   after_script: *simu_after_script
 
@@ -535,6 +538,7 @@ simu-gate:
     SIMU_PERIOD: "20"  # 50 Mhz
     PERIOD: "15"  # 66 Mhz
   script:
+    - mkdir -p artifacts/{reports,logs}
     - git -C verif/core-v-verif fetch --unshallow
     - !reference [.copy_spike_artifacts]
     - echo $PERIOD
@@ -550,12 +554,15 @@ simu-gate:
     - mkdir -p pd/synth/${TOP}_${DV_TARGET}/outputs/
     - export DV_SIMULATORS="spike"
     - bash verif/regress/${PROG_NAME}.sh
-    - cp verif/sim/out_*/directed_c_tests/*.o verif/sim/testelf.o
+    - cp verif/sim/out_*/directed_tests/*.o verif/sim/testelf.o
     - python3 ${SYNTH_SCRIPT_PATH}/scharm -p configs/modules/CVA6.yml --runner=True --compaign="simu-gate" --name=testelf
     - grep "Simulation terminated" verif/sim/out_*/*/*.log.iss
     - mv ${SYNTH_SCRIPT_PATH}/artifacts/ artifacts/artifacts_gate/
     - rm artifacts/artifacts_gate/*/build/*.fsdb
-  after_script: *simu_after_script
+    - mkdir -p verif/sim/out_reports
+    - mkdir -p artifacts/sim_artifacts
+    - for i in verif/sim/out*/vcs-uvm-gate*/*; do cp $i $(dirname $(dirname $i))/vcs-uvm_sim/gate.$(basename $i); done
+    - python3 .gitlab-ci/scripts/report_tandem.py verif/sim/out*/vcs-uvm_sim
 
 fpga-boot:
   extends:

diff --git a/.gitlab-ci/expected_synth.yml b/.gitlab-ci/expected_synth.yml
@@ -1,2 +1,2 @@
 cv32a65x:
-  gates: 142603
+  gates: 178869
diff --git a/.gitlab-ci/scripts/report_benchmark.py b/.gitlab-ci/scripts/report_benchmark.py
@@ -23,7 +23,8 @@
     "dhrystone_single": 25019,
     "coremark_dual": 1017451,
     "coremark_single": 1308656,
-    "dhrystone_cv32a65x": 39994,
+    "dhrystone_cv32a65x": 32566,
+    "dhrystone_cv32a60x": 39994,
 }
 
 for arg in sys.argv[1:]:

diff --git a/.gitlab-ci/scripts/report_tandem.py b/.gitlab-ci/scripts/report_tandem.py
@@ -27,8 +27,10 @@ def main():
 
 
 def check_provided_args():
-    if len(sys.argv) != 2 or not os.path.exists(sys.argv[1]):
-        print("Usage : python report_tandem.py path/to/log/dir", file=sys.stderr)
+    if len(sys.argv) != 2: 
+        sys.exit("Usage : python report_tandem.py path/to/log/dir")
+
+    if not os.path.exists(sys.argv[1]):
         sys.exit("No valid log directory provided!")
 
     if len(list(glob.iglob(sys.argv[1] + "/*.yaml"))) == 0:

diff --git a/config/gen_from_riscv_config/cv32a60x/linker/link.ld b/config/gen_from_riscv_config/cv32a60x/linker/link.ld
@@ -0,0 +1,82 @@
+/*======================================================================*/
+/* Proxy kernel linker script                                           */
+/*======================================================================*/
+/* This is the linker script used when building the proxy kernel. */
+
+/*----------------------------------------------------------------------*/
+/* Setup                                                                */
+/*----------------------------------------------------------------------*/
+
+/* The OUTPUT_ARCH command specifies the machine architecture where the
+   argument is one of the names used in the BFD library. More
+   specifically one of the entires in bfd/cpu-mips.c */
+
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+/*----------------------------------------------------------------------*/
+/* Sections                                                             */
+/*----------------------------------------------------------------------*/
+
+SECTIONS
+{
+
+  /* text: test code section */
+  . = 0x80000000;
+  _start_text = .;
+  .text.init : { *(.text.init) }
+
+  . = ALIGN(0x1000);
+  .tohost : { *(.tohost) }
+
+  . = ALIGN(0x1000);
+  .uvmif : { *(.uvmif) }
+
+  . = ALIGN(0x1000);
+  .text : { *(.text) }
+  . = ALIGN(0x1000);
+  .text.startup : { *(.text.startup) }
+  . = ALIGN(0x1000); 
+  _end_text = .;
+  . = ALIGN(0x1000);
+  .rodata : { *(.rodata*)}
+  . = ALIGN(0x8);
+  . = ALIGN(0x1000);
+  .page_table : { *(.page_table) }
+  .user_stack : { *(.user_stack) }
+  .kernel_data : { *(.kernel_data) }
+  .kernel_stack : { *(.kernel_stack) }
+
+  /* data segment */
+  .data : { *(.data) }
+
+  .sdata : {
+    __global_pointer$ = . + 0x800;
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+
+  /* bss segment */
+  .sbss : {
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+  }
+  .bss : { *(.bss) }
+
+  /* thread-local data segment */
+  .tdata :
+  {
+    _tdata_begin = .;
+    *(.tdata)
+    _tdata_end = .;
+  }
+  .tbss :
+  {
+    *(.tbss)
+    _tbss_end = .;
+  }
+
+  /* End of uninitalized data segement */
+  _end = .;
+}
+
diff --git a/config/gen_from_riscv_config/cv32a60x/spike/spike.yaml b/config/gen_from_riscv_config/cv32a60x/spike/spike.yaml
@@ -0,0 +1,54 @@
+spike_param_tree:
+  bootrom: true
+  bootrom_base: 65536
+  bootrom_size: 4096
+  dram: true
+  dram_base: 2147483648
+  dram_size: 1073741824
+  generic_core_config: false
+  max_steps: 200000
+  max_steps_enabled: false
+  isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs
+  priv: M
+  core_configs:
+    -
+      isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs
+      extensions: cv32a60x,cvxif
+      boot_addr: 2147483648
+      marchid_override_mask: 0xFFFFFFFF
+      marchid_override_value: 0x3
+      misa_write_mask: 0x0
+      pmp_granularity: 8
+      pmpaddr0: 0
+      pmpcfg0: 0
+      pmpregions_max: 64
+      pmpregions_writable: 8
+      priv: M
+      status_fs_field_we: false
+      status_fs_field_we_enable: false
+      status_vs_field_we: false
+      status_vs_field_we_enable: false
+      mstatus_write_mask: 136
+      mstatus_override_mask: 6144
+      mie_write_mask: 0x00000880
+      mie_override_mask: 0xfffff77f
+      mie_override_value: 0x00000000
+      mip_write_mask: 0x00000000
+      mip_override_mask: 0xfffff77f
+      mip_override_value: 0x00000000
+      mtval_write_mask: 0
+      tinfo_accessible: 0
+      mscontext_accessible: 0
+      mcontext_accessible: 0
+      tdata1_accessible: 0
+      tdata2_accessible: 0
+      tdata3_accessible: 0
+      tselect_accessible: 0
+      mhartid: 0
+      mvendorid_override_mask : 0xFFFFFFFF
+      mvendorid_override_value: 1538
+      csr_counters_injection: true
+      interrupts_injection: true
+      unified_traps: true
+      mcycleh_implemented: false
+      mhpmevent31_implemented: false
diff --git a/config/gen_from_riscv_config/cv32a65x/spike/spike.yaml b/config/gen_from_riscv_config/cv32a65x/spike/spike.yaml
@@ -18,6 +18,7 @@ spike_param_tree:
       marchid_override_mask: 0xFFFFFFFF
       marchid_override_value: 0x3
       misa_write_mask: 0x0
+      pmp_granularity: 8
       pmpaddr0: 0
       pmpcfg0: 0
       pmpregions_max: 64

diff --git a/config/riscv-config/cv32a65x/generated/isa_gen.yaml b/config/riscv-config/cv32a65x/generated/isa_gen.yaml
@@ -21,7 +21,7 @@ hart0:
     supported_xlen:
       - 32
     physical_addr_sz: 32
-    pmp_granularity: 4
+    pmp_granularity: 8
     misa:
         reset-val: 0x40001106
         rv32:

diff --git a/config/riscv-config/cv32a65x/spec/isa_spec.yaml b/config/riscv-config/cv32a65x/spec/isa_spec.yaml
@@ -20,7 +20,7 @@ hart0: &hart0
   User_Spec_Version: '2.3'
   supported_xlen: [32]
   physical_addr_sz: 32
-  pmp_granularity: 4
+  pmp_granularity: 8
   misa:
    reset-val: 0x40001106 # B: bit 1, C: bit 2, I = bit 8, M = bit 12, Z = bit 25
    rv32:

diff --git a/core/cache_subsystem/axi_adapter.sv b/core/cache_subsystem/axi_adapter.sv
@@ -201,7 +201,7 @@ module axi_adapter #(
               end else begin
                 // bursts of AMOs unsupported
                 assert (amo_i == ariane_pkg::AMO_NONE)
-                else $fatal("Bursts of atomic operations are not supported");
+                else $fatal(1, "Bursts of atomic operations are not supported");
 
                 axi_req_o.aw.len = BURST_SIZE[7:0];  // number of bursts to do
                 axi_req_o.w.data = wdata_i[0];
@@ -232,7 +232,7 @@ module axi_adapter #(
               gnt_o = axi_resp_i.ar_ready;
               if (type_i != ariane_pkg::SINGLE_REQ) begin
                 assert (amo_i == ariane_pkg::AMO_NONE)
-                else $fatal("Bursts of atomic operations are not supported");
+                else $fatal(1, "Bursts of atomic operations are not supported");
 
                 axi_req_o.ar.len = BURST_SIZE[7:0];
                 cnt_d = BURST_SIZE[ADDR_INDEX-1:0];

diff --git a/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv b/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv
@@ -407,13 +407,13 @@ module cva6_hpdcache_subsystem_axi_arbiter
   //  pragma translate_off
   initial
     assert (CVA6Cfg.MEM_TID_WIDTH <= AxiIdWidth)
-    else $fatal("MEM_TID_WIDTH shall be less or equal to AxiIdWidth");
+    else $fatal(1, "MEM_TID_WIDTH shall be less or equal to AxiIdWidth");
   initial
     assert (CVA6Cfg.AxiDataWidth <= CVA6Cfg.ICACHE_LINE_WIDTH)
-    else $fatal("AxiDataWidth shall be less or equal to the width of a Icache line");
+    else $fatal(1, "AxiDataWidth shall be less or equal to the width of a Icache line");
   initial
     assert (CVA6Cfg.AxiDataWidth <= CVA6Cfg.DCACHE_LINE_WIDTH)
-    else $fatal("AxiDataWidth shall be less or equal to the width of a Dcache line");
+    else $fatal(1, "AxiDataWidth shall be less or equal to the width of a Dcache line");
   //  pragma translate_on
   //  }}}