diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index acb725d606..b59aa34359 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -297,10 +297,9 @@ fpga-build:
     - source ./verif/sim/setup-env.sh
     - mkdir -p artifacts/logs
     - make fpga target=$TARGET &> artifacts/logs/logfile.log
-    - tail -20 artifacts/logs/logfile.log > artifacts/logs/logfile.log.tail
     - mkdir -p artifacts/reports
     - mv corev_apu/fpga/work-fpga/ariane_xilinx.bit artifacts/ariane_xilinx_$TARGET.bit
-    - python3 .gitlab-ci/scripts/report_fpga.py corev_apu/fpga/reports/ariane.utilization.rpt artifacts/logs/logfile.log.tail
+    - python3 .gitlab-ci/scripts/report_fpga.py corev_apu/fpga/reports/ariane.utilization.rpt
 
 .regress_test:
   stage: heavy tests
diff --git a/.gitlab-ci/scripts/report_fpga.py b/.gitlab-ci/scripts/report_fpga.py
index 88a12e9e48..a1f48c7fa6 100644
--- a/.gitlab-ci/scripts/report_fpga.py
+++ b/.gitlab-ci/scripts/report_fpga.py
@@ -15,9 +15,6 @@
 with open(str(sys.argv[1]), "r") as f:
     log = f.read()
 
-with open(str(sys.argv[2]), "r") as f:
-    outputlog = f.read()
-
 pattern = re.compile(
     "\|(?P<ind> +)(?P<Instance>[\w()\[\].]+) +\| +(?P<Module>[\w()\[\].]+) \| +(?P<TotalLUTs>\d+) \| +(?P<LogicLUTs>\d+) \| +(?P<LUTRAMs>\d+) \| +(?P<SRLs>\d+) \| +(?P<FFs>\d+) \| +(?P<RAMB36>\d+) \| +(?P<RAMB18>\d+) \| +(?P<DSP48Blocks>\d+) \|"
 )
@@ -50,8 +47,5 @@
             i["DSP48Blocks"] + " DSP48Blocks",
         )
 
-log_metric = rb.LogMetric("Last lines of logfile")
-log_metric.values = outputlog.splitlines()
-
-report.add_metric(metric, log_metric)
+report.add_metric(metric)
 report.dump()